Abstract: Circuit and methods accelerate jitter tracking and reduce or eliminate the processing delay of loop filtering in timing recovery. A timing recovery circuit incorporates a phase tracking accelerator and a frequency tracking accelerator to compute the phase and frequency variation of incoming signal during the delay period of a loop filter. In one embodiment, phase and frequency tracking accelerators are realized in direct forms. In another embodiment, pre-computed look-up tables are employed in phase and frequency tracking accelerators to ease timing closure and simplify accelerator circuit. The phase tracking accelerator and the frequency tracking accelerator together compensate the estimated phase at the output of a loop filter and eliminate the processing delay of loop filtering. The loop bandwidth and jitter tolerance of timing recovery are increased.

Abstract: An enhanced base station and clock synchronization method are provided. The method includes scanning to discover a satellite transmitting a satellite signal and a master base station providing clock synchronization signal, entering, when a satellite having a signal that fulfills predetermined conditions is found, a master mode for receiving the satellite signal to acquire clock synchronization and transmitting a clock synchronization signal to at least one slave base station, and entering, when no satellite having a signal that fulfills the predetermined conditions is found, a slave mode for receiving the clock synchronization signal from the master base station to acquire clock synchronization. The method allows the base station to switch between the master and slave modes dynamically according to variation of the communication environment, resulting in efficient clock synchronization.

Abstract: Techniques are described herein that synchronize media streams using time signal(s) from an independent time source. An independent time source is a time source that is independent from (i.e., that is not connected to) an asynchronous data network via which the media streams are transferred. In accordance with the techniques described herein, media server(s) transfer the media streams to client(s) via an asynchronous data network. The independent time source provides the time signal(s) to the media server(s) and/or the client(s). If the time signal(s) are provided to the media server(s), the media server(s) may provide timing information that is based on the timing signal(s) to the client(s). The client(s) use the timing information from the media server(s) and/or the timing signal(s) from the timing source to synchronize the media streams.

Abstract: A clock generation device provided for a transmitter is provided and comprises a clock generator, a calculator and a first phase locked loop (PLL) circuit. The clock generator generates a first clock signal. The calculator calculates a frequency difference between the first and second clock signals. The first PLL circuit generates an output clock signal according to a first reference clock signal related to the first clock signal, and a frequency of the output clock signal is changed according to the frequency difference. The transmitter transmits data according to the output clock signal.

Abstract: A method, telecommunication apparatus, and electronic device for detecting a status of a radio link are disclosed. A transceiver 302 may maintain a radio link with a network base station 104. A processor 304 may map channel state information to a synchronization status associated with the radio link based on the received signal and determine the synchronization status via a block error rate estimate in the radio link based on the channel state information.

Abstract: A data reception unit 21 of a reception device 20n receives calibration data to detect a data reception state or a clock reception state in the reception device 20n from a data transmission unit 11 of a transmission device 10. A decoder unit 24 causes a transmission unit 26 to send out calibration sample data that a sampler unit 23 obtained by sampling calibration data to the transmission device 10. A control unit 15 of the transmission device 10 detects a data reception state or a clock reception state in the reception device 20n based on calibration sample data received from the reception device 20n and controls the data transmission unit 11 and a clock transmission unit 12 based on the detection result.

Abstract: Aspects of the disclosure provide a method for detecting marks. The method includes receiving a data signal from a channel. Further, the method includes matching the data signal to a template that corresponds to a predetermined pattern transmitted over the channel to detect marks, prior to decoding the data signal into a decoded bit stream.

Abstract: A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

Abstract: A method, telecommunication apparatus, and electronic device detect a status of a radio link. A transceiver 302 may receive a reference signal transmitted from a base station 104. A processor 304 may assume a transmission of a codeword of a first payload type from the base station and may determine a synchronization status based on the received reference signal and based on the assumed transmission of the codeword of the first payload type from the base station.

Abstract: A method for synchronizing two connection nodes by a reception node of the connection nodes with a clock data recovery circuit that generates a synchronization clock from input data. The method includes performing a synchronization process to establish synchronization between the connection nodes based on the synchronization clock, performing a connection failure process when the synchronization is not established when a first time elapses after receiving the input data, correcting the clock data recovery circuit when the synchronization is not established when a second time elapses after receiving the input data, wherein the second time is shorter than the first time, and performing a resynchronization process to establish synchronization between the connection nodes based on a synchronization clock, which is generated by the clock data recovery circuit that has been corrected, before the first time elapses and after the second time elapses.

Abstract: A network entity and computer program for detecting occurrence of transmission resynchronizations in a network carrying packets subject to variable delays, and adaptively varying the play out time of data packets. The method may include that the packets are received at a network entity and forwarded by delaying them by a jitter protection time, and determining for a predetermined time period a set of arrival time jitter values. A peak to peak value may be determined indicating the largest difference among the values included in the determined set of arrival time jitter values and detecting an out of range condition. The peak to peak value may be compared with the jitter protection time when the out of range condition is detected and detecting that a resynchronization occurred on the basis of the comparing.

Abstract: A continuous-rate clock and data recovery circuit includes a delay locked loop with a first integrator and a phase locked loop with a separate integrator. The delay locked loop and the phase locked loop are in a dual loop architecture. The first integrator is a digital accumulator that wraps upon exceeding a maximum or minimum value. The second integrator is a digital accumulator that saturates at its maximum or minimum value.

Abstract: Certain aspects of a method and system for satellite communication are disclosed. Aspects of one method may include a receiver that handles digital broadcasting. The receiver may be enabled to dynamically vary spacing between two or more pilots and/or the size of one or more pilots within at least one frame based on a determined symbol rate. The size of each of a plurality of received programs may be determined and the spacing between two or more pilots may be dynamically varied based on the determined size of each of the plurality of received programs.

Abstract: A clock and data recovery circuit injects a noise waveform into the control loop to offset the data sampling point artificially in order to induce errors. The amplitude of the injected waveform can be varied to ascertain the effect on the bit error rate (BER) so as to be able to evaluate the temporal noise margin.

Abstract: A system may include a bus carrying signals, a frame pulse generator generating a generally periodic frame pulse signal having timing boundaries delineating consecutive timing periods and a frame pulse enable signal active for a portion of each timing period proximate to the timing boundaries and inactive otherwise, a first controlled buffer driving the frame pulse signal on the bus during durations in which the frame pulse enable signal is active to generate a modified frame pulse, a reference clock controller receiving the modified frame pulse via the bus and generating a reference clock enable signal in response to presence of the modified frame pulse, a reference clock generator generating a generally periodic reference clock signal, and a second controlled buffer driving the reference clock signal on the bus during durations in which the reference clock enable signal is active to generate a modified reference clock.

Abstract: A device and method for synchronization of data for audio and/or video between a memory of a device in a motor vehicle and an external device is provided. The method comprises synchronizing the data between the memory and the external device through a radio connection through a synchronization unit. The method further comprises outputting a status signal (St) based on a charge state (C) of the first power source by a monitoring unit to the synchronization unit and signaling from the synchronization unit to the external device an interruption of the synchronization due to low charge level. The method further comprises terminating the synchronization of the data based on the status signal (St) indicating that the charge state (C) of the first power source is below a threshold (th) and/or that a second power source for charging of the first power source is disconnected from the first power source.

Abstract: Briefly, some embodiments of the invention may provide devices, systems and methods of in-phase and quadrature mismatch analysis and correction. For example, a method in accordance with an embodiment of the invention may include re-encoding an estimated symbol of an input signal having an in-phase component and a quadrature component, based on an analysis of a mismatch between said in-phase component and said quadrature component.

Abstract: A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

Abstract: In a wireless mobile communications system, a method of transmitting and receiving radio access information that allows a faster and an efficient way of establishing a radio connection between a terminal and a target base station while performing a handover for the terminal to a cell of the target base station. The network transmits in advance, the radio access information and the like, to the terminal so that the terminal can be connected with the target cell in a faster manner which minimizes the total time for the handover process.

Abstract: Disclosed herein is a synchronization circuit including: a first phase-locked loop circuit; a second phase-locked loop circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; and a control circuit.

Abstract: A method of serializing a data stream includes passing a series of data words from a source in a first clock domain to a serializer in a second clock domain and passing valid signals from the source to the serializer indicating when each of the data words is available from the source. The serializer divides each of the data words into a plurality of portions for serial transmission. The method also includes synchronizing the serializer and the source based on the first of the valid signals.

Abstract: A system for synchronizing the operation of a circuit with a control signal includes synchronization flip-flops operating in cascade for receiving a control signal to be synchronized and providing a corresponding control signal synchronized with a clock signal, and a circuit including a finite state machine for receiving the clock signal having state flip-flops for storing the current state of the finite state machine, wherein a last synchronization flip-flop includes one of the state flip-flops.

Abstract: A receiving apparatus includes a first receiving circuit that receives an input signal based on a clock signal, and outputs a first output signal, a second receiving circuit that receives the input signal based on the clock signal, and outputs a second output signal, and a comparison circuit that compares value of the first output signal outputted by the first receiving circuit and value of the second output signal outputted by the second receiving circuit.

Abstract: A method for relaying and forwarding feedback information in hybrid automatic repeat request scenario is provided, wherein the method for sending feedback information includes that: a relay station receives a resource allocation message; the relay station determines the time of sending the feedback information according to the resource allocation message, and sends the corresponding feedback information when the feedback time arrives. The processes of triggering the relay station to perform feedback or sending in multiple HARQ scenarios such as initial transmission and retransmission of downlink and uplink, and uplink feedback loss of subordinate node etc. are integrally and uniformly defined according to the present invention.

Abstract: A serial communication system includes a receiver with an amplitude monitor. The amplitude monitor compares the input signal with a reference level in response to a sample clock. The sample clock is periodically phase shifted with respect to the incoming data so the amplitude monitor is sure to sample an incoming data eye at or near the peak amplitude over a selected sample period. The amplitude detector notes the detection of an input signal if the input signal surpasses the reference level for any sample phase. The amplitude monitor experiments with different sample-clock phases over a number of data symbols, but is capable of measuring amplitude fast enough to resolve amplitude-based signals used for rate negotiation.

Abstract: Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock switching in a clock selector operable to switch between clock signals including a first clock signal based on first and second clock-stop-permission signals and a clock-resume-permission signal. The clock-control-signal-generation circuit includes: a before-switching clock processing unit; and an after-switching clock processing unit. In each of the before-and after-switching clock processing units, the high-frequency clock processing subunit and the low-frequency clock processing subunit take partial charges of processing of clock signals involved in the switching respectively, whereby the processing is speeded up.

Abstract: A method and system for reducing power consumption of OFDM (Orthogonal Frequency Division Multiplexing) signal synchronization circuit comprises a sync setting, a sync controller, a sync pipeline and a data corrector. The sync setting dynamically changes correlation data sample rate based on synchronization statuses and results. The sync controller controls and schedules frame and symbol synchronizations, and turns on and off the sync pipeline based on synchronization activities. The sync pipeline integrates frame and symbol synchronization operations, synchronizes receiving signal with scalable synchronization window, synchronization sequence length, synchronization delay and variable data sample rate. Data corrector adjusts input data with coarse timing and fine frequency offsets estimated in sync pipeline, and generates corrected output data for further processing. By using the above techniques, the power consumption of signal synchronization circuit is reduced.

Abstract: A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from ?/2, ?/4, ?/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of ?/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

Abstract: The present invention relates to an apparatus and method for correcting synchronization errors, which involve correcting synchronization errors occurring between video signals and audio signals when multiple videos are combined. The apparatus and method of the present invention involve: storing synchronization errors between an initial video signal and an initial audio signal of each video to be combined when combining different pieces of video content; and combining multiple pieces of video content such that the initial synchronization error which is set to synchronize existing video signals with existing audio signals can be maintained when combining multiple pieces of video content. The apparatus and method of the present invention enable the drawbacks of conventional techniques, i.e. that video signals and audio signals are uniformly combined, errors are corrected, and thus the video signals and the audio signals are unsynchronized which results in unnatural video, to be overcome.

Abstract: A method, telecommunication apparatus, and electronic device detect a status of a radio link. A transceiver 302 may receive a reference signal transmitted from a base station 104. A processor 304 may assume a transmission of a codeword of a first payload type from the base station and may determine a synchronization status based on the received reference signal and based on the assumed transmission of the codeword of the first payload type from the base station.

Abstract: A method of transmitting over a network a signal comprising a plurality of data elements the method comprising; receiving the signal at a terminal; determining a transmission delay of at least one data element; estimating a first component of the transmission delay; determining a second component of the transmission delay by removing the first component of the transmission delay from the transmission delay; and determining a receiver delay to be applied between receiving at the terminal and outputting from the terminal one of said plurality of data elements, in dependence on the second component of the transmission delay.

Abstract: A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

Abstract: A passive phase jitter modulation (PJM) tag is charged with power in a continuous wave (CW) section. When receiving a command from a reader, the passive PJM tag must recognize the command and determine exactly when to begin demodulating the command. Only then can the passive PJM tag demodulate the command. To this end, a synchronization apparatus for accurately demodulating a signal input to a PJM tag includes a plurality of correlators correlating a received phase jitter-modulated signal with a template of an internal matched filter which is in the same form as at least a portion of a modified frequency modulation (MFM) flag.

Abstract: An intermittent operative communication apparatus can send data, received from a source communication device, to any receiver communication device at a predetermined interval and wait for receiving data at the predetermined interval. The communication apparatus has a selector for selecting one or multiple receiver communication devices as a reference communication device that gives a reference timing at which the communication apparatus waits for receiving data, and a timing controller for setting a timing, at which the communication apparatus waits for receiving data, to a timing according to operation of any reference communication device.

Abstract: A method, telecommunication apparatus, and electronic device for detecting a status of a radio link are disclosed. A transceiver 302 may maintain a radio link with a network base station 104. A processor 304 may map channel state information to a synchronization status associated with the radio link based on the received signal and determine the synchronization status via a block error rate estimate in the radio link based on the channel state information.

Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.

Abstract: A system for arbitrating a transmission of data includes a number K of transmitters, a request signal transmission device, a device valid signal transmission device, and a data valid logic device, wherein a transmitter asserts a request signal to request permission to begin a data transmission and transmits transmission-identifying information to a receiver. The data valid logic device deasserts a data valid signal based on the state of a wait signal, thereby preventing a transmission of data from each of the K transmitters at one clock cycle after a clock cycle at which the data signal is deasserted. An arbitration logic device of the receiver selects one of the number K of transmitters to grant permission to transmit data to the receiver and outputs an arbitration signal to a wait logic device instructing the wait logic device to deassert the wait signal of the selected trnasmitter.

Abstract: Certain aspects of a method and system for satellite communication are disclosed. Aspects of one method may include a receiver that handles digital video broadcasting. The receiver may be enabled to dynamically vary spacing between one or more pilots within at least one frame based on a determined symbol rate. The size of each of a plurality of received programs may be determined and the spacing between one or more pilots may be dynamically varied based on the determined size of each of the plurality of received programs.

Abstract: Techniques are described to provide a device and network of devices that collect distributed coordinated timestamps from distributed time counters in a multi-module or multi-integrated circuit system. The interconnect between the modules can be a single-wire or a two-wire interconnect. The modules communicatively coupled to the interconnect can use a collision-avoidance protocol for triggering the broadcasting of timestamps among the modules as well for allowing all modules to transmit their timestamps. Timestamps from multiple clocks can be transmitted by all modules and then collected and compared to produce correction factors to clock signals of each module to potentially achieve distributed clock synchronization in multiple independent modules or integrated circuits.

Abstract: A self-stabilizing network in the form of an arbitrary, non-partitioned digraph includes K nodes having a synchronizer executing a protocol. K?1 monitors of each node may receive a Sync message transmitted from a directly connected node. When the Sync message is received, the logical clock value for the receiving node is set to between 0 and a communication latency value (?) if the clock value is less than a minimum event-response delay (D). A new Sync message is also transmitted to any directly connected nodes if the clock value is greater than or equal to both D and a graph threshold (TS). When the Sync message is not received the synchronizer increments the clock value if the clock value is less than a resynchronization period (P), and resets the clock value and transmits a new Sync message to all directly connected nodes when the clock value equals or exceeds P.

Abstract: A disclosed data processing apparatus includes: a binarization unit binarizing input data based on a threshold voltage; a capture unit capturing data from a binary output binarized by the binarization unit; a duty cycle detection unit detecting a duty cycle of the binary output; and a control unit controlling a level of the input data based on the duty cycle detected by the duty cycle detection unit.

Abstract: A digital broadcast demodulator receives a tuner signal output from a tuner and carries out demodulation processing on the tuner signal by using an internal clock signal that is synchronized with a reference signal. The digital broadcast demodulator has an internal clock-signal generator and an internal clock frequency controller. The internal clock-signal generator generates the internal clock signal, and the internal clock frequency controller controls a frequency of the internal clock signal in accordance with a reception channel.

Abstract: An OFDM demodulator which does not require a reference signal for synchronization of carriers and can reduce influence of phase rotation by a propagation path when carrier synchronization is made. The OFDM demodulator performs Fourier transform plural times in 2 or more different operation ranges for the same OFDM symbol, calculates phases of sub carriers from the plural-time results of the Fourier transform, compares the calculated phases for each of the plural-time results of the Fourier transform and detects an error in frequency of reproduction carrier from the compared results.

Abstract: A device and a method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle.

Abstract: A transmitting method has steps of modulating carrier waves having frequencies set at ½N?n (n?N; n is a positive integer) of a reference frequency with transmission signals to produce modulated signals, multiplexing the modulated signals by frequency division multiplexing to produce an input signal, and transmitting the input signal to a synchronous detector in which the transmission signals are extracted from the input signal by calculating a moving average of the input signal every sampling period of time corresponding to the reference frequency and performing an addition and subtraction calculation corresponding to the cycle of each carrier wave for the moving averages. The frequency of each carrier wave, modulated with one transmission signal having a first signal level, is equal to or lower than the frequency of any carrier wave modulated with another transmission signal having a second signal level higher than the first signal level.

Abstract: A system and method for determining an approximate location of a mobile device. The occurrence of a predetermined event may be determined at a first node of a network. Measurement data associated with the mobile device may be stored at a second node of the network. An attempt may be made to determine a location of the mobile device using a first location methodology. Upon failure of the location attempt, the mobile device data may be received at a third node of the network from the second node. At the third node an approximate location of the mobile device may be determined using the mobile device data.

Abstract: An OFDM receiver apparatus receives an OFDM signal including a plurality of DBPSK signals transmitting identical information. An extraction unit extracts the plurality of DBPSK signals from the OFDM signal. A phase difference calculation unit calculates a phase difference between symbols of each of the plurality of extracted DBPSK signals. An accumulation unit accumulates the plurality of phase differences. A decision unit decides data transmitted by the DBPSK signals on the basis of an accumulation result.

Abstract: A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.

Abstract: The invention is directed to a method and system for providing centralized automated synchronization clock reconfiguration in packet switched telecommunications networks having network nodes that do not implement Synchronization Status Messaging (SSM) internally. This is especially useful when integrating TDM networks with packet switching network elements having T1 and E1 interfaces.

Abstract: Briefly, some embodiments of the invention may provide devices, systems and methods of in-phase and quadrature mismatch analysis and correction. For example, a method in accordance with an embodiment of the invention may include re-encoding an estimated symbol of an input signal having an in-phase component and a quadrature component, based on an analysis of a mismatch between said in-phase component and said quadrature component.