Abstract: Systems and methods for adaptive clock and equalization control are provided for data receivers, which are based on a “closed loop” sampling clock framework that employs controllable and dynamically adapted time offsets on both local data and amplitude clocks. The controllable clock offsets are dynamically adapted using signal processing methods adapted to achieve optimum sampling of data and amplitude sampling clock signals to accurately detect data bits and optimize system equalization settings, including, decision-feedback equalizer and/or an optional linear equalizer preceding a decision-feedback equalizer.

Abstract: A method and system of sample recovery is disclosed. In one embodiment, a method includes selecting initially in an arbitrary manner, a current symbol from a sequence of input samples, comparing a symbol timing estimate associated with the current symbol to a predetermined threshold, selecting a future symbol strobe that is ahead at an interval equivalent to a predetermined interval based on the comparison of the symbol timing estimate to the predetermined threshold, selecting a future symbol from the sequence of samples corresponding to the future symbol strobe, assigning the future symbol to the current symbol, which is the recovered symbol, rearranging the recovered symbols to form Pulse Code Modulated (PCM) samples of a bandlimited signal at a sample rate which is derived from the recovered symbol rate, and resampling at the sample rate of the receptor block which receives the recovered PCM samples.

Abstract: A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.

Abstract: A transmission system includes: a transmission-side device that has a transmission-side clock generation unit that generates a first clock signal on the basis of a reference clock signal; a clock extraction unit that removes a data clock signal superimposed with transmission data to a reception-side device; a clock difference acquisition unit that determines a difference between the first clock signal and the data clock signal; and a packet generation unit that packetizes the information on the difference determined by the clock difference acquisition unit; and the reception-side device that has a reception-side clock generation unit that generates a second clock signal on the basis of the reference clock; a packet reception unit that receives the information on the packetized difference from the transmission-side device; and a data clock regeneration unit that regenerates the data clock signal on the basis of the second clock signal and the difference information.

Abstract: Certain aspects of a multi-channel signal synchronizer may comprise receiving a plurality of clock signals from a plurality of clock signal sources, wherein a portion of the received plurality of clock signals may be out of synchronization with a remaining portion of the received plurality of clock signals. A plurality of data signals may be received from a plurality of data signal sources, wherein a portion of the received plurality of data signals may be out of synchronization with a remaining portion of the received plurality of data signals. The received portion of plurality of clock signals and data signals may be synchronized to the received remaining portion of plurality of clock signals and data signals utilizing bit alignment and sample alignment. A plurality of synchronized output signals may be generated based on the synchronized received plurality of clock signals and synchronized received plurality of data signals.

Abstract: A serial communication system includes a receiver that incorporates an amplitude monitor, which may be used to set and maintain appropriate termination-resistance values and transmit pre-emphasis and receive equalization settings. The amplitude monitor can note the presence or absence of input signals, as is required by some communication standards, such as those that require support for “out-of-band” (OOB) signaling for e.g. rate negotiation. The amplitude monitor compares the input signal with a reference level in response to a sample clock. The sample clock is periodically phase shifted with respect to the incoming data so the amplitude monitor is sure to sample an incoming data eye at or near the peak amplitude over a selected sample period. The amplitude detector notes the detection of an input signal if the input signal surpasses the reference level for any sample phase.

Abstract: In an embodiment, a digital pre-distortion apparatus processes an input signal to produce a pre-distorted signal, and processes the pre-distorted signal to produce a feedback signal. The apparatus also rotates an adjustment gain by a gain rotation angle to produce a rotated adjustment gain, where the gain rotation angle is based on a phase difference between the input signal and the feedback signal. The apparatus also applies the rotated adjustment gain to the feedback signal, which may result in rotation of the feedback signal into a target phase region.

Abstract: A system and method are provided for auto-squelching digital communications. The method receives digital information from a source node. If the receive channel is corrupted, an alarm condition is detected that is associated with the received digital information. The method transmits an alarm-condition signal to a destination node, and in response to transmitting the alarm-condition signal, maintains a valid link to the destination node. For example, detecting the alarm condition may include: comparing a frequency associated with the recovered clock signal, with a reference frequency; and, detecting a variance between the recovered clock signal frequency and the reference frequency. Alternately, loss of signal, loss of lock, out of band, and run length alarm conditions may be detected. The alarm-condition signal that is transmitted may be a serial data stream of information such as all “0”s data, all “1”s data, or alternating “0”s and “1”s data for example.

Abstract: A method and system for removing the effect of intersymbol interference (ISI) from a data record indicating times of logic level transitions exhibited by a data signal that has been distorted by ISI exhibited by a system having a particular step response may perform the following acts. The data record may be received, and a transition from within the data may be selected record for removal of ISI. Preceding transitions within the data record are then inspected. A time defect is obtained, based at least in part upon the inspected preceding transitions. Finally, the data record is adjusted, based upon the time defect, to indicate a new time of transition for the selected transition, thereby removing the effect of ISI for the selected transition.

Abstract: A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates an activated sync detect signal. The lost bit storage unit detects a data bit of the data packet corresponding to an activation point of the sync detect signal. The deserializer recovers the data packet by combining the detected data bit with the data packet.

Abstract: The invention relates to a method of transmitting time information relating to the clock of the source of a sending part consisting in using a fixed latency indicator signal to authorize the source to insert time information used to slave the clock of the decoder of the associated receiving part to its clock.

Abstract: A method and an apparatus for synchronizing a data stream are disclosed. The method comprises: decoding the data stream to generate a decoded data stream and program clock references; generating a local clock reference; generating a simulated clock reference according to the program clock references and the local clock reference; comparing the local clock reference with the simulated clock reference; adjusting a processing timing of the decoded data stream according to the comparison result; and processing the decoded data stream according to the processing timing.

Abstract: A method and apparatus is provided for synchronizing a clock signal by generating time varying PLL phase coefficients which approximate optimal PLL phase coefficients. An acquisition mode phase coefficient is determined by adding an error signal (A) to the sample counter (k) and finding the reciprocal of the result (1/(A+k)). The reciprocal can be calculated in hardware or determined by using a lookup table. A tracking mode phase coefficient is determined based on the error signal for use in the PLL during a track a tracking period. The tracking period begins when the tracking mode coefficient is greater than the acquisition mode coefficient.

Abstract: An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the plurality of samples to be a second selected sample of the input signal. A phase control circuit is coupled to receive the first and second selected samples of the input signal and includes circuitry to compare the selected samples to determine whether the first clock signal leads or lags a transition of the input signal. The transmit circuit includes a serializing circuit to receive a parallel set of bits and to output the set of bits in sequence to an output driver in response to a first clock signal.

Abstract: In a single-wire data communication characterized in that a data communication unit time is different in accordance with the polarity of a signal, a communication control time is dependent on a communication data pattern, and hence, the control of the whole system is difficult. A counter for counting a clock continues the counting until a count value thereby obtained reaches a predetermined upper limit value, retains the predetermined upper limit value as the count value until a next pulse is detected in a reception signal after the count value reaches the predetermined upper limit value, and initializes the count value when the next pulse is detected. A data value judger judges a data value depending on whether or not the pulse is detected during a period before the time when the count value reaches the predetermined upper limit value.

Abstract: The time synchronization system according to the present invention can allow the master and slave time Tx/Rx devices to communicate information therebetween via two-way interactive wireless communication, so that it can rapidly detect an error that occurs in the system, via a monitoring device and a network management device for performing real-time integral management. Therefore, the system can reduce the user's system maintenance fee and can also maximize efficiency. In addition, the time synchronization system can allow for the easy extension of the equipment construction coverage area even in a long distance environment, by installing only repeaters, and can manage log information that may be used as evidence data for various incidents.

Abstract: A host base transceiver station BTS derives a reference timing signal from a physical layer training signal (such as a preamble) received from a neighbor network node/BTS. Downlink transmissions are then synchronized to the derived reference timing signal. This may be used as a holdover timing mode, such as when the host BTS determines that synchronization from a primary source is no longer reliable. In an embodiment, a reference oscillator of the host BTS is phase locked to the derived reference timing signal. Variations include one or multiple such training signals from one or multiple neighbor BTSs, selecting one BTS when the primary synchronization mechanism fails for several BTSs in the same area, and how to phase lock the oscillator without dithering about the target frequency. Apparatus and computer programs are also detailed.

Abstract: Aspects of a method and system for reordered QRV-LST (layered space time) detection for efficient processing for multiple input multiple output (MIMO) communication systems are presented. The method may include receiving an ordered plurality of signals wherein each of the ordered plurality of received signals comprises information contained in an ordered plurality of spatial streams. Each spatial stream may comprise one or more frequency carriers, or tones. Information, or data, contained in a corresponding one of the ordered plurality of spatial streams may be detected. The order in which the information is detected may be determined for each individual frequency carrier.

Abstract: A transmitting and receiving section transmits data to which a time measured in a first device is attached, from the first device through a communication line, and receives the data in a second device. A communication abnormality detecting section detects an abnormality in a communication between the first device and the second device on the basis of the received data. A time lag detecting section detects a time lag between the first device and the second device by comparing the time attached to the data with a time measured in the second device at the time of receiving the data.

Abstract: User Equipment in a wireless communication network considers the downlink channel bandwidth in setting out of synchronization (OoS) and in synchronization (IS) thresholds and filter durations. Additionally, the UE may consider transmitter antenna configuration—that is, the number of transmitting antennas in a MIMO system—in setting the OoS and IS thresholds. The UE determines it is OoS when a monitored, filtered, downlink channel quality metric, such as reference symbol SINR, is below the OoS threshold.

Abstract: A timing lock detection apparatus and method for digital broadcasting receiver are provided. The apparatus includes: a discrete value generator for cyclically selecting a discrete signal value from a continuous timing error signal; a differential calculator for obtaining a difference between the currently selected timing error signal value and a previously selected timing error signal that is a timing jitter signal; a sign variation detector for detecting variation in a sign of the timing jitter signal; a lock control signal generator for discriminating a period based on the detected sign changing time, and controlling a lock step of the loop filter according to a convergence mode of the timing jitter signal at each period; and a lock detection signal generator for generating a lock signal or an unlock signal according to whether the timing jitter signal reaches a steady state and using the current lock step signal.

Abstract: A clock synchronization circuit includes a clock generation circuit generating a sampling clock for sampling a received signal from an output of a local oscillator, a phase error detection circuit finding a phase error between sampling timing of the sampling clock and ideal sampling timing, and a timing correction circuit finding a correction quantity to correct a frequency error between a frequency of the sampling clock and a frequency of the ideal sampling timing and the phase error every sampling timing of the sampling clock, and outputting a sampling value interpolated according to the found correction quantity.

Abstract: A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the CDR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.

Abstract: A system includes first and second wireless nodes having a clock with plural times, a wireless transceiver, and a processor cooperating with the transceiver to transmit and receive packets. The second node transceivers wirelessly communicate with the first or other second node transceivers. The second nodes include a Kalman filter with an output, plural filter gains, and an input representing the difference between: about the time of the clock when a received packet should have ideally been received, and a time when the received packet was actually received as measured by the clock. A circuit provides dynamic adjustment of the filter gains. The Kalman filter output estimates the difference between the time of the receiving node clock and a corresponding one of the times of the transmitting node clock. The second processor cooperates with the Kalman filter output to adjust the times of the receiving node clock.

Abstract: A method, a related system, and recordable media adapted to store the method. The method controlling transmission frequency for first and second transmission signals exchanged between a host and an attached device using a serial advanced technology attachment (SATA) technology by detecting a first transmission frequency from a received first transmission signal, and controlling a second transmission frequency for a second transmission signal in relation to the detected first transmission frequency.

Abstract: A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.

Abstract: An object of the present invention is to provide a DLL circuit adjustment system that can adjust the sampling timing of a DLL circuit without causing any increase of the number of interface signals or amount of coding overhead and any reduction of the data transfer efficiency. On a transmitter side, an ECC generating section adds an error detection/correction code to transmission data and outputs the transmission data with the error detection/correction code. Of output channels of the transmission data from the ECC generating section, a data bit associated with the DLL circuit to be adjusted is replaced with a sampling timing adjustment pattern using a to-be-adjusted channel selection circuit and a selector, and the resulting transmission data is transmitted to a receiver side.

Abstract: A coder is fed with pre-coded data such that the absolute value of the RDS of the code words as produced by the coder is limited. This is achieved by ensuring that in a group of 2 code words the RDS of the first code word is compensated by the RDS of the second conde word. The RDS at the end of the second code word is then zero and the excursions of the RDS from the start of the first code word until the end of the second code word are limited because there are only a limited number of bits that can contribute to an increase of the absolute value of the RDS. This principle can easily be applied to the 17PP coder.

Abstract: A semiconductor substrate integrated electronic circuit includes a transmitter block and a receiver block connected through a communication network (4). A data signal having a transmission period is generated on a first line that is received by the receiver block. A congestion signal is generated on a second line from the receiver block to the transmitter block when a congestion event of the receiver block occurs in order to interrupt the data signal transmission. A synchro signal is generated on a third line starting from the transmitter block, this synchro signal indicating to the receiver block that the data signal comprises a new datum. The congestion signal also interrupts the synchro signal transmission when a congestion event of the receiver block occurs.

Abstract: A MODEM device includes a detector configured to detect a synchronization signal transmitted from a source MODEM in a resynchronization process of a primary channel and a timer configured to count up starting from a beginning of a detection of the synchronization signal, and send information to forcibly move into a receiving mode for receiving image data when a time period from the beginning to a completion of the detection of the synchronization signal exceeds a predetermined time period.

Abstract: There is provided a jitter injection apparatus that generates an output signal having an injected jitter. The jitter injection apparatus includes a first oscillator that generates a first periodic signal, a second oscillator that generates a second periodic signal having a period different from that of the first periodic signal, and a switching section that switches which of the first periodic signal and the second periodic signal is output at every predetermined timing and outputs the switched periodic signal as the output signal.

Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.

Abstract: A method and system for a frequency shift key demodulation is provided. The system includes a counting block for counting a reference clock within a window defined by a modulated signal, a detector for comparing a count value output from the counting block with digital multi-level thresholds and outputting baseband data based on the comparison, and a configurations block for configuring at least one of the counting block and the detector. The method includes counting a reference clock within a window defined by the FSK modulated signal and outputting a count value as a result of the counting, and comparing the count value with multi-level thresholds to output baseband data based on the comparison.

Abstract: Systems and methods for synchronizing a source and sink device are disclosed. A sink device can efficiently determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method for transmitting a source data stream from a source device to a sink device includes, forming a logical channel from a source device to a sink device, where the logical channel is configured to carry the source data stream, and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel.

Abstract: A transceiver apparatus and a method comprise detecting means for detecting messages, wherein the detecting means comprises a first detector arranged to operate over a first detection period and which output indicates the beginning of a message with a first detection probability, and a second detector arranged to operate over a second detection period and which output indicates the detection of the beginning of a message with a second detection probability. The second detection probability is higher than the first detection probability and the transceiver apparatus is arranged to receive the message if the second detector indicates detection of the beginning of a message.

Abstract: One or more aspects of the present invention pertain to transferring digital data between first and second domains, where a first clock of the first domain operates at a first frequency and a second clock of the second domain operates at a second frequency, where the first frequency is higher than the second frequency, and where the first and second clocks have arbitrary phase relationships relative to one another. Techniques employed facilitate efficient digital data transfer between the first and second domains while conserving valuable semiconductor real estate.

Abstract: Method and apparatus for synchronizing base stations employing an independent synchronizing source or identifying a base station as a master source. An RNC (C-RNC) or a base station may designate one base station or a UE to acquire measurements derived from base stations to achieve synchronization. Synchronization activities may be regularly scheduled or may be undertaken when periodic measurements indicate that a drift value exceeds a given threshold.

Abstract: A composite signal includes a high power beacon signal and low power corresponding wideband synchronization signal and is communicated over a time interval exceeding a single OFDM transmission time interval. A base station transmits one or more different such composite broadcast signals in a recurring timing structure. Each different potential beacon signal, e.g., a single tone signal, is paired with a unique wideband synchronization signal. A wideband synchronization signal includes at least some predetermined null tones and at least some predetermined non-null tones. For a given wideband synchronization signal, the predetermined null tones carry predetermined modulation symbol values, A wireless terminal receives a composite signal, identifies a beacon, determines a corresponding known wideband synchronization signal, compares received to known wideband synchronization signals, and determines at least one of a timing adjustment, frequency adjustment and channel estimation.

Abstract: A semiconductor integrated circuit includes a sampling unit, a delay unit, a first operating unit and a second operating unit. The sampling unit samples an input signal supplied from an external circuit in synchronization with a clock signal, and outputs the sampled input signal as a first signal. The delay unit delays the first signal in synchronization with the clock signal, and outputs the delayed first signal as a second signal. The first operating unit operates whether a signal level of the input signal is sustained equal to or longer than a predetermined period based on the first and second signals, and outputs an output signal in synchronization with the clock signal when the signal level of the input signal is sustained equal to or longer than the predetermined period. A signal level of the output signal is sustained equal to or longer than the predetermined period. The second operating unit asynchronously controls the sampling unit based on the input signal and the output signal.

Abstract: A method and an apparatus for synchronizing a data stream are disclosed. The method includes: decoding the data stream to generate a decoded data stream and program clock references; generating a local clock reference; generating a simulated clock reference according to the program clock references and the local clock reference; comparing the local clock reference with the simulated clock reference to generate a comparison result; adjusting a processing timing of the decoded data stream according to the comparison result; and processing the decoded data stream according to the processing timing.

Abstract: A frame synchronous circuit operable in a dedicated short-range communication system, applicable to several modulation schemes, includes a UW detector for detecting a UW word from received data, an operation setting register group for specifying the operations of an on-board unit, a synchronous manager for controlling synchronization, an unlimited synchronization continuation register for maintaining the unlimited continuation of the synchronization, and an FCMC data analyzer for analyzing FCMC data. The operation setting register group can control synchronization by using not only operational information obtained from the FCMC data but also another operational information retrieved from an input device such as a CPU or terminal connected to the on-board unit. Consequently, debug and test operations can be performed without receiving any FCMC data.

Abstract: An Orthogonal Frequency Division Multiplexing (OFDM) synchronization module includes a window generator module, a symbol timing estimator module, and a reliability metric calculator. The window generator module generates a sampling window that bounds a plurality of samples of OFDM symbols. The symbol timing estimator module generates an estimated symbol timing from the plurality of samples before a fast Fourier transform operation is performed on the plurality of samples. The reliability metric calculator calculates a reliability metric for the estimated symbol timing based on the estimated symbol timing. The window generator module changes at least one parameter of the sampling window based on the reliability metric.

Abstract: The invention relates to a method and system for use in assessing the quality and integrity of a data transmission path or link between a data transmitting location and at least one receiving location at which a broadcast data receiver is located with means to allow an error rate calculation to be made with respect to a known data signal sequence which is inserted into the transmitted signal. On the basis of the calculations made and sent to the transmitting location a particular data modulation scheme is adopted to provide the most efficient data transmission method for each receiving location. The invention is of particular use in cable data transmission networks of the type which for example allow television channels and other services to be provided to a plurality of receiving locations.

Abstract: Methods and apparatuses for dynamically adjusting sync windows are described. A default sync window is set; a data signal is input; detecting if parts of the data signal within the sync window form a sync pattern; accumulating a count of the sync pattern within and without the sync window; and reducing the sync window when the count of sync pattern within the sync window achieves a first threshold value, and increasing the sync window when the count of the sync pattern outside the sync window achieves a second threshold value.

Abstract: The present invention describes a method and a system for executing preamble detection, symbol timing recovery, and frequency offset estimation that are applied to a PHS system for executing the preamble symbol detection and timing recovery. The system includes a first absolute value circuit, an average circuit, a multiplier, a sample and accumulate circuit coupled to the multiplier, a second absolute value circuit, a first compare circuit, and a second compare circuit, such that the system with the foregoing structure can detect a preamble symbol by less symbols while performing a timing recovery. The invention also describes a frequency offset computation method and its circuit.

Abstract: A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

Abstract: A system and method of performing re-synchronization for a Digital Video Broadcasting over Handheld (DVB-H) receiver comprises performing a time division multiplexing (TDM) data burst transmission sequence on bits of data received by the DVB-H receiver; performing a data bit re-synchronization sequence on the DVB-H receiver; and reducing a re-acquisition time at every stage of the data bit re-synchronization sequence, wherein the reducing process results in a reduction in the time to perform the re-synchronization for the DVB-H receiver, wherein the reduction in the time to perform the re-synchronization for the DVB-H receiver is greater than one-half of the time required to perform the re-synchronization for the DVB-H receiver absent the reducing of the re-acquisition time at every stage of the data bit re-synchronization sequence.

Abstract: A system and method of performing re-synchronization for a Digital Video Broadcasting over Handheld (DVB-H) receiver, wherein the method comprises performing a time division multiplexing (TDM) data burst transmission sequence on bits of data received by the DVB-H receiver; performing a data bit re-synchronization sequence on the DVB-H receiver; removing an on-chip timer and internal state registers in the DVB-H receiver; and allowing the DVB-H receiver to power off in between receipt of data bursts. Preferably, the removing process reduces the time to perform the re-synchronization in the DVB-H receiver. Preferably, the data bit re-synchronization sequence comprises performing an automatic gain control (AGC) lock process; performing a mode and guard detecting process; performing a frequency offset estimation process; performing a transmit parameter signaling (TPS) detection process; performing a timing and carrier loop lock process; and performing an equalizer delay process.

Abstract: A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.

Abstract: A clock generating device includes: a frequency divider having an input node coupled to a transmission interface for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit having a data input node coupled to the transmission interface and a reference clock input node coupled to an output node of the frequency divider, for generating an output clock signal according to one of the input data received at the data input node and the reference clock signal received at the reference clock input node.