Abstract: A method and system for detecting frame slips due to loss of synchronization in a digital communication channel is described. In an illustrative embodiment, a synchronization bit pattern is periodically embedded in the digital data stream. In a described embodiment, the sign bits of the octets of every N frame of data is robbed to form a periodic control channel carrying the synchronization bit pattern. The control channel can be monitored at the appropriate intervals to detect the appropriate synchronization bit pattern. Failure to detect the synchronization bit pattern at the appropriate interval indicates a loss of synchronization such as a frame slip.

Abstract: A phase lock loop receives a baseband signal which has an input frequency, and modulating the baseband signal to be a corresponding RF signal which has a predetermined transmission frequency for transmitting. The phase lock loop comprises a programmable divider, a modulator, a phase detector, a charging pump, a loop filter, a voltage-controlled oscillator and a frequency converter. The programmable divider divides the frequency of a local oscillating signal by a programmable divisor to generate a reference signal. The modulator receives the baseband signal, modulates the frequency of the reference signal according to the baseband signal, and generates a corresponding first comparison signal. The frequency converter receives the feedback RF signal and the local oscillating signal and outputs the second comparison signal according to the frequency difference. The divisor of the divider is programmable to avoid the spur frequency being generated because the local oscillating signal is interfered.

Abstract: Disclosed is a clock signal control device which has: an oscillator which generates a clock signal; a pulse detecting circuit which detects the frequency or duty of the clock signal and outputs a control signal based on the result of detection; and a clock signal supply selecting circuit which generates a supply clock signal from the clock signal generated from the oscillator in response to the control signal from the pulse detecting circuit.

Abstract: A system and method for switching between input clock signals from different clock sources without losing lock by providing a supplemental correction signal to the loop filter in a phase locked loop (PLL) circuit. The phase detector includes a supplemental correction pulse generator configured to offset, at least partially, the effects of losing an input clock signal from a first clock source failure. The phase detector is coupled to receive the input clock signal and a feedback signal. The phase detector outputs a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The loop filter is coupled to receive the phase error signal and to output an error correction signal. A voltage controlled oscillator is coupled to receive the error correction signal and to generate the output signal of the PLL, with the feedback signal indicative of the output signal. Switching logic is coupled to monitor the input clock signal from the first clock source for a failure.

Abstract: The present invention relates to a method for maintaining a time reference which is governed by a high clock frequency produced by a first clock frequency generator, in which a changeover is essentially made, for a changeover time period, to a low clock frequency produced by a second clock frequency generator. The apparatus of the invention maintains the time reference governed by the high clock frequency, wherein a changeover is made to the low clock frequency for a specific changeover time period. The invention is advantageously used to save power in electronic apparatus such as in mobile stations of mobile radio systems.

Abstract: An indoor GPS clock using GPS signals lower that −143 dBm for issuing disciplined frequency and time standard signals. The indoor GPS clock includes a correlation machine using long integration periods for enabling the indoor GPS clock to operate with low signal levels; a carrier-less tracking loop for tracking the low level signals without carrier offset feedback, a clock bias loop for providing clock bias feedback; and a reference oscillator using the clock bias feedback for providing disciplined frequency and time signals having greater accuracy than is available in conventional GPS positioning receivers. The indoor GPS clock also includes a holdover driver providing compensation for predicted drift in clock bias error for disciplining the reference oscillator for several hours when the GPS signal is no longer being received.

Abstract: A circuit for receiving data includes a first receiver having an input for receiving data and an input for receiving a first clock signal. The data is clocked into the first receiver by the first clock signal. The circuit also has a second receiver having an input for receiving data and an input for receiving a second clock signal. The first and second clock signals have the same frequency and are phase shifted with respect to one another. The data is clocked into the second receiver by the second clock signal. Determination is provided to determine if at least one of the receivers has correctly received the data. A first output of one of the receivers is enabled in accordance with the determination.

Abstract: A system and method for enabling an optical network unit (ONU) in a passive optical network to scramble data and send the scrambled data upstream to an optical line termination unit (OLT). In passive optical networks the clocks in the OLT and ONU are synchronized by recovering the clock from the data signal. However, the clocks may drift when no data transitions occur on a long string of data. In addition, the OLT may require data transitions to ensure proper adjusting of its receive threshold. In either circumstance, collectively called Loss of Synchronization, the data may not be received correctly by the receiver and the transmitter will need to resend the data. In the present invention, the transmitter will vary the seed used in the scrambling operation. The use of a different seed per each transmission significantly reduces the chances that a loss of synchronization will occur.

Abstract: A telecommunications device includes a synchronization bus. A first controller coupled to the bus generates first pulses and communicates the first pulses using the bus. A second controller coupled to the bus generates second pulses synchronized with the first pulses and communicates the second pulses using the bus. A card also coupled to the bus receives the first and second pulses and generates internal pulses synchronized with the first and second pulses. The card compares at least one internal pulse with at least one first pulse to detect a loss of synchronization between the internal pulse and the first pulse. The card indicates this loss of synchronization and the second controller may determine a failure of the first controller in response to at least the indication from the card.

Abstract: A communication system including a plurality of communication apparatuses connected via a data transmission line to execute data exchange between any of the communication apparatuses. The communication apparatuses include a transmitter/receiver configured to access said data transmission line at timing periods peculiar to respective communication apparatuses in synchronism with a common system clock among respective communication apparatuses. Further, the timing periods peculiar to respective communication apparatuses are set to be mutually shifted such that accesses to said data transmission line are not simultaneously generated from said plurality of communication apparatuses, and at least two communication apparatuses have communication speeds different from each other.

Abstract: A method and device for counting the number of consecutive data symbols in a stream of data bytes, the device comprising a main counter for maintaining a count which is incremented/decremented for each respective consecutive data byte of said stream and adjustment means for incrementing/decrementing the count of the main counter, after every occurrence of a predetermined number of consecutive data bytes, by an adjustment value determined according to the ratio of the number of bits in the bytes to the number of bits in the symbols, such that the count represents a count of data symbols and a method and device for generating a synchronization signal from a received MPEG data stream with a MAC message containing an Upstream Slot Marker Pointer, the device including the above counting device, a controller for starting main counter according to a received MPEG synchronization signal and synchronization means for generating the synchronization signal once the main counter has counted the number of symbols indicate

Abstract: An apparatus which depends on one of a plurality of master clocks as a timing source includes a timing-dependency-direction-identifier-extraction unit which detects an identifier indicative of a direction of timing dependency from a received signal with respect to each of the master clocks, a timing-quality-information-extraction unit which detects a code indicative of a timing quality from the received signal with respect to each of the master clocks, and a synchronization unit which selects the timing source based on the code indicative of a timing quality, and identifies a direction of timing dependency of the timing source based on the identifier indicative of a direction of timing dependency.

Abstract: In a clock management apparatus for a synchronous network system, when the quality of a clock signal is deteriorated, the clock signal is switched to another clock signal automatically to continue synchronous communication. Clock signals are received and extracted by transmission/receiving units of the synchronous network system. A plurality of clock signals including the extracted clock signals and a clock signal from an external clock are selectively switched by a clock switching unit, and a master clock signal is selected and output based on quality information transferred with each clock signal. The master clock signal is applied to a clock generator generate a clock signal. A quality control table is used to convert quality information into associated quality levels. A quality determination processing unit issues an alarm when the quality level of the master clock signal is deteriorated beyond a threshold provided by a synchronization management table.

Abstract: A clock selection controller is shown which allows a user to assign a priority scheme to recovered clock signals obtained from communication facilities. The clock selection controller also receives a plurality of alarm signals corresponding to the communications facilities for each of the recovered clock signals. The clock selection controller then automatically selects, for output as a reference clock signal, the highest priority clock input available for which the corresponding alarm signals are inactive. In the absence of an available clock input in the priority scheme, the processor selects a free running clock input.

Abstract: A scalable clock recovery system. In one embodiment the system comprises a clock master unit, a clock distribution network, and a plurality of clock recovery units. The master clock unit generates a plurality of master clock signals, which are received by the clock recovery units. The clock recovery units use multiple stages of mixing to generate a recovered clock. The recovered clock can be used to recover data from a serial data stream.

Abstract: A frame synchronism processing apparatus including a first detecting unit for detecting the synchronism of a subframe, a second detecting unit for detecting the synchronism of a multiframe, and a synchronism detection retrying control unit for forcibly bringing the first detecting unit and the second detecting unit into a synchronism detection retrying mode if the second detecting unit has failed to detect the synchronism of the multiframe. Assuring that a false synchronous state is brought about on the subframe synchronism with the result that the detection of the synchronism of the multiframe has been failed, the detection of synchronism of the subframes and the detection of synchronism of the multiframe are retried, thus avoiding a deadlock of frame synchronism process due to the possible false synchronous state and hence improving the reliability in synchronism process.

Abstract: A prescribed signal transmission channel parameter is estimated by employing a unique arrangement and/or method that does not require the estimation of all the signal channel parameters. Specifically, this is realized by employing a rotational invariance arrangement or technique that utilizes either spectral, and/or temporal, and/or spatial diversity present in the wireless system to generate a single prescribed parameter of the mobile signal transmission channel. The single prescribed signal transmission channel parameter is obtained by forcing the rotational invariance arrangement or technique to yield the single largest eigenvector from a prescribed relationship of signal data vectors of the signal transmission channel. In one embodiment of the invention the prescribed parameter of the signal transmission channel is the delay that is substantially constant over the diversity, while the gain of each signal transmission channel path may vary.

Abstract: A clock forwarding circuit automatically detects the delay in transmission of data between a master circuit such as a central processing unit and a slave circuit such as a semiconductor memory and forwards clocks corresponding to the delay. The master circuit includes a clock forwarding circuit which generates a clock signal. The slave circuit is coupled to the master circuit and generates a second clock signal which is synchronized with the first clock signal. The clock forwarding circuit receives the second clock signal, detects delay between the first and second clock signals and sets initial data load/unload parameters of the master circuit based on the detected delay. By forwarding clocks, the data transmission between the clocked circuits can be performed in faultless fashion independently of the delay.

Abstract: An interpolating bandpass filter for packet-data receiver synchronization comprises a single delay line that delays the passband-sampled data from the analog-to-digital converter, and a convolving structure that uses the delay line to implement a L-times oversampling bandpass filter. A separate accumulator accumulates a fractional phase difference that represents the frequency offset between the remote transmitter's frequency and the receiver's sampling frequency. The integer portion of the accumulator is used to determine the number of samples to delay the input of the filter, while the fractional portion is used to choose two coefficient sets closest to the desired delay and to interpolate between these two filter sets.

Abstract: Interface apparatus for interfacing data to a plurality of different clock domains where the clock signals in the different domains are phase locked together and respective clock signals have different frequencies includes a plurality of cascade connected first and second latches coupled between respective clock domains. One of the latches is a clocked Data Latch and the other is a clocked and Enabled Data Latch. A timing generator provides respective domain clock signals, wherein a domain clock signal of a domain providing a data signal is applied to the clock input connection of the first latch of a respective cascade connected set of latches and a domain clock signal of a domain receiving said data signal is applied to the second latch. The timing generator also provides a common Enable Signal phase locked to the domain clocked signals. The common Enable Signal is applied to the enable input terminal of one of the latches of each set of cascade connected latches.

Abstract: A communication system includes a timing circuit which generates phase conversion information from a transmitter to transfer data from a first clock domain to a second clock domain, and a receive phase calculation circuit which utilizes the phase information from the transmitter to transfer data from the second clock domain to the first clock domain. The timing circuit includes a transmit (TX) numerical controlled oscillator (NCO) and a modulo indicator, and the receive phase calculation circuit calculates a receive phase based on a modulo signal.

Abstract: A radio transmission system including many radio transmitters using frequency hopping carriers to intermittently transmit very short messages indicative of status of sensors associated with the transmitters. In operation, a time interval generator included in a transmitter generates pulses activating the transmitter at time intervals according to a predetermined algorithm. When activated, the transmitter transmits a message at one or several different frequencies. The frequencies are changed according to a predetermined algorithm and preferably differ for each subsequent transmission. Alternatively, when an abnormal sensor status is detected, the transmitter transmits repeated messages at a plurality of predetermined alarm frequencies for a predetermined time regardless of the time interval generator.

Abstract: An efficient method of accurately estimating delay spread in multi-path transmission applications is based on quantifying the effect of the actual delay spread on the shape of the correlation energy profile between the received signal and the synchronization pattern of the receiver. Depending on the degree of the estimated delay spread, an appropriate demodulation technique is selected for optimizing the receiver performance over a range of channel multi-path conditions. The invention is applicable to digital wireless mobile communication systems, as well as to any device that performs characterization or testing of a transmission system.

Abstract: A self-adjusting path is created by utilizing a phase detector and modifying a clock path and a data path to enable the passing of data in either phase of the clock. The new input path is controlled by the output of the phase detector. Each time a command is issued, the phase of the clock is detected and latched. The phase of the clock at the time the command issues is thus captured and can propagate through the pipeline along with the data. Accordingly, each stage along the data path can be synchronized to a different phase of the clock to reduce data corruption.

Abstract: A storage cell of an integrated circuit is operable in a radiation environment to capture and store at predetermined time intervals a time sample of a data input signal. A signal representative of the stored data sample for each time interval is generated at an output of the storage cell. At least three data capturing circuits operate to capture and store a time sample of the data input signal at each predetermined time interval, the stored data sample of each circuit being generated correspondingly at an output thereof. Coupled to the outputs of the data capturing circuits is a circuit for generating a signal representative of a stored data sample selected from at least two of the circuit outputs. Also coupled to the data capturing circuits is a circuit for causing each data capturing circuit to capture a different time sample of the input data signal from the other data capturing circuits over each predetermined time interval.

Abstract: Disclosed herein are circuits in which a plurality of clock signals are generated by corresponding clock generators from one or more common clock references. The clock generators accept control values that specify the phases of the individual clocks. The actual phase of each clock signal potentially varies during operation, and the phases of the various clock signal are generally independent of each other. To detect or measure phase relationships, the disclosed circuits evaluate or compare the control values using arithmetic logic.

Abstract: A GPS receiver having a fast time to lock to a GPS signal by storing a time period of an incoming GPS signal in a signal memory and rapidly comparing the signal memory against locations in a replica memory having stored GPS signal replicas. The GPS receiver includes a memory-based search engine for acquiring the GPS signal so that it may be tracked. The memory-based search engine includes a signal memory for storing a millisecond of a digitized GPS signal, a replica memory section for storing replicas representative of the digitized GPS signal for all possible frequency differences between the GPS carrier frequency and a local reference frequency and phase offsets between the GPS code phase and a local reference time, and a GPS memory comparator for comparing the stored signal in signal memory to the stored replicas in replica memory and issuing an acquisition detection signal when the level of the comparison is greater than a selected threshold.

Abstract: For restraining jitter amount of a transmission clock signal (16) generated by a digital PLL (8), a data transmission apparatus comprises a {fraction (1/24)} clock generator (6) for dividing frequency of a receiving clock signal (4), a clock multiplier (7) for generating a reference frequency signal (18) by multiplying frequency of the output of the {fraction (1/24)} clock generator (6), and a control unit (28) for controlling a frequency multiplying ratio of the clock multiplier (7) and controlling a frequency dividing ratio of a frequency divider provided in the digital PLL (8). According to jitter amount detected by a jitter detection signal generator (19), the frequency of the reference clock signal (18) is selected among {fraction (1/12)}, ⅛ and ⅙ of the frequency of the receiving clock signal.

Abstract: The invention relates to a digital radio system and to a method for correcting a synchronization error in a digital radio system comprising at least one base station (100) communicating with terminals (102, 104) in its coverage area, and a mobile telephone exchange (108) communicating with the base station and controlling the operation of the base stations. The information to be transmitted is coded and decoded in a transcoder unit (200) into a form suitable for the transmission. The base station sends information frames to the transcoder at a certain pace, and, correspondingly, the transcoder sends information frames to the base station at a certain pace. To ensure easy transmission of information and to increase flexibility, the base station (100) indicates in an information frame sent to the transcoder (200) the synchronization error present in the information frames coming from the transcoder, and the transcoder corrects its synchronization after receiving said message.

Abstract: The present invention presents an anti-meta trap (AMT) circuit for maintaining the data integrity of transmitted bit data in various applications. The anti-meta trap (AMT) circuit implement bit data integrity checks to prevent bit data from being misinterpreted at the bit level, that is, from being sampled at a data transition state. The invention also presents an anti-meta circuit combined with an auto-synchronization circuit to synchronize the phase of complete, bit-data verified cells, e.g., ATM data cells. The combined AMT-ASC is therefore able to verify the integrity of the data at the bit level, and synchronizing fixed-length data cells.

Abstract: An OFDM frequency/timing recovery circuit provides accurate recovery of both sub-carrier frequency and symbol timing information from a single OFDM symbol. Accuracy may be further enhanced in demanding applications by utilizing two OFDM symbols. A unique frequency/timing recovery symbol is used that is an OFDM symbol.

Abstract: A method and apparatus for adjusting timing in a digital system or telecommunication system includes processing that begins by dividing a data clock by a 1st value to produce a divided data clock. The processing continues by dividing an analog front-end clock by a 2nd value to produce a divided analog front-end clock. The 1st and 2nd values are selected such that the divided data clock and the divided analog front-end clock have similar clock rates. The processing continues by comparing the phase of the divided data clock with the phase of the divided analog front-end clock to produce a phase difference. The processing continues by adjusting the analog front-end clock based on the phase difference to produce an adjusted analog front-end clock.

Abstract: In a synchronization system adopted in a synchronous-multisystem control apparatus including a plurality of systems operating synchronously with each other at a fixed control period, the synchronous-multisystem control apparatus can be operated in a single-system mode in the event of failures occurring simultaneously in some of the systems. The synchronous-multisystem control apparatus employs a plurality of control circuits each provided for one of the systems.

Abstract: For synchronisation purposes, a transmitter (TX) multiplexes a pilot carrier with carriers whereon data elements (DATA) are modulated, and transmits the pilot carrier together with the modulated carriers to a receiver (RX). The immunity of the pilot carrier from interference, such as radio amateur signals, is improved by modulating the pilot carrier with a non-constant signal, for instance a random signal, an alternating signal or even scrambled data elements (DATA), before transmission thereof. Since demodulation of the pilot carrier in the receiver (RX) and averaging successive demodulated pilot carriers reduces the effect of the interference induced on the non-constantly modulated pilot carrier, the degradation of the synchronisation between transmitter (TX) and receiver (RX) is reduced significantly.

Abstract: A system and method for switching between input clock signals from different clock sources without losing lock by providing a supplemental correction signal to the loop filter in a phase locked loop (PLL) circuit. The phase detector includes a supplemental correction pulse generator configured to offset, at least partially, the effects of losing an input clock signal from a first clock source failure. The phase detector is coupled to receive the input clock signal and a feedback signal. The phase detector outputs a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The loop filter is coupled to receive the phase error signal and to output an error correction signal. A voltage controlled oscillator is coupled to receive the error correction signal and to generate the output signal of the PLL, with the feedback signal indicative of the output signal. Switching logic is coupled to monitor the input clock signal from the first clock source for a failure.

Abstract: An apparatus for receiving an asynchronous data signal may include a clock generator that generates a clock signal having a frequency approximately equal to the bit rate of the asynchronous data signal. An edge detector may detect transitions of the asynchronous data signal. A dead-band detector may detect when a transition of the clock signal used to sample the data signal occurs within a predetermined amount of time of a transition of the asynchronous data signal so that data sampled on that transition of the clock signal may be invalid. The phase of the clock signal may be adjusted if the transition of the clock signal occurs within this predetermined amount of time.

Abstract: The present invention provides a transceiver which does not lose synchronization upon a transition from a non-precoded communication mode to a precoded communication mode and minimizes phase drift. A transceiver unit outputs a signal representing the phase of a received signal, and that possesses a controllable sampling rate. The transceiver is coupled to a phase reference selector and a timing control system. Upon a transition between communication modes, an adaptation period is initiated. The phase reference selector captures the phase estimate immediately prior to termination of the adaptation period, outputting a predetermined phase reference until such termination, at which point the stored phase estimate is outputted. The timing control system minimizes the difference between the phase estimate and the output of the phase reference selector by altering the sampling rate, except during the adaptation period, during which the sampling rate is held constant.

Abstract: In a system in which active and standby units, each used to control a VCXO on the basis of a reference signal from a GPS receiver to generate a high-precision clock, constitute a redundant arrangement, and a clock is output from the active unit, a clock generating circuit has an arrangement in which when the active unit cannot receive any reference signal from the GPS receiver for some reason, free-running operation is performed in the control state the VCXO assumed when the reference signal stopped in the internal circuit of the active unit, and switching to the standby unit is not immediately performed, and an arrangement in which when the standby unit can normally receive the reference signal from the GPS, the output clock from the active unit during free-running operation is monitored, and the unit that is to receive the reference signal is switched from the active unit to the standby unit at the timing at which no influence is exerted on the output clock when a phase difference larger than a predetermine

Abstract: A method of synchronizing a base station and a remote station is presented. The base station is communicatively coupled with the remote station and a reference network. The base station clock signal is compared with a reference clock signal derived from the reference network and adjusted accordingly. The adjusted base station clock signal is then used to generate timing information in the form of a preamble, which is periodically transmitted from the base station over a wireless communication network to the remote station where a clock signal is generated. The remote station compares the clock signal with the timing information and adjusts the clock signal accordingly. This is done without reference to an external clock.

Abstract: A modem system includes a programmable synchronization signal format that can be configured at a first modem in response to a request received from a second modem. The synchronization signal format may define a number of parameters of the synchronization signal, such as the sign pattern for symbols transmitted by the first modem during a training sequence. The specific parameters of the synchronization signal format may be associated with the design and operation of the second modem. For example, the particular timing recovery and automatic gain control schemes used by the receiver portion of the second modem may be optimally initialized with a synchronization signal having a specific length, amplitude, or spectrum. In one embodiment, a synchronization signal is configured to convey a single frequency tone for use during a synchronization routine. The modem system may also employ similar techniques to generate, transmit, and analyze a programmable line impairment learning signal.

Abstract: A circuit comprising a first counter, a second counter, a third counter and a decoder, where the decoder may be configured to present a locked output signal. The first counter may present a first output signal in response to a start of frame signal and one or more control signals. The second counter may be configured to present a second output signal in response to the start of frame signal and the first output signal. The third counter may present a tracking control signal to the first counter in response to one or more of the control signals.

Abstract: A communication system (105) utilizes the global positioning system (GPS) to maintain a high degree of accuracy of synchronization of base-stations (115-116). When the GPS signal (106, 107, or 108) is absent, the communication system (105) employs an alternate signal (110-113), such as a WWVB, LORAN-C, and MSF signal, to provide redundant synchronization of the base-stations (115-116). To achieve the degree of synchronization accuracy provided by the GPS signal (106-108), the communication system (105) characterizes the alternate signal (110-113) by utilizing the GPS signal (106-108) when the GPS signal (106-108) is present. When the GPS signal (106-108) is absent, the characterized alternate signal is then employed such that synchronization of the base-stations (115-116) is transparent to the base-stations (115, 116).

Abstract: A circuit for glitch-free changing of clock having different phases. The circuit comprises a phase detector for receiving a data stream and a system clock, and generating a phase-up signal and a phase-down signal; a flag signal generator for receiving the phase-up signal and the phase-down signal, and then generating M flag signals, wherein the select signal corresponding to the enabled flag signal is enabled; an output stage for receiving the M select signals and the M clocks, and then outputting the system clock.

Abstract: A phase lock device and method applicable to a data transmission system, particularly to a high speed transmission system are provided. Based on that the optimum operation margin for delaying data strobe is to shift the edge of data strobe to the middle region of data signal, the phase lock device and method suggest a solution, by analyzing the influence of environmental and operational conditions on delaying data strobe and system clock, to adapt delay element to the variation of environmental and operational conditions, so that the delay of data strobe is always in such a range that the data receiver can be enabled to do accurate and reliable data reading, regardless of external interference.

Abstract: A phase detecting/collating circuit collates a phase of a reception serial data input from outside through an external interface circuit, a phase of the reception data shift clock output from the clock frequency divider/corrector circuit, and a phase of a phase collating clock obtained by delaying the reception data shift clock by ¼ periodic cycle of the reception data shift clock by means of the delay circuit. By the phase collation in the phase detecting/collating circuit, if a difference in phase capable of generating a reception error in the data transmission circuit is detected, the clock shortening timing signal or the clock elongating timing signal is output. A reception clock frequency divider/corrector circuit corrects such as to shorten or elongate said reception data shift clock when a clock shortening timing signal or a clock elongating timing signal is input, respectively. With this effect, the reception operation in the data transmission circuit is executed always normally.

Abstract: This vehicle communication system is suitable for high speed communication with small signal distortion. The communication system for a vehicle includes, provided with charge and discharge that allow a distributed capacitance of a signal line to be discharged by making a stored charge by-pass a pull-up resistor, or causing the distributed capacitance of the signal line 5 to be charged up by making a charge by-pass a pull-up resistor. The charge and discharge units charge or discharge for only a fixed period of time. This fixed period of time is shorter than 1 bit length of the signal, from when transistors are switched from on to off. For a node connected through the signal line, this fixed period of time is longer than the time taken for a reception circuit that is providing a reception signal from the signal line to switch on or off.

Abstract: As part of a preferred communication protocol, base stations which are synchronized to a PSTN of a wireless communication network, periodically transmits a preamble. A remote detects the preamble and, upon verification of the data contained in the base station transmission, sets its counter to an initialized state based on the received preamble. An early/late analysis of each subsequently received base station timing pulse is used to adjust both the mobile station timing and to adjust the output frequency of the mobile station master clock and codec clock to effectively maintain end to end synchronization with the respective base station and the PSTN throughout the duration of an established communication link.

Abstract: A synchronization message detecting unit detects a synchronization message from a line signal received from a line terminating unit. A synchronization message processing unit controls whether or not to select a clock reference received from the line as an active reference according to a quality level represented by the synchronization message. In this case, when an installed state detecting unit has determined that the synchronization message detecting unit has not been installed, the synchronization message processing unit does not select a clock reference corresponding to the synchronization message detected by the synchronization message detecting unit determined as a non-installed unit as the active reference.

Abstract: It is an object of the invention to provide a synchronizing circuit which prevents an occurrence of an unexpected output data caused by latching an input signal on a course of a transition thereof. An input signal Si is represented as a binary data having a width of three bits which increases by “1” every clock, and encoded into a signal having a width of eight bits. The encoded signal having the width of eight bits is latched and restarted synchronizing with a clock (CLK1) by a F/F circuit and another F/F circuit operating in accordance with an asynchronous clock (CLK2). The output signal of the F/F circuit is decoded into a signal having a width of three bits by the decoder, and outputted as an output signal So. Since an encoder is provided, the data before or after a transition can be correctly outputted, even when the data is latched by the F/F circuit on a course of the transition.

Abstract: A ring oscillator includes an even-numbered plurality of ring coupled delay stages. Each delay stage includes a differential amplifier, a voltage clamping circuit, and a current source. The differential amplifier receives first and second input signals from a preceding delay stage. The differential amplifier provides a first output signal and a complementary second output signal at first and second nodes, respectively. The voltage clamping circuit is coupled between the first and second nodes to limit a peak-to-peak voltage swing of each of the first and second output signals. The current source is coupled to the differential amplifier and varies a bias current in accordance with a delay bias voltage.