Abstract: A decoder/de-interleaver comprises a de-interleaver for de-interleaving received interleaved encoded data that includes periodic decoder synchronization signals to produce de-interleaved encoded data. A decoder decodes the de-interleaved encoded data to produce output data. The de-interleaver has a latency such that the de-interleaved encoded data is delayed by (B-1) times a period of the decoder synchronization signals plus a constant interval, where B is the interleave depth. A synchronization pulse generator receives the interleaved and encoded data and generates decoder synchronization pulses that are substantially coincident with the decoder synchronization signals. A delay unit is connected between the synchronization pulse generator and the decoder for delaying the decoder synchronization pulses by the constant interval. The decoder thereby receives decoder synchronization pulses that correspond to previous decoder synchronization signals, but functions properly because the relative timing is correct.

Abstract: The present invention is for fast, reliable recognition of coded signals where the signal includes a predetermined code sequence in a lead portion thereof. This has particular application in spread spectrum transmission and receptions. The code sequence is a long sequence of bits known to the receiver which breaks the long sequence into a series of bit segments which are more easily analysed. Each series of bits is analysed for a direct match and a decision whether a code segment has been received is based on the number of direct matches. For example, if there are 8 bit segments, each 16 bits in length, high reliability has been achieved if two direct matches are received within a time period corresponding t the transmission time of the code sequence. This system can also be used for assessing signal strength where many matches indicate good signal strength, approximately 50% indicates moderate signal strength, and less indicating poor signal strength.

Abstract: Digital methods and apparatus for reverse link signal detection and recovery in a mobile data base station. In accordance with the method, the received signal is frequency downshifted by multiplying the received signal by inphase and quadrature components of a local carrier oscillator, and the resulting downshifted inphase and quadrature components of the signal vector is sampled and digitized at a rate of more than twice the expected bit rate. Difference vectors for digitized downshifted signal vectors one expected bit time apart are determined and examined for detection of a dotting sequence and for estimation of the carrier frequency error, which on detection of the dotting sequence, is used to initially correct the digitized downshifted signal vectors for the frequency error. Techniques for bit timing recovery, frequency error correction during data detection and detection of voice versus data, as well as other features of the invention, are disclosed.

Abstract: A synchronizing signal detection apparatus of the present invention comprises a demodulator for digitally demodulating input signals, a partial matching error counter for comparing every bit of the demodulated input signal bit pattern demodulated by said demodulator with a part of the known synchronizing signal bit pattern. The apparatus further comprises a remaining bit matching counter for comparing the input signal bit pattern with remaining bits of the synchronizing signal bit pattern used in the partial matching error counter, or with all synchronizing signal bit pattern, for every bit, when an error bit number, which is compared in the partial matching error counter, is equal or less than a first threshold value. When the error bit number compared in the remaining bits matching error counter is equal or less than a second threshold value, synchronizing signal is assumed to be detected. In the apparatus of the present invention, bit pattern comparison numbers are decreased.

Abstract: Apparatus for detecting synchronisation data in an input serial-bit digital signal formed of a series of word blocks each including a predetermined serial group of m bits forming said synchronisation data, comprises a deserialiser for deserialising the input signal to parallel-bit p-bit words where p<m, a delay for delaying at least p-1 bits of each p-bit word by one p-bit word period, and logic for receiving successive groups of 2p-1 bits each formed of a said p-bit word and the adjacent p-1 bits of the preceding or succeeding word. The logic is arranged to detect an initial portion of said synchronisation data by comparing bit sequences in a said group of 2p-1 bits with the bit sequence at the beginning of said predetermined group of m bits. On detection of said initial portion of the synchronisation data, bits of one or more succeeding groups of 2p-1 bits are compared with succeeding bits of said predetermined m bits in dependence upon the position of said initial portion in the corresponding 2p-1 bits.

Abstract: In a spread spectrum communication apparatus, frame synchronization is established by inserting data for frame synchronization as a part of a synchronization word of a transmission frame on a sending side and detecting the data for frame synchronization from reproduction data of a reception frame on a receiving side. A frame synchronization pseudo-noise train generator section generates a pseudo-noise train for frame synchronization used as the frame synchronization data. A frame synchronization correlator section receives the pseudo noise train for frame synchronization and reproduction data to output a signal when the value of correlation of the pseudo noise train for frame synchronization and the reproduction data is not smaller than a reference value. A reception frame timing generator section outputs a reception synchronization word timing signal with the output signal of the frame synchronization correlator section being taken as a reference.

Abstract: A diversity receiver (200) recovers clock information from different versions (301, 302) of a transmitted signal (106). The diversity receiver (200) receives the different versions (301, 302), converts the versions (301, 302) into samples (307, 317) via a common sampling clock (309). The receiver (200) then correlates the samples (307, 317) with like synchronization patterns and uses clock information from the received version (307 or 317) which gives the greatest correlation output signal (504, 506) for data detection in one of two detectors (323, 326). The choice of detectors (323, 326) is determined by the diversity receiver (200) by counting the total number of bit-differences output by detectors (323, 326) over a predetermined time period and comparing the total bit-differences with a number represented by a threshold signal (330).

Abstract: A receiver capable of effecting frame synchronization control even at the time of initial acquisition and hand off in the presence of frequency selective fading.

Abstract: A method and apparatus minimize false detection of packet data in a receiver (202) due to noise in a communication system (100) utilizing time slots (420). Some time slots (420) contain a data packet (418), while others contain only noise. The data packet (418) includes a sync word (602) and an error-detecting code word (604, 606, 608). The receiver (202) is synchronized (1006, 1008) with a nominal predetermined timing of the time slots (420), and determines (1014) time windows (808) for receiving the data packets (418). During each of the time windows (808) data is received, demodulated, and stored (1016), and a predetermined portion of the data stored is searched (1018) to locate a point of maximum correlation between the data and a data template (902) matching the sync word (602).

Abstract: A synchronizing signal generating apparatus generates a synchronizing signal from digital data in which a synchronizing signal formed of a fixed data pattern having a predetermined bit number is inserted at a predetermined time interval L.

Abstract: A multi-channel transmission system operates by transmitting digitally-coded signals modulated in sequential symbol blocks at a plurality of carrier frequencies, and receiving and demodulating the digitally-coded signals, wherein, in the transmitting, a test signal is generated in at least one symbol block, the test signal containing at least one periodically continued, differentially coded, self-orthogonal sequence of a constant amplitude modulated to a part of the plurality of carrier frequencies within a symbol block in differential coding.

Abstract: A synchronization pattern is provided within an incoming waveform which represents a serial data stream transmitted at a rate determined by a data clock. The synchronization pattern includes a periodic training portion and a sync word portion. The periodic training portion is periodic and has a preselected period. As the periodic training portion is received, a receiver clock phase-locks to the periodic training portion of the incoming waveform, and a sampling circuit periodically samples the incoming waveform relative to the phase and frequency of the receiver clock to produce sample words. Thereafter, a subset of the sample words are selected utilizing a selection pattern having a period equal to the period of the periodic training portion of the incoming waveform. Utilizing the selected subset of sample words, a sync indicator word is produced and compared to preselected criteria. Such a sync indicator word may be produced with reference to the sign of each sample word of the subset of sample words.

Abstract: A radiotransmission station transmits digital data at a predetermined rate to a receiving station. The receiving station is controlled by a timing circuit which recognizes a predetermined enabling code. The digital data is transmitted as bit sequences and each sequence contains a first group of bits for synchronizing the timing circuit and the transmission rate. This first group of bits is followed by a second group of bits which includes the enabling code. The recognition of the enabling code enables the reviewing station to receive and process the transmitted information. The enabling code is derived from a sequence of logical "1" and "0" bits and certain bits of the sequence are altered to form groups of three like bits (111,000). Each group of three bits has no more than two adjacent pairs of like and opposite bits (00,11).

Abstract: A high bit-rate serial communications link encodes data by inserting non-data 0's and 1's. These extra bits are removed by a decoder at the receiving end of the link. Transmission of data can be made along optical fibers.