Abstract: The present invention relates to a method and apparatus for correcting frequency offset of a local oscillator in a direct sequence spread spectrum receiver such as Universal Mobile Telecommunications System (UMTS). Received signals comprise a plurality of sequential slots of data. At least one of these includes synchronization data. A correlation is performed between this received data and a locally stored synchronization code. Subsequently, the received data is phase adjusted and a further correlation performed between the phase adjusted data and the locally stored synchronization code. The strongest correlation peak is then determined and a phase offset to be applied to the local oscillator is estimated from the phase adjustment required to produce the strongest peak. This is subsequently applied to the local oscillator.

Abstract: The repetitive structure of a preamble signal is exploited to enhance timing synchronization performance and frame start detection performance under adverse channel conditions. Received values are cross-correlated in time against a known noise-free version of the preamble. The presence of peaks in the cross-correlation output indicates presence of a frame. The peak locations provide symbol timing. Further cross-correlation processing and/or non-linear processing can be used to enhance the signal to noise ratio of the peaks.

Abstract: Fast detection of a selected portion of a data packet (e.g. the preamble of a Bluetooth data packet) is accomplished by defining a reference signal waveform conforming to an expected waveform representing a signal modulated in accordance with the selected portion of a data packet. A waveform representing a received data signal containing a data packet with the selected portion is derived, and the reference signal waveform is correlated with this derived waveform to produce a correlation result. This correlation result is used to identify the selected portion in the received data signal.

Abstract: A transmission method uses multiple kinds of control codes to be exchanged on a serial transmission path between a sender side and a receiver side, and each of the multiple kinds of control codes has bits smaller in number than a predetermined fixed length.

Abstract: A synchronism pattern detecting timing recorder (20) records a synchronism pattern detecting timing at which a synchronism pattern is detected in reception data, a synchronism decider (12) collates the reception data with reference data to decide whether or not the reception data is consistent in phase with the reference data, and a timing generator (22) operates, when the synchronism decider (12) gives a decision for inconsistency in phase, for a match between the synchronism pattern detecting timing recorded in the synchronism pattern detecting timing recorder (20), as a subsequent one, and a timing of a synchronism pattern of the expectation data, and the subsequent synchronism pattern detecting timing in record is used to render the phases consistent, allowing for a rapid synchronization to be obtained, without the need of waiting a detection of synchronism pattern, even with an inconsistency in phase due to a false synchronism pattern.

Abstract: There is provided a digital data receiver for recovering at least one message word signal from a digital data frame.

Abstract: A frequency offset correction value estimation section (21) receives a signal including a predetermined fixed pattern from a transmission side, thereafter, selects a combination of fixed patterns used in a process of estimating a frequency offset is selected depending on the state of a channel, and an estimation result of the frequency offset calculated by the combination of the fixed patterns is output as a correction value of a determined frequency offset. A frequency offset correction section (22) receives the received signal obtained after the correction is performed for correcting a frequency offset of the received signal on the basis of the correction value, and an equalizer (23) demodulates the received signal by using a predetermined algorithm.

Abstract: Method for synchronizing frames by using pilot patterns in a compressed mode. In a case a W-CDMA mobile communication system is operated in a compressed mode, the present invention permits to restore perfect frame synchronization words in frames by using dedicated pilot sequence pattern, and achieve frame synchronization by using correlation of the restored frame synchronization words, even if all the 15 slots of one frame are not transmitted.

Abstract: Techniques for incorporating non-pilot symbols along with pilot symbols to improve the estimate of the characteristics (e.g., amplitude and phase) of a communication link. A pilot filter weighs samples corresponding to pilot and non-pilot symbol by different sets of coefficients, which have values determined by and/or corresponding to the confidence in the detected sample. Samples corresponding to pilot symbols are typically associated with higher degree of confidence and are weighted more (e.g., with weights of 1.0). Samples corresponding to non-pilot symbols are typically associated with lower confidence and are weighted with values that may be variable and dependent on the degree of confidence in the samples (e.g., with weights ranging from 0.0 up to 1.0). The weights are updated based on a particular estimator such as a MAP (Maximum a Posteriori) estimator, a MLE (Maximum Likelihood Estimator), or some other estimator.

Abstract: A transmitting apparatus, a receiving apparatus, and a communication system are provided that allow a reduction in a frame loss due to interference caused by use of the same channel. A transmitting apparatus disposed in a base station includes a GPS receiver for receiving a GPS signal, a timing generator for controlling respective function blocks in accordance with the GPS signal and an inter-base-station control signal so as to precisely synchronize the timing of frame transmission among base stations, the front-end transmission processing unit including for converting transmission information into transmission time slots, a frame generator for generating a frame including a plurality of time slots and one frame guard, and a back-end transmission processing unit for transmitting the generated frame as a radio signal.

Abstract: A method for maintaining synchronization between a transmitter and a receiver is disclosed. The method offsets time drift which causes a degradation in the quality of communication between a transmitter and a receiver. The method comprises using a first sampling time to obtain a first sequence of hard decision symbols for decoding contents of a portion of a received packet, switching to a second sampling time upon degradation in a reliability of the symbols, and using the second sampling time to obtain a second sequence of hard decision symbols for decoding contents of a remaining portion of the received packet.

Abstract: A method and apparatus for time-shift extraction in a wideband transmitted signal containing strong narrowband interference or noise. The time-shift extraction is based on the time domain and frequency domain relation of symbol misalignment. The invention uses the sign of the product of a recieved signal sample and a reference symbol in the frequency domain to determine the time-shift. It does not rely on the signal magnitude and is therefore less dependent on the signal gain. It also does not rely on the soft phase values, which have ambiguity for values more than three hundred sixty (360) degrees.

Abstract: The frame synchronizing circuit establishes frame synchronization by detecting a sync pattern laid in an incoming frame. The frame synchronization circuit comprises a first frame synchronizing unit and a second frame synchronizing unit. The first and second synchronizing units synchronize with a first pattern, a second pattern at a first position and a second position, respectively. Thereafter, when the first position used for the synchronization by the first frame synchronizing unit is found to be in error, the first frame synchronizing unit synchronizes with the second pattern at the second position used by the second frame synchronization unit.

Abstract: There is provided an apparatus and method for generating a frame sync word and verifying the frame sync word in an asynchronous CDMA communication system. In the apparatus for generating a sync word for synchronization of frames each having a predetermined number of slots, each of at least two m-sequence generators generates the predetermined number of sequential elements, and a selector multiplexes the sequential elements received from the m-sequence generators and assigns the multiplexed elements in the slots.

Abstract: Selector circuits are connected in a hierarchical arrangement. Each of the selector receives two of synchronizing pattern detection signals and two of synchronizing pattern position signals and selects one of the received synchronizing pattern position signals in accordance with values of the received synchronizing pattern detection signals, so that the position of a synchronizing pattern on parallel data can be identified in a tournament fashion.

Abstract: A signal processing circuit having a data sync signal detector and a disk device. Input data read from a magnetic disk is input to a data discriminator. A data discrimination output constituting a code bit output discriminated by the data discriminator is input to a post-coder the output of which is input to a decoder and a (1+D) processing unit. The processed output of the processing unit is input to an error detection/correction unit and separated into bit strings of odd numbered bits and even numbered bits, divided into groups. An error detection/correction output is input to a data sync signal detector, and matched against a sync pattern. When the number of coincident groups is greater than a threshold value, a sync signal is output and upon detection causes the decoder to demodulate the data.

Abstract: A system and method of frame synchronization and detection for use in a digital receiver within a communication system. The digital radio communication system includes a receiver for receiving a signal stream that includes data frames. Each frame includes an arbitrary data sequence and a unique word. A predetermined number of contiguous bits from the unique word are appended to the beginning of each data frame to identify the start of the data frame. The communication system comprises a sampling circuit for sampling symbol levels, a filter to implement the cross correlation of the received signal with the stored unique word, a threshold detector circuit to detect when frame synchronization is achieved as well as additional circuitry to refine the estimate from the threshold detection circuit. The design utilizes coherent demodulation. However, the design is equally applicable to non-coherent demodulation. In one embodiment, the sampling rate is assumed to be two samples per symbol.

Abstract: The present invention provides an apparatus and a method for improved connectivity in wireless optical networks. Therefore at least two or more receiving units are used which receive an infrared signal and convert it to a digital signal. The digital signals represent data in the form of frames whereby each frame comprises at least a data field and a header field containing a preamble. A selector determines a measure related to the signal-to-noise ratio of the preamble and compares the measures in order to select the best suited signal for further processing.

Abstract: Method for determining the sampling phase of a signal modulated by digital modulation, is described. The method includes oversampling by factor m, the coordinates of L consecutive symbols. The oversampled coordinates of the L symbols are then converted into angular values. The angular values are folded over onto a point of the constellation of the modulation. The noise in the angular values is estimated for each oversampling phase, with respect to the point, and the oversampling phase exhibiting the lowest noise is selected. The subject of the invention is also a synchronization word detection process.

Abstract: Methods and apparatus for use in aligning frames in a receiver of a data transmission system include checking one or more bit positions associated with a received data stream to determine a number of bits in the bit positions, respectively, that match a predetermined bit pattern. The number for a bit position is compared to a first threshold value and a second threshold value. A bit position is identified as being associated with a false framing pattern or mimic when the number is not less than the first threshold value. A bit position is identified as a potential framing bit position or possible framing bit position when the number is not less than the second threshold value. The first threshold value is changed when a bit position is identified as a potential framing bit position and another bit position is identified as being associated with a false framing pattern.

Abstract: A synchronization signal includes a plurality of predetermined synchronization symbols shaped by a predetermined symbol pulse. A receiver (100) receives (202) a signal including the synchronization signal, and a processor (106)determines (204) a first plurality of cross-correlations between the predetermined symbol pulse and the received signal. The processor calculates (206) a plurality of sums of products of the plurality of predetermined synchronization symbols and a predetermined subset of the first plurality of cross-correlations. The plurality of sums are mathematically equivalent to a second plurality of cross-correlations between the synchronization signal and the received signal. The processor locates (208) a peak of the plurality of sums to establish receiver synchronization.

Abstract: A system and method for synchronizing a number of specialized circuits or application-specific integrated circuits to a common timing standard is provided. The system includes a first communications device including at least first and second type communication paths which is configured to receive first and second timing signals in the first type communications path and to transmit data on the second type communications path. The data is transmitted in association with the received first timing signal. A controller or signal processor element is coupled to the first device and configured to receive the second timing signal and produce a timing word therefrom. A second communications device is coupled to the processor and configured to receive the second timing signal and produce a timing word therefrom. The second communications. device receives the timing word and the transmitted data and derives synchronization information therefrom.

Abstract: A data communications subsystem (15) including a digital signal processor (DSP) (20) for performing bit insertion to preclude the inadvertent serial transmission of a protocol flag sequence is disclosed. A trigger sequence detection process (40) applies an infinite impulse response (IIR) filter to a current sequence of the input bitstream to generate a insertion bitstream that is bit sychronized with the the input bitstream. A bit insertion process (50) then inserts bits into the input bitstream at bit positions indicated by the insertion bitstream. The trigger sequence detection process (40) may be applied to subsequent sections of the input bitstream, as it is not dependent upon the results of the bit insertion process (50).

Abstract: Candidate limiting section 104 outputs to correlation value calculating section 105 only the TFCI coding sequences corresponding to TFCI numbers that are actually used based on TFCI numbers that are included in the group of TFCI numbers notified from a layer which is upper than the physical layer, correlation value calculating section 105 calculates the correlation values between the coding sequences outputted from candidate limiting section 104 and the received TFCI and stores the results in correlation value memory 106, maximum value detecting section 107 notifies error correction decoding section 108 of the TFCI number corresponding to the maximum correlation value among the correlation values stored in correlation value memory 106, and error correction decoding section 108 performs an error correction decoding on the data stored in data memory 103 according to the transmission format specified based on the notified TFCI number.

Abstract: A technique for encoding digital communication signals. Data symbols are augmented in pilot symbols inserted at predetermined positions. The pilot augmented sequence is then fed to a deterministic error correction block encoder, such as a turbo product coder, to output a coded sequence. The symbols in the error correction encoded sequence are then rearranged to ensure that the output symbols derived from input pilot symbols are located at regular, predetermined positions. As a result, channel encoding schemes can more easily be used which benefits from power of two length block sizes.

Abstract: A method and a system for framing variable-length packets in a data communications system are disclosed. The successive variable-length packets carrying users' data, are formed in a stream of chained packets comprising a header. Two CRC's are computed. One over the data and another one over the header however, including also the data CRC of the immediate previous packet, thus chaining successive packets in a steam of such packets. The invention also assumes that encryption is performed independently over header and corresponding CRC's and, on the other hand, over the data of current packet. The invention allows to better adapt the transportation of multi-media users' data in packets of variable-lengths while securing transport by chaining successive packets, thus preventing that accidental or malicious deletion and insertion of packets occur and remain undetected.

Abstract: A network device configured to detect a framing pattern includes a data scanner and a frame detector. The data scanner examines parallel bytes of data and detects portions of a framing pattern in the parallel bytes of data, identifies the phase of the framing pattern and outputs alignment information and phase information when a framing pattern has been detected. The frame detector receives the alignment information and phase information and determines whether framing patterns having the same phase relationship have been detected within a predetermined number of frames.

Abstract: A method for transporting and aligning data across a set of serial data streams. The method includes creating a predetermined number of data streams from a first data stream. The first data stream has a first predetermined bit width and each data stream of the predetermined number of data streams has a second predetermined bit width smaller than the first predetermined bit width. In addition, the method includes inserting an alignment pattern in each of the predetermined number of smaller data streams. The predetermined number of smaller data streams are combinable into a data stream having the first predetermined bit width based on the alignment pattern. The method also includes preparing the predetermined number of smaller data streams for transmission. An apparatus for performing the method is also disclosed.

Abstract: Using a combination of auto-correlation and cross-correlation techniques provides a symbol timing recovery in a Wireless Local Area Network (WLAN) environment that is extremely robust to wireless channel impairments such as noise, multi-path and carrier frequency offset. An auto-correlator provides an estimate for a symbol boundary, and a cross-correlator is subsequently used to more precisely identify the symbol boundary. Peak processing of the cross-correlation results provides further refinement in symbol boundary detection. In receiving a packet conforming to the IEEE 802.11a standard, the method requires a minimum of only three short symbols of the 802.11a short preamble to determine timing, and guarantees timing lock within the duration of the 802.11a short preamble. This method and system can be easily applied to any other preamble based system such as 802.11g and High Performance Radio LAN/2 (HIPERLAN/2).

Abstract: A method and a device are provided for acquiring synchronization to a received digital signal. The signal consists of consecutive frames with a frame synchronization pattern distributed over a significant part of a frame. A number of blocks of constant length (303) are received (302) and a passage is selected (304) from the same location within each received block. A regularly occurring bit value is observed (305, 306) at a constant bit position within the selected passages. As a response to an observed regularly occurring bit value, the corresponding position in the received digital signal is used (308, 309) as a starting point, and the rest of the distributed frame synchronization pattern is located within the received digital signal.

Abstract: A system and method of timing estimation for use in a digital receiver within a communication system. An algorithm calculates the timing offset by evaluating the spectral component at the symbol clock frequency. The spectral component is generated using a nonlinearity operation. However, the maximum likelihood non-data-aided timing estimation equation reveals an alternative approximation for the logarithm of the hyperbolic cosine function present in the maximum likelihood equation, which offers a compromise between implementation complexity and variance performance. The estimated timing offset is then fed to a timing correction unit, which calculates the data samples corresponding to the sampling clock phase and removes the redundant samples. The ideal sampled signal is then forwarded to additional synchronization and functional units for further processing.

Abstract: A digital signal detection system, method and computer program product, including (a) partitioning a digital signal into a plurality of frames; (b) calculating a number of zero crossings of the digital signal within each frame; (c) determining whether or not an absolute value of a difference of the number of zero crossings in between frames is less than a first predetermined value; (d) determining whether or not a sum of the zero crossings of the frames is greater than or equal to a second predetermined value and less than or equal to a third predetermined value; (e) calculating a maximum amplitude of the digital signal for each of the frames; (f) calculating an average amplitude of the digital signal for all of the frames; (g) determining whether or not an absolute value of a difference between the maximum amplitude of a frame and the average amplitude is less than a fourth predetermined value times the average amplitude for each of the frames; and (h) determining that a frame contains a narrowband digital s

Abstract: A communication device includes a transmitter and receiver. The transmitter includes an M-ary encoder configured to generate an M−1 number of distinctive symbols each comprising k bits. M is equal to 2k and k is a positive integer. The transmitter also includes a code generator configured to produce spread spectrum codeword sequences based on the symbols generated by the M-ary encoder and based on a first and a second Gold code polynomials. The transmitter sends a radio signal based on the spread spectrum codeword sequences. The receiver is configured to receive the radio signal. The receiver includes a first shift register configured to receive an input signal generated based on the received radio signal and a second shift register configured to receive and circularly shift a locally generated codeword sequence that is identical to the codeword sequence used to encode the symbols.

Abstract: A User Equipment (UE) has a circuit that performs the acquisition for the low chip rate option of the Universal Mobile Telecommunication System (UMTS) Time Division Duplex (TDD) standard as formulated by the Third Generation Partnership Project (3GPP). The present invention implements the detection of the basic SYNC code; the determination of the midamble used and the detection of the superframe timing based on SYNC code modulation sequence. This enables reading of a full Broadcast Channel (BCH) message.

Abstract: A method is provided for transmitting a composite digital audio broadcast signal having an analog portion and a digital portion to mitigate intermittent interruptions in the reception of said digital audio broadcast signal. The method comprises the steps of arranging symbols representative of the digital portion of the digital audio broadcast signal into a plurality of audio frames, producing a plurality of modem frames, each of the modem frames including a group of the audio frames, and adding a frame synchronization signal to each of the modem frames. The modem frames are then transmitted along with the analog portion of the digital audio broadcast signal, with the analog portion being delayed by a time delay corresponding to an integral number of the modem frames. The invention also encompasses radio receivers and transmitters which process signals according to the above methods.

Abstract: A CDMA system in which the base stations transmit a synchronization channel comprising a primary subchannel from which slot synchronization is determinate and a secondary subchannel containing a cyclic hierarchical code unique for each base station and for each slot in a frame. The cyclic code is derived from a first code unique to a base station and a different cyclic shift of a second code also unique to the base station in each slot of a frame. Mobile stations quickly and with low-complexity detectors determine slot synchronization from the primary subchannel and then determine base station identification and frame synchronization by correlating samples of signal received on the secondary subchannel with a set of first codes and cyclic shifts of corresponding second codes.

Abstract: A method and apparatus reduces the complexity of initial synchronization in mobile terminals operating in TDMA communications systems. A TDMA transmission comprises multiple repeating time slots marked by synchronization words. Initial synchronization requires locating at least one time slot in the received signal. Information in a slot is received as a sequence of symbols at a defined symbol rate. The mobile terminal receives the TDMA transmission for a period longer than one time slot and samples a baseband version of the received signal at M times the symbol rate. This oversampling produces M symbol-rate sample sets, with each sample set corresponding to one of M sampling phases. The mobile terminal performs a FFT on each one of the plurality of the M sample sets after raising it to the nth power, where n is based on the number of modulation phases used to transmit the symbols.

Abstract: A base station including a transmitting and receiving amplifier for amplifying CDMA signals exchanged with a mobile station; a radio stage connected to the transmitting and receiving amplifier for carrying out D/A conversion of a transmitted signal that undergoes baseband spreading, followed by quadrature modulation, and for carrying out quasi-coherent detection of a received signal, followed by A/D conversion; a baseband signal processor connected with the radio stage for carrying out baseband signal processing of the transmitted signal and the received signal; a transmission interface connected with the baseband signal processor for implementing interface with external channels; and a base station controller for carrying out control such as management of radio channels and establishment and release of the radio channels. The base station communicates with the external channels by mapping logical channels into physical channels. The CDMA signals are spread using a short code and a long code.

Abstract: Definition takes place of a sliding window of width Ne times the sampling period (Te); for each sliding window calculation takes place of the sum of the elementary powers of the correlation samples located in said window; determination takes place of the window for which the sum of the powers is at a maximum, the synchronization then being defined by the position of the synchronized window on the window having the maximum power sum and by the rank of each correlation sample within said window.

Abstract: A device and method for regulating a sampling rate in a digital data transfer system includes transmitting a synchronizing word used for receiver-side regulation of the sampling rate at regular time intervals. The received signal is filtered by a rate-regulating criterion filter and is simultaneously detected to recognize the synchronizing word. The initial value of the rate-regulating criterion filter controls an adjusting logic for the sampling rate once the synchronizing word is recognized. A rate is formed for the initial value of the rate-regulating criterion filter and the rate undergoes high pass filtering before it is fed to the adjusting logic. An apparatus for controlling the sampling includes a clock control criterion filter, an adjustment logic device, a switch, an apparatus identifying the synchronization word, a magnitude formation circuit, and a high-pass filter. The formation circuit and the high-pass filter are disposed between the criterion filter and the logic device.

Abstract: A timing acquisition algorithm for locating the sync timing position of a sync word embedded in a received signal for achieving synchronization between the received signal and a base station, e.g., a base station receiving the received signal, within a wireless telecommunications system. The timing acquisition algorithm is preferably a set of programmable instructions incorporated within a software package and processed by a processor at the within the wireless telecommunications system, such as at the base station. The timing acquisition algorithm gets rid of the unlikely sync timing position for each branch of an adaptive antenna array in the first step; gets rid of the unlikely sync timing position for all branches in the second step; and uses optimal diversity combining for the remaining timing position and uses the conventional correlation or mean-square-error (MSE) approach on the combined data in the third step to finally locate the timing position of the sync word.

Abstract: A system and method for synchronizing a number of specialized circuits or application-specific integrated circuits to a common timing standard is provided. The system includes a first communications device including at least first and second type communication paths which is configured to receive first and second timing signals in the first type communications path and to transmit data on the second type communications path. The data is transmitted in association with the received first timing signal. A controller or signal processor element is coupled to the first device and configured to receive the second timing signal and produce a timing word therefrom. A second communications device is coupled to the processor and configured to receive the second timing signal and produce a timing word therefrom. The second communications. device receives the timing word and the transmitted data and derives synchronization information therefrom.

Abstract: Digital signals transmitted on an RF carrier modulated in phase and amplitude and subject to noise constitute separate bursts each comprising information symbols of data and a pair of separated unique words. The signals are subjected to processing which involves reception of the signals and an initial conversion to approximate baseband and then analog to digital sampling. Quadrature and in phase samples are then stored in a buffer. The buffered samples are subjected to coarse timing, coarse frequency synchronization, a first phase correction, fine timing, further phase and amplitude correction and finally to fine frequency correction and subsequent reliability estimation.

Abstract: A received signal phase detecting circuit in provided in which the circuit scale is small. The circuit functions so as to capture a frame synchronizing signal from a demodulated baseband signal, extract a symbol stream during the period of frame synchronizing signal from the demodulated baseband signal through delay circuits (41, 42) at a timing matching the bit stream of the captured synchronizing signal, rotating the phase of a corresponding symbol extracted from the symbol stream when the big in the bit in the bit stream is logic “0” by 80°, outputting the symbol after the phase rotation and a corresponding symbol extracted from the symbol stream when the bit in the bit stream is logic “1” from a 0°/180° phase rotating circuit (43), operating the cumulative average of the output from the 0°/180° phase rotating circuit (43) for a specific period through cumulative averaging circuits (45, 46), rotating the phase of the outputs therefrom through a 22.

Abstract: Method and apparatus for synchronizing communication between a battery and an electronic device are disclosed. Bytes consisting of a number of bits are transmitted between the electronic device and the battery. A predetermined bit sequence is appended to at least some of the bytes prior to transmission. The time interval between given shifts in the predetermined bit sequence is used to synchronize the communication.

Abstract: The present invention relates to methods and devices for receiving signals in a Wireless Local Area Network (wireless LAN, or WLAN), particularly in the case that the signals are Orthogonal Frequency Division Multiplexed (OFDM) signals. A symbol timing apparatus for an OFDM receiver is disclosed having: means for determining the correlation of corresponding samples of two received preamble symbols, one said sample delayed a predetermined duration with respect to the other; means for determining the maximum correlation value within a predetermined integration window, said maximum value indicating the start of a symbol; wherein the integration window duration is not equal to said delay duration.

Abstract: A digital system (100) has two or more nodes (120, 130) and a communication channel (110, 111) for transferring a single stream of ordered data from one node to another. The communication channel (110) has a number of data links (110a-110g) for transferring a plurality of sub-streams of data in a parallel fashion in order to transfer more data than a single data link is capable of transferring. Receivers (132a-132g) each have synchronizing circuitry (200, 202) for synchronizing a byte clock and a frame pulse of each received data sub-stream to the byte clock and frame pulse of a preselected master one of the receivers such that inherent data skew is eliminated.

Abstract: A digital data separator that is capable of separating data signals and clock signals from an encoded data stream. The digital data separator includes a synchronizer to synchronize the encoded data stream with the system clock of the digital data separator. An up-counter counts the number of clock pulses between valid logic 1's in the encoded digital data stream. Combination logic compares the value of the up-counter with established threshold values to determine whether the data separator has received a valid logic 1. The combinatorial logic also reset the up-counter on determining that a valid logic 1 was received.

Abstract: In the transmission device, a synchronization pattern made by arranging a predetermined basic pattern consisting of a combination of a predetermined number of symbols and a reversal basic pattern made by reversing a polarity of each symbol of the basic pattern, in the order according to a reversal pattern, is generated, and transmission data obtained by adding thus obtained synchronization pattern at predetermined timing is transmitted. In the reception device, the basic pattern and reversal basic pattern in the synchronization pattern are correlated with each other by a matched filter (11) corresponding to the basic pattern, and the correlation of the reversal pattern which appears in a signal obtained as a result, is taken by a matched filter consisting of delay portions (12), multipliers (13) and an adder (14).

Abstract: In the present invention, UW gate signal generator generates a UW gate signal for detecting a unique word. Gate circuit masks received signal using UW gate signal. PN detector compares a preset unique word signal set value and the signal output from inverting circuit during the active-high interval of UW gate signal, detects whether or not they are matching, and outputs the result. UW detector compares a preset unique word signal set value and the signal output from gate circuit during the active-high interval of UW gate signal, and outputs UW detection signal. Error detector outputs a detection stop signal for stopping unique word detection based on the signals output from PN detector and UW detector.