Abstract: A communication system, clock generation circuit, and method are provided for receiving jitter upon data and to generate a clock reference that does not contain the received jitter. The clock reference can be used either by a digital subsystem of a communication system node, or can be transmitted as substantially jitter-free data from that node to a downstream node of the communication system. Instead of recovering the clock reference from the data having jitter, a pattern is regularly defined within the data stream preferably at periodic, timed intervals. The data pattern may be made up of a series of non-transitions which, regardless of any jitter in the data itself, does not impute any jitter onto a phase-locked loop triggered from an edge of the non-transitioning data pattern. Using the edge as a reference point, a jitter-free clocking signal can be derived at the same frequency as a clocking signal which would normally be produced from the jitter-induced data.

Abstract: In a communication system based on OSI (Open Systems Interconnection) Reference Model, a pattern body generation circuit of a transmitting device generates and outputs a jitter test pattern body for jitter test. A selector selects an output (frame data) of a transmitting-end upper circuit during normal communication and selects an output (pattern body) of the pattern body generation circuit during jitter test. A transmitting-end MAC circuit performs transmitting-end processing of a MAC layer on the data selected by the selector to thereby obtain a MAC frame. A receiving-end MAC circuit performs receiving-end processing of a MAC layer on a received frame in MAC frame format to thereby obtain a payload. A pattern body verification circuit verifies a pattern body that is a payload obtained by the receiving-end MAC circuit during jitter test against a corresponding pattern body before transmission.

Abstract: A communication apparatus which includes a clock generation circuit outputting a plurality of clocks, each of said plurality of clocks having a different phase from each other; a synchronization detection block receiving a sync word and a payload having a predetermined length after receiving said payload, sampling said sync word by using each of said plurality of clocks and to output a first signal indicating a clock or clocks capable of sampling said sync word successfully, said synchronization detection block being capable of sampling said payload by using a clock or clocks inputted thereinto; a clock phase selection block coupled to said synchronization detection block to-receive said first signal to select one of said plurality of clocks in accordance with said first signal and to output a second signal indicating a selected clock; and a clock gate unit coupled between said clock generation circuit and said synchronization detection block and coupled to said clock phase selection block to receive each of

Abstract: A method and apparatus having a modified Reed-Solomon decoder is used for finding a specific code group used by a base station and the frame timing synchronization with the base station. The modified Reed-Solomon decoder uses a standard Reed-Solomon decoder and some reliability measurements computed from the received code word symbols. If the reliability of a received symbol is too low, this symbol is considered as erasure. By selecting code word symbols with higher reliabilities and erasing code word symbols with lower reliabilities, the symbol error probability is reduced and the performance is improved. Several modified Reed-Solomon decoders and a few decoding strategies are introduced in order to decode the received code word sequences with a power- and memory-effective method.

Abstract: A method and apparatus for frame synchronization in digital communication systems using multiple modulation formats perform a search for a differential frame alignment sequence (FAS) to frame-align the received digital stream and determine the polarity of the stream. Embodiments of the invention are compatible with Differential Phase Shift Keying (DPSK), Duobinary Signaling (DBS), and ON/OFF Keying (OOK) modulation formats.

Abstract: A method includes the steps of receiving a signal indicative of data bits, and performing per survivor processing-iterative timing recovery (PSP-ITR) on the received signal to generate probabilities of the data bits. To perform PSP-ITR on the received signal, the signal can be processed using a per survivor processing-soft decision algorithm (PSP-SDA) which jointly performs timing recovery and equalization in accordance with embodiments of the present invention. The soft decision algorithm (SDA) can be, for example, a Bahl, Cocke, Jelinek, and Raviv (BCJR) algorithm or a Soft Output Viterbi Algorithm (SOVA) modified in accordance with the concepts of the present invention such that it is configured to implement per survivor processing (PSP) to jointly perform timing recovery and equalization.

Abstract: A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from ?/2, ?/4, ?/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of ?/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

Abstract: A method and system of decoding a convolutionally encoded data block having known padding bits. A Viterbi decoder is constrained to a state corresponding to k?1 padding bits immediately adjacent to data bits of the data block, where k is a constraint length of a convolution encoder used to encode the data block. Symbols of the encoded data block that have influence only from the padding bits are discarded.

Abstract: A method for word synchronization can be applied to asynchronous devices including SERDES devices connected across serial lines. A state transition methodology characterizes the state of the device based on control characters received consistently across the serial lines and channels the system to a state of word synchronization. Loss of synchronization and transmission errors lead to a re-establishment of synchronization.

Abstract: A transmission interval counter measures the period of a packet sync generated in a sync generator. A comparator compares the period of the packet sync to a reference interval as selected by a type selector to calculate a period error. A correction value calculator calculates a correction value based on the period error. An adder sums the correction value to a predetermined value to output a sum. A frequency dividing counter counts the high-speed clock signals to output its count, and is reset by a pulse. A comparator outputs the pulse when the count coincides with the sum. A circuit generates clocks synchronized with the pulses. A circuit frequency-divides the clocks by ? to generate synchronization signals.

Abstract: The present invention provides a method for matching the rate of presentation of digital video data at a receiver/client with the rate the server is serving the data without the need of a voltage control oscillator or other hardware. An embodiment of the invention compares the presentation time at the receiver with the server elapsed time estimated from timestamp values on the served data. When the presentation time and the server elapsed time differ by an unacceptably large amount, an adjustment is made to the audio data stream to re-synchronize the presentation time with the elapsed time, which effectively also synchronizes the overall presentation rate with the overall server rate. The video data stream is then synchronized to the adjusted audio stream. The video data stream and audio data stream are converted to analog signals for presentation.

Abstract: Apparatus for frame synchronization in a broadcast receiver where received frames comprise first and second synchronization words at predetermined locations in the frame, comprises: a correlator set with expected synchronization words for correlation with incoming symbols of said frame, to find probable locations of the first and second synchronization words within the frame, and a thresholder for thresholding the correlation according to both the first and second thresholds, thereby to allow, the receiver to synchronize with the frame.

Abstract: In a radio transmission system, a receiver comprises means for synchronizing the time on the side of the receiver with the time on the side of the transmitter by a PLL circuit on the basis of receiving intervals of a packet transmitted for each predetermined time interval from a transmitter, means for holding the received packet in a receiving buffer, and means for outputting, when the time on the side of the receiver coincides with the time on the side of the transmitter which is represented by the transmitter-side time information added to the packet held in the receiving buffer, the packet to a decoding device.

Abstract: Disclosed is a method and an apparatus for generating a preamble sequence for an adaptive antenna system supporting a space division multiple access in an OFDMA communication system. Particularly, disclosed is a method for forming a preamble sequence identifying each of a plurality of mobile subscriber stations located within a cell or a sector of a communication system which includes a plurality of sub-channels assigned to the mobile subscriber stations, each of the sub-channels including a plurality of bins each of which includes n number of contiguous subcarriers in a frequency domain, the preamble sequence being transmitted before each of the sub-channels is transmitted, the method including the step of generating a preamble sequence by phase-shifting a predetermined sequence according to a predetermined phase shift sequence in the frequency domain.

Abstract: A method and apparatus are disclosed for detecting a synchronization mark in a received signal. The received signal is processed to compensate for a DC bias in the received signal, such as subtracting an average of a block of received samples from each sample in the block. A distance metric, such as a sum of square differences, is computed between the DC compensated received signal and an ideal version of the received signal expected when reading the synchronization mark. The synchronization mark is detected if the distance metric satisfies predefined criteria. The ideal version of the received signal can optionally be processed to compensate for a DC bias in the synchronization mark. A search for the synchronization mark search can be limited to time cycles that match a known phase.

Abstract: In case of disposing a pilot symbol in data transmission which depends on a DWMC transmission system, in a plurality of transmission symbols on a time axis, a pilot symbol, which becomes a signal of a sine wave, is configured, by giving contiguous identical data in a plurality of predetermined symbols. By transmitting a transmission signal with the use of this pilot signal, between a transmitting device and a receiving device, it is possible to carry out channel equalization by complex information which is obtained from a pilot symbol.

Abstract: A predetermined syncword detecting circuit includes a matched-bit-number comparing circuit, a comparing-result-change detecting circuit, a detected-result storing circuit, a total number detecting circuit, and a syncword detecting circuit. The matched-bit-number comparing circuit acquires and compares a number of bits in a baseband signal that matches bits of the predetermined syncword with a threshold. The comparing-result-change detecting circuit samples the comparison result, and detects changes in the comparison result. The detected-result storing circuit sequentially stores a result of the comparing-result-change detecting circuit. The total-number detecting circuit detects a total number of the result of the matched-bit-number comparing circuit. The result is included in an N cycle period and surpasses the threshold. The syncword detecting circuit detects the predetermined syncword and selects an intermediate phase of the cycles as a detection phase.

Abstract: Circuits, methods, and apparatus for transmitting, receiving, aligning and re-synchronizing high-speed single-ended signals by aligning a clock signal to one or more received data signals. A receiver amplifier circuit senses and captures low swing single ended signals at the receiver. Alignment is done on a per pin basis where a clock signal is distributed and independently phase shifted and aligned to each incoming data signal. In one example, a preamble containing a training data pattern is transmitted. The receiver steps through a number of dynamic timing alignment codes, each of which selects a different phase-shifted clock signal. The received data is examined for errors and the optimal clock signal is selected. Periodic dynamic readjustments of multiple clock alignment circuits may be made to compensate for temperature and voltage drift and variations.

Abstract: The invention relates to a method for transmitting at least one sequence of Np pulses over Np time windows, each pulse being enclosed within a predetermined time chip Tc. The method according to the invention includes a signal detection step, in the course of which Np detection windows Dj. (for j=1 to Np) encompassing predetermined time chips are examined by performing correlations over said detection windows Dj of the received signal with at least a first and a second sinusoidal signal S1 and S2. The method according to the invention enables to limit the processing time and power needed for carrying out the detection step, which only requires to examine detection windows defined by a signature of a transmitter by using sinusoidal signals, instead of mapping the whole pulse sequence by means of a correlation with expected pulses.

Abstract: In accordance with a method for identifying a preamble sequence and for estimating an integer carrier frequency offset, a signal that comprises a preamble sequence from a set of possible preamble sequences is received. A reduced set of integer carrier frequency offset (CFO) candidates may be determined. Cross-correlation operations may be performed with respect to the received signal and multiple candidate transmitted signals. Each candidate transmitted signal may include one of the set of possible preamble sequences. In addition, each candidate transmitted signal may correspond to one of the reduced set of integer CFO candidates. Multiple correlation values may be determined as a result of the cross-correlation operations. The correlation values may be used to identify the preamble sequence and to estimate the integer CFO.

Abstract: The present invention provides an audio data sync format detecting circuit that can minimize both the hardware configuration software processing, and furthermore, has a large flexibility with respect to unknown formats. Audio data is written in sequence into a data register, where the audio data are units having a predetermined number of bits. Samples of the format that is the object of detection are written in sequence into a register. A comparator compares the data in the sample register and the data in the data register. A control circuit receives hit signals and outputs an interrupt signal to the controller, and the controller writes in sequence samples of the format that is the object of detection into the register each time an interrupt signal is received. When hit signal is continuously output a predetermined number of times, a match detection circuit outputs a format match signal.

Abstract: A bit synchronization circuit comprising an initial phase determining unit for rapidly determining, during a period of receiving a preamble of burst data, a clock with a phase synchronized with received burst data from among multi-phase clocks having the same frequency as an internal reference clock and a phase tracking unit for modifying the synchronized phase clock responsive to phase variation of received data during a period of receiving a payload of burst data by taking the synchronized phase clock determined by the initial phase determining unit as an initial phase. The bit synchronization circuit retimes burst data with a data retiming clock having a predetermined phase relation with the synchronized phase clock and outputs the burst data in synchronization with the internal reference clock.

Abstract: A system for synchronizing a wireless receiver is provided. The system includes a first antenna (101a) and a second antenna (101b) to receive wireless signals containing data packets. The system includes one or more analyzer components (156) operable to determine correlation metrics based on at least a portion of the first received signal and a portion of the second received signal. The system further includes a synchronization component (158) operable to use the correlation metrics to determine a preferred correlation metric for synchronization by the wireless receiver of the first and second received signals to decode the data packet. A method for synchronizing a receiver of two wireless signals is also provided.

Abstract: Various embodiments are described to provide for the transmission and reception of data in an improved manner. Data transmission is improved by including in a transmitter a null generator (110) to generate an output data symbol sequence that exhibits nulls in the frequency domain at particular frequencies that an input data symbol sequence does not. A pilot inserter (120) then adds a pilot symbol sequence to this output data symbol sequence to create a combined symbol sequence. Since the pilot symbol sequence exhibits pilot signals corresponding to the nulls of the output data symbol sequence in the frequency domain, the combined symbol sequence exhibits pilots that are orthogonal to the data in the frequency domain.

Abstract: When data bursts are transmitted between a base station and a mobile receiver, a changeover is made between a plurality of modulation methods during an existing radio link for modulation of the data. For resynchronization of the receiver in the event of the changeover, synchronization information items are determined from a first part (ET) of the data burst modulated by a first modulation method, and are used for synchronization with a second part (ZT) of the data burst modulated by the second modulation method.

Abstract: A bit synchronization circuit comprising an initial phase determining unit for rapidly determining, during a period of receiving a preamble of burst data, a clock with a phase synchronized with received burst data from among multi-phase clocks having the same frequency as an internal reference clock and a phase tracking unit for modifying the synchronized phase clock responsive to phase variation of received data during a period of receiving a payload of burst data by taking the synchronized phase clock determined by the initial phase determining unit as an initial phase. The bit synchronization circuit retimes burst data with a data retiming clock having a predetermined phase relation with the synchronized phase clock and outputs the burst data in synchronization with the internal reference clock.

Abstract: A DSRC communication technology that prevents unique word detection errors even when the frame changes in data reception and the timing of the unique word detection window and the timing of the received data do not match, and that adjusts the data transmission timing in a flexible fashion when the slot timing deviates from the frame timing. In this technology, bit counter 111 generates the frame timing from the frame synchronization signal, and bit counter 112 generates the sot timing in response to the slot synchronization signal. The unique word detection window is generated from the frame timing and the received data operation timing and the data reception timing are generated from the slot timing. In addition, the data transmission timing and the transmission data operation timing are generated based on one of the frame timing and the slot timing chosen in selector 123.

Abstract: The present invention discloses a method for transmitting a synchronization signal in a mobile multimedia system. In the method, a transmitter of the system transmits a synchronization signal sequence at a regular interval. The methods includes: generating a first synchronization signal sequence; generating a second synchronization signal sequence by performing a reversible transform for the first synchronization signal sequence; and transmitting the first and the second synchronization signal sequences in cascade. By the method provided by the present invention for transmitting a synchronization signal in a mobile multimedia system, a channel with wider delay spread can be handled, more precise and stabler synchronization performance can be achieved and the channel estimation module can be helped to get more accurate channel frequency domain response.

Abstract: A Universal Mobile Telephone System (UMTS) receiver performs slot synchronization using a received primary synchronization channel (PSCH). Subsequent to completion of slot synchronization, the UMTS receiver performs frame synchronization using a received secondary synchronization channel (SSCH) in such a way that the UMTS receiver uses the received primary synchronization channel (PSCH) to detect a change in channel conditions.

Abstract: A system and method for detecting a synchronization (sync) signal in a communication signal are disclosed. A received communication signal is stored in a memory and portions thereof are read from the memory and monitored to detect the sync signal. When a detected sync signal is determined to be invalid, previously read portions of the received communication signal, preferably beginning at a portion of the received signal immediately after a start of the detected sync signal, are again read and monitored to detect the sync signal. Such reading and monitoring of previously read portions of a received signal provide for recovery from so-called false triggering based on invalid sync signals.

Abstract: A system and method of recovering symbol timing from a high symbol rate TDD or TDMA broadband transmission. A correlator operating at a fraction of the symbol rate receives in-phase and quadrature data signals from a broadband demodulator and processes those signals using a predefined match filter for a pilot signal to detect the pilot signal. The correlator measures any timing error in the symbol timing and adjusts a pointer in a memory buffer to replay the pilot signal to the correlator. Again, any timing error is determined and the pointer in the memory buffer is adjusted for a final replay of the pilot signal as well as the data to the correlator. At this point the timing error in the symbol timing is reduced to a minimum. With symbol timing established, coefficients in an equalizer are adjusted so that the remaining data transmission is properly received.

Abstract: For use in a CDMA receiver having a Viterbi decoder, a system for, and method of, performing one-pass blind transport format detection (BTFD) with respect to a received frame and a WCDMA receiver incorporating the system or the method. In one embodiment, the system includes: (1) a traceback circuit that performs a zero state BTFD traceback function with respect to at least a Viterbi-decoded portion of the frame, the traceback function being dependent upon a relative position of a BTFD checkpoint and generating hard decision bits and (2) a BTFD point selection circuit, coupled to the traceback circuit, that employs the hard decision bits to determine a location of a BTFD point with respect to the frame.

Abstract: A User Equipment (UE) receives and samples communication signals, where the communication signals have a time frame format, a transmission chip rate and a synchronization code associated with a time slot that includes a midamble that indicates a modulation of the synchronization code where a specified modulation of received synchronization codes identifies the timing for a timeslot in which data is to be received. The UE preferably includes a synchronization code determination circuit, a midamble determination circuit, and a phase modulation sequence detection circuit operatively associated with the midamble determination circuit. The UE can be configured for use with the low chip rate option of the Third Generation Partnership Project (3GPP) Universal Mobile Telecommunication System (UMTS) standards that employ a predefined set of downlink SYNC codes that point to midambles which indicate SYNC code modulation sequence to enables reading of data in a subsequent Broadcast Channel (BCH) message.

Abstract: A synchronization signal detector includes: a first circuit configured to delay the data signal by a period of at least one data segment of the data signal to generate a delayed signal; a second circuit configured to produce a plurality of similarity signals according to the data signal and the delayed signal, each of the similarity signals representing the similarity between the data signal and the delayed signal, and a third circuit configured to determine the synchronization signal of the data signal according to the similarity signals. The present invention further provides a method corresponding to the signal detector.

Abstract: A demultiplexer circuit includes a first serial-to-parallel conversion circuit for receiving input serial data and for performing serial-to-parallel conversion to output resultant data to parallel paths, a code detection circuit for activating and outputting a detection signal on detection of coincidence between output data sent out from the first serial-to-parallel conversion circuit to the parallel paths and a predetermined check code, a circuit for generating recovery clocks of a period corresponding to the length of a predetermined number of bits of the input serial data, and for varying the period of the recovery clocks, in case the detection signal from the code detection circuit is activated, in dependence upon bit deviation of the detection signal, to output resulting recovery clocks; and a second serial-to-parallel conversion circuit for converting data serially transmitted on the parallel paths into parallel data to output resulting parallel data responsive to the recovery clocks.

Abstract: This invention adds one extra bit which can be viewed as a shadow of most significant bit of the serial register. This extra register bit is referred as buffer_flop. When the receive data is coming in, the data bits keep shifting into the serial register of the serializer block bit by bit. The first bits enters into the most significant bit of the serial register and is shifted towards the least significant bit of the serial register. When a whole block of bits (32 bits) are received, the serializer is full and is read into the VBUS clock domain. The first bit of next block of bits is stored in the buffer flop. The second bit is stored in the most significant bit of the serializer and the buffer flop bit is copied into the second most significant bit of the serializer. Subsequent bits are received and right shifted by one.

Abstract: A technique for encoding digital communication signals. Data symbols are augmented in pilot symbols inserted at predetermined positions. The pilot augmented sequence is then fed to a deterministic error correction block encoder, such as a turbo product coder, to output a coded sequence. The symbols in the error correction encoded sequence are then rearranged to ensure that the output symbols derived from input pilot symbols are located at regular, predetermined positions. As a result, channel encoding schemes can more easily be used which benefits from power of two length block sizes.

Abstract: The invention provides a receiver that is capable of deducing the timing of a received signal having a frame structure and corresponding methods. Each frame contains a synchronization word. The receiver correlates the known synchronization word against the received signal to determine the position of the synchronization word. The correlation results can be accumulated over several frames' worth of the signal in order to enhance the determination. The frame boundaries within the signal can be translated and the process of determining the synchronization word position can then be repeated. In this manner, several results for the synchronization word position can be obtained and the best selected. A thresholding process can be used to curtail the number of frames' worth of the received signal that needs to be processed and a mechanism is provided to prevent the thresholding process from biasing the determination of the synchronization word position.

Abstract: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.

Abstract: A method and system for frame synchronization in a digital data transmission. A synchronization word is selected that is suitable for good correlation in a receiver detector. Either traffic bits or control bits are interleaved within the synchronization word in a predetermined pattern that is fixed for consecutive frames. The position of the sync word is varied from frame-to-frame. Also, the interleaved bits that are either traffic or control bits varies substantially between consecutive frames.

Abstract: A receiver comprising a processor having an input to receive a sequence of transmission frames conforming to a transmission protocol to represent payload data, a memory arranged to store and to provide to the processor a transmission protocol, a code provider arranged to provide to the processor one or more predetermined codes for association in a predetermined distributed manner within a group of transmission frames of a transmission sequence to represent one or more particular positions in the group of transmission frames, and wherein the processor is arranged to compile at least a portion of one or more distributed codes from a group of transmission frames of a transmission sequence received at the input using the predetermined distributed manner of the one or more predetermined codes received from the code provider, and to compare one or more compiled portions of one or more codes with the one or more predetermined codes received from the code provider to determine one or more particular positions in t

Abstract: A method for detecting a specific timing from a synchronization channel is described. A signal with a known sequence is received. Two or more correlation values between the received signal and the known sequence are calculated at two or more positions. The two or more correlation values are compared. A determination is made whether the position of the known sequence has been shifted based on the comparison. A specific timing of a synchronization channel is detected based on the determination.

Abstract: A receiving apparatus for receiving signals in a digital telecommunication system and a synchronizing method for synchronizing the receiving apparatus. The receiving apparatus includes a receiver for receiving a reference symbol having at least two repetition patterns. One of the, repetition patterns is phase-shifted in relation to the other. The receiving apparatus is synchronized in the digital telecommunication system using the received reference symbol. The synchronization includes a cross correlation of at least one of two repetition patterns within a cross correlation window having a predetermined length. In this manner, the performance and the accuracy of a cross correlation peak detection can be enhanced for improved synchronization.

Abstract: In the synchronous compensator, a load generator loads a bit counter with data in dependence upon whether or not a detection signal from a UW detector falls within the range indicated by an enable signal from a synchronous compensator circuit, thereby excluding the detection signal appearing far from the normal position to establish an appropriate synchronous compensation. The synchronous compensation is thus accomplished on the basis of normally received signal waves without picking up abnormal waves supposed as reflected waves.

Abstract: A DSRC communication and DSRC communication method for preventing UW detection errors as a result of shifts in timings of received data and a UW detection window. A configuration is adopted where a frame timing generating section that receives a UW detection window timing signal of a receiving slot of the head of a frame, synchronizes frames, and counts up a first synchronization bit counter to generate a frame timing, and a UW detection window timing generating section that generates a timing signal for a UW detection window of a receiving slot of the head of the next frame using the generated frame timing as a reference, are provided, and the frame timing is maintained by taking the UW detection timing at receiving slot 100 of the head of the frame as frame synchronization timing 106, and loading and counting up a value of frame synchronization bit counter within the receiving circuit at frame synchronization timing 106.

Abstract: A device that synchronizes circuits over asynchronous links is disclosed. Some embodiments of the invention include a device that comprises a plurality of circuits. One of the plurality of circuits is designated as a “master” circuit. The master circuit is configured to send a first synchronization signal to one or more of the plurality of circuits, and each circuit that receives the first synchronization signal is configured to responsively send a second synchronization signal to one or more of the plurality of circuits.

Abstract: Using a combination of auto-correlation and cross-correlation techniques provides a symbol timing recovery in a Wireless Local Area Network (WLAN) environment that is extremely robust to wireless channel impairments such as noise, multi-path and carrier frequency offset. An auto-correlator provides an estimate for a symbol boundary, and a cross-correlator is subsequently used to more precisely identify the symbol boundary. Peak processing of the cross-correlation results provides further refinement in symbol boundary detection. In receiving a packet conforming to the IEEE 802.11a standard, the method requires a minimum of only three short symbols of the 802.11a short preamble to determine timing, and guarantees timing lock within the duration of the 802.11a short preamble. This method and system can be easily applied to any other preamble based system such as 802.11g and High Performance Radio LAN/2 (HIPERLAN/2).

Abstract: A technique for synchronizing a device for communication is based on an accumulated sum of values or absolute values. The absolute value can be of either the sum or difference of a plurality of symbols. In one embodiment, the absolute values of the sum or difference of three symbol pairs are accumulated, and the accumulated total compared to a threshold value to determine whether the symbols are at the end of a predetermined sequence of symbols. When the comparison to the threshold value is positive, the three symbol pairs are the last six symbols in the predetermined sequence. In practice, the invention can be implemented in a number of different environments including, for example, in a WiMedia MBOA network environment. In the WiMedia MBOA environment, the predetermined sequence can comprise the preamble of a WiMedia MBOA packet.

Abstract: A permuted sequences combination uses a frame structure in which two sync words, each comprising M complex symbols, are appended at the frame start. One benefit is the reduction of the large variance of the timing estimation error in the conventional correlation method. In at least one embodiment, the first sync word, s1, is a predetermined constant amplitude zero autocorrelation (CAZAC) sequence. The second sync word, s2, is a permutation of the first such that the combination of the two received sync signal vectors perform sliding window processing where the peak occurs at the correct frame start. The permuted sequences combination can be used in both AWGN channel and multi-path environments.

Abstract: A method and apparatus for searching the synchronization signal of a next frame in encoded digital signal without the need of referring to a frame length indication signal. The encoded digital signal contains a plurality of frames, wherein each frame may have varying length and contain a synchronization signal. The method includes determining a search region, and locating the synchronization signal in the search region.