Abstract: Methods and systems are provided which utilize pilots in an information sequence to periodically retrain a channel estimator. Thus, a channel tracker may be synchronized using a synchronization sequence and then periodically retrained using known pilot symbols. Furthermore, the utilization of pilots may allow for the detection of errors in previous channel estimates. When errors are detected, a new channel estimate may be used based on the retraining using the pilot symbols and, optionally, previous errors in symbol estimation may be corrected. Thus, by retraining based on pilot symbols, the propagation of errors may be reduced.

Abstract: In order to provide a simple and reliable means of frame synchronisation in a serial data communication system, which avoids the problem of ‘bit-stuffing’ in known HDLC systems, the data communication system comprises a transmitter arranged to transmit data as a sequence of frames, each frame comprising a synchronisation section and a payload section of data, and the transmitter including in the synchronisation section of each frame a count value of a sequence of count values (a part of a predetermined code sequence), wherein successive frames contain successive count values (other parts of the predetermined code sequence). The receiver includes a FIFO buffer for storing three successively received frames, and a processor for assessing the stored data within the frames in order to locate and recognise the count values, whereby to synchronise to the received frames.

Abstract: A method and apparatus for determining synchronization and loss of synchronization in a high speed multiplexed data system. The system also includes a plurality of justification control bits and a backwards compatibility flag that allows the system to operate with older systems that have fewer justification control bits.

Abstract: A system includes a unique word correlator module which correlates a unique word field in a burst of a time division multiple access (TDMA) signal against a predefined marker sequence. Automatic timing control circuitry is coupled to the unique word correlator module. The automatic timing control circuitry derives a number of errors that are allowable during correlation of the unique word field.

Abstract: A method is provided for identifying a training baud in a digital audio broadcasting signal. The method includes the steps of receiving a plurality of carrier signals modulated by a plurality of data baud, wherein the data baud include normal baud and training baud. The data baud received on the carriers are compared with predetermined data signals to produce a plurality of difference signals. The difference signals are then used to produce a plurality of distance signals, which are combined to produce group distance signals. One of the group distance signals is selected and used to determine if the data baud corresponding to the selected group distance signal is a training baud or a normal baud. This determination is performed by storing successive selected group distance signals until at least one training baud has been received, and using the stored group distance signals to determine normal/training synchronization.

Abstract: A signal synchronism detecting circuit comprises a receiving circuit receiving a serial data including data bit groups each composed of a predetermined number of continuing bits and delimiter bit groups each composed of a predetermined number of continuing bits for delimiting the data bit groups from one another, a detecting circuit for obtaining an exclusive OR between continuing bits of the received serial data, so as to detect the delimiter bit group, and a serial-to-parallel converting circuit for serial-to-parallel converting the received serial data on the basis of the result of the detection of the delimiter bit group by the detecting circuit.

Abstract: There is disclosed a bit sync search and frame sync search system operative with a digital data signal as transmitted by a digital radio transmitter. The bit search is implemented by detecting a predetermined phasing signal which is incorporated in the digital signal and which has a repetitive bit pattern of ones and zeroes. The phasing signal is first detected by providing an in-phase and quadrature component signal and correlating those signals to provide an output signal indicative of the bit pattern in the phasing signal. After the phasing signal has been provided and an oscillator associated with a receiving apparatus is compensated according to the detected phasing signal, a tracking mode is entered, whereby a frame signal is captured and the system generates histograms of data bit transitions for producing an error signal indicative of the difference of the transmitted clock rate and the sampling portion of a received bit.

Abstract: A microcontroller includes a direct memory access unit that compresses and decompresses data and transfers from one block of memory to another. Specifically, word size data can be read, one byte discarded, and stored as consecutive, byte size data. This can be used in conjunction with an extended read and extended write asynchronous serial port that stores status information along with data. Once the status information is processed, the status is stripped by performing the “compressive” DMA.

Abstract: An apparatus for detecting a sync signal in a digital data record/replay device having a parallel clock generator, a parallel data generator, and a window unit comprises: a sync signal detector for comparing a pattern matching sync signal output from a sync pattern detector with an output signal of the window unit and detecting a sync signal according to clocks of the parallel clock generator; a latch unit for latching the sync signal detected by the sync signal detector and outputting the sync signal as a sync position signal according to clocks of the parallel clock generator; an identification error correction code (ID ECC) controller for generating an ID ECC control signal according to the sync position signal of the latch unit; an ID ECC decoder for decoding ID areas of parallel data generated by the parallel data generator; and a sync signal checking unit for outputting the sync position signal of the latch unit as a final sync signal and, when errors are detected as a result of the ID ECC decoding, sen

Abstract: Disclosed herein is a receiving circuit comprising demodulator 101 which pulls in the phase of each of burst signals respectively having preambles 701 and 711 each storing phase information or data therein, synchronous pattern parts 702 and 712 each storing synchronous information therein, and data parts 703 and 713 each storing the data therein, and outputs data obtained by demodulating the burst signal, a controller 110 which performs counting based on the demodulated data to output a timing signal, and a storage unit 102 which stores or outputs the demodulated data, based on the timing signal.

Abstract: A method and device for finding a reference pattern in a serial stream of digital data draws up comparison tables for the front and rear bits of the reference pattern. Using the comparison table for the front bits, bits which in terms of time are located upstream of a point P in the data stream are compared, and using the comparison table for the rear bits, bits which in terms of time are located downstream of point P in the data stream are compared. Next, the number of bits matching the reference pattern upstream and downstream of the point P are added up, and in case the sum total is greater than or equal to the number of bits in the reference pattern, there is a signal that the reference pattern has been found.

Abstract: A burst analyzer is useful in a digital communication system in which a signal burst has a plurality of reference segments distributed within the signal burst for transmission of a plurality of reference signals. The burst analyzer includes a filter that compares the received signal, for each reference segment thereof, with each reference signal offset by one of a plurality of time offsets to generate correlation data. The burst analyzer then determines, for each reference segment of the signal burst, a maximum correlation value from the correlation data for each time offset. Then the burst analyzer determines the time offset at which a sum of the maximum correlation values, over the plurality of reference segments, is a maximum. The burst analyzer jointly generates a frequency domain representation of the correlation data associated with the time offset at which the maximum correlation sum is a maximum, and then determines a frequency at which the frequency domain representation is a maximum.

Abstract: A discrete multitone modulation transmission system is described in which frame synchronization is monitored at the receiver by correlating frequency domain complex amplitudes of a synchronizing frame with a stored synchronizing pattern. If the correlation result falls below threshold, indicating a loss of frame synchronization, a plurality of correlations are performed, in each case using the stored complex amplitudes of the synchronizing frame multiplied by a respective complex value representing a respective complex derotation corresponding to a respective possible time shift of the synchronizing frame. The best correlation result, if it exceeds another threshold, indicates a time shift for restoring frame synchronization, this being possible before the next synchronizing frame is received.

Abstract: In accordance with this invention, a data capture circuit of a data receiver captures data from a data stream of a data transmitter operating at a different phase or frequency from the system clock of the data receiver. In one embodiment, the data receiver determines the number of clock periods of a clock signal in a data period of the data stream. Specifically, a signal detection circuit receives a signal having a periodic and distinctive feature. The period of the periodic and distinctive feature is related to the data period by a fixed scaling factor. A counter counts the number of clock periods of the clock signal between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit divides or multiples the content of the first counter by the scaling factor to determine the integer clock period count. The results of the multiply or divide is stored in a count register.

Abstract: Selector circuits are connected in a hierarchical arrangement. Each of the selector receives two of synchronizing pattern detection signals and two of synchronizing pattern position signals and selects one of the received synchronizing pattern position signals in accordance with values of the received synchronizing pattern detection signals, so that the position of a synchronizing pattern on parallel data can be identified in a tournament fashion.

Abstract: A synchronization detector has three registers to memorize individual patterns of three successive frames. A decoder produces a frame location signal on the basis of the individual patterns. A pointer circuit counts the number of the frame location signal to produce a pointer signal. The decoder produces a count-up signal when it can decode the individual patterns. The decoder produces a reset signal when it can not decode the individual patterns. A counter counts the count-up signal and is reset by the reset signal. A register holds a predetermined value. A comparator compares the count value of the counter with the predetermined value. The comparator produces a comparing order signal when the predetermined value is less than the count value. A comparing circuit compares the frame location signal with the pointer signal. If the frame location signal is not equal to the pointer signal, it happens that an optical head skips a few frames or slips to a next truck.

Abstract: A method of, and frame synchronizing device for, synchronizing systems having a digital interface. The systems are synchronized by extracting frame time information from a signal transferred from an external source through a digital interface, generating a frame reset signal, delayed by predetermined time based on the extracted frame time information, and resetting the entire systems based on the generated frame reset signal. Also, the color burst signal is free-oscillated during the digital interface mode in order to accommodate to the frame reset signal, which has a variable period.

Abstract: A modem system includes a programmable synchronization signal format that can be configured at a first modem in response to a request received from a second modem. The synchronization signal format may define a number of parameters of the synchronization signal, such as the sign pattern for symbols transmitted by the first modem during a training sequence. The specific parameters of the synchronization signal format may be associated with the design and operation of the second modem. For example, the particular timing recovery and automatic gain control schemes used by the receiver portion of the second modem may be optimally initialized with a synchronization signal having a specific length, amplitude, or spectrum. In one embodiment, a synchronization signal is configured to convey a single frequency tone for use during a synchronization routine. The modem system may also employ similar techniques to generate, transmit, and analyze a programmable line impairment learning signal.

Abstract: A synchronizing signal detecting circuit is disclosed. The sycnhronizing signal detecting circuit is characterized in that full matching or n mismatching is determined depending on a sub code area, a main data area, and the state of a system. Input data are compared with a predetermined synchronizing pattern and then a synchronizing signal is detected depending on the determined matching degree. As a result, since the synchronizing signal is detected, it is possible to minimize the missing synchronizing signal. The synchronizing signal detected in error is primarily removed using the window signal and the remaining synchronizing signal detected in error is finally removed by the error flag signal err_flag output as a result of ID ECC. Therefore, the actual synchronizing signal and the forcible synchronizing signal do not occur simultaneously, so that error detection of the synchronizing signal can be minimized.

Abstract: Coarse symbol synchronization is carried out during reception, for tuning, the signal being correlated in the time domain with various copies of itself which are shifted in time and correspond to the possible transmission modes. The present mode, the present guard interval and a sampling window are derived from this.

Abstract: A synchronization detection apparatus able to quickly detect synchronization words (synchronization patterns) arranged at predetermined bit intervals in a signal, provided with a synchronization word detector for identifying data having the same number of bits as the synchronization pattern in order while shifting positions of data in the signal in units of bits and comparing the identified data with a predetermined synchronization pattern stored beforehand; a consecutive synchronization word detection counter for establishing synchronization using the identified data as the synchronization pattern when all of the comparison results of a predetermined number of data identified and arranged consecutively at predetermined bit intervals are in agreement; a delay unit; and a synchronization processing state judging unit.

Abstract: There are received digital data serially transmitted in a predetermined format such as an SPDIF format. In the format, identification data are incorporated in the serial data in predetermined cycles. Generation of a train of bit-extracting pulses having a predetermined pulse generation pattern is triggered by detection of a pulse edge of the received serial data. By counting the bit-extracting pulses, bit location information is generated which identifies each bit location in the received serial data. Data of each bit is extracted from the received serial data using the bit-extracting pulse train, and each of the identification data is detected from the extracted data. Whenever such identification data is detected, a locked state is set at least on condition that the bit location information corresponds to a predetermined bit location, in response to which a lock status signal is generated.

Abstract: An invention for more accurately initiating the generation of detection windows for detecting data within a stream of data pulses is disclosed. A high frequency clock, typically operating at rate corresponding to a multiple of the nominal clock rate (e.g., two or three times, is used for a portion of a decoder system. In one embodiment, a down counter and a detection window generation component of the decoder system are clocked at the higher rate, while the remaining elements are clocked at the nominal clock rate. In this manner, the detection windows are more accurately initiated, while the remaining portions of the decoder system do not require the extra expense imposed of operating at the higher clock rate. Using the present invention, synchronization delay is minimized and detection windows are more accurately aligned with data pulses which reduces the error rate and improves performance of the decoder system.

Abstract: Packets in a bitstream are delineated by a) employing a first in, first out buffer (FIFO) with a storage capacity equal to the number of bits in a packet plus the number of bits in the synchronization pattern arranged so that comparison of its head end and tail end with the data pattern of the synchronization data pattern may be made, and b) declaring that a packet is detected when both the head end and the tail end of the FIFO each, substantially simultaneously, contains information equal to the synchronization pattern. Advantageously, the invention may be employed whether or not the bitstream is byte-aligned.

Abstract: A data sync signal detecting device with a simple configuration for detecting a sync signal with a few sync signal detection errors is disclosed. The detecting device is configured such that the output data of a most-likelihood decoder constituting a data discriminator is applied to a shift register bit cell and sequentially shifted and held in the bit cells of shift registers. The outputs of these bit cells are separated into an odd-numbered bit string and an even-numbered bit string and applied to first and second pattern matching circuits. The odd-numbered bit string is matched with “01001” as a predetermined sync signal pattern by a first pattern matching circuit which produces a first matching result. The even-numbered bit string is matched with “01011” as a predetermined sync signal pattern by a second pattern matching circuit which produces a second matching result. The first and second matching results are applied to a coincidence number adder/majority decision circuit.

Abstract: A synchronization equipment performs correlation processing between a first known pattern included in a received signal and a second known pattern, and detects reception timing of the received signal. A correlation value computing portion computes a correlation value between the first known pattern and the second known pattern at every reception time. A reception timing detection portion compares the computed related value with a predetermined threshold value, determines the reception time when the correlation value becomes larger than the threshold value to be the reception timing of a received signal, and, after this determination, suspends the comparison between the correlation value and the threshold value, and holds the reception time determined to be the reception timing.

Abstract: A GPS receiver having a fast time to lock to a GPS signal by storing a time period of an incoming GPS signal in a signal memory and rapidly comparing the signal memory against locations in a replica memory having stored GPS signal replicas. The GPS receiver includes a memory-based search engine for acquiring the GPS signal so that it may be tracked. The memory-based search engine includes a signal memory for storing a millisecond of a digitized GPS signal, a replica memory section for storing replicas representative of the digitized GPS signal for all possible frequency differences between the GPS carrier frequency and a local reference frequency and phase offsets between the GPS code phase and a local reference time, and a GPS memory comparator for comparing the stored signal in signal memory to the stored replicas in replica memory and issuing an acquisition detection signal when the level of the comparison is greater than a selected threshold.

Abstract: A road side communication equipment is provided crossing over lanes of an expressway, so that a communication processing for toll collection is executed between the road side equipment and an on-board equipment passing a communication area. The road side equipment sends signals using a 32-bit synchronizing signal for the start slot of each frame and a 16-bit synchronizing signal for subsequent slots of the frame. The on-board equipment receives this to perform signal receiving processing. The received communication signals are then digital-demodulated and entered to a shift register, so that the bit pattern is compared in two comparators to detect the synchronizing signal. According to the output from AND circuits, the synchronizing signal is distinguished from the synchronizing signal to determine the received data and receive subsequent data.

Abstract: When a sync pattern in a frame of a bit stream is detected to synchronize a data processing apparatus with the bit stream, data patterns containing a pattern identical to the sync pattern are often erroneously detected as the sync pattern. In order to overcome such problem, an apparatus for detecting data in a bit stream is provided. The bit stream contains a sequence of frames, and each frame has a predetermined number of bits and comprises a sync pattern and a data portion. The apparatus contains a detecting circuit, a counting circuit, and a synchronization signal generating circuit. The detecting circuit detects a first data pattern in the bit stream that equals the sync pattern and detects a second data pattern in the bit stream that equals the sync pattern. The counting circuit begins counting bits in the bit stream to generate a count value when the first data pattern is detected by the detection circuit.

Abstract: A frame synchronization detecting circuit is provided which is capable of efficiently reducing power consumption in a hunting state.

Abstract: A data sync signal detecting device with a simple configuration for detecting a sync signal having a few sync signal detection errors is disclosed. The detecting device is configured such that the output data of a most-likelihood decoder constituting a data discriminator is applied to a shift register bit cell and sequentially shifted and held in the bit cells of shift registers. The outputs of these bit cells are separated into an odd-numbered bit string and an even-numbered bit string and applied to first and second pattern matching circuits. The odd-numbered bit string is matched with “01001” as a predetermined sync signal pattern by a first pattern matching circuit which produces a first matching result. The even-numbered bit string is matched with “01011” as a predetermined sync signal pattern by a second pattern matching circuit which produces a second matching result. The first and second matching results are applied to a coincidence number adder/majority decision circuit.

Abstract: A method and apparatus for detecting framing alignment sequence within a received bit stream. A stream state memory is assigned for each possible location of the framing alignment sequence. Bits of a particular stream are loaded into the respective stream state memory. If the bits do not match an acceptable subsequence of the framing alignment sequence then the stream is eliminated from consideration by writing an exile state to the respective stream state memory. Then subsequently received bits are used to transition either to the next state if the next bit is a correct bit in the framing alignment sequence, or to the exile state if the bit is not the correct bit. After all of the streams have been exiled but one, the remaining stream may contain the framing alignment sequence. However, it may be that a certain number of correctly received bits are required to declare in-frame with sufficient certainty in which case incoming bits will continue to be processed until this is satisfied.

Abstract: A data transmission apparatus using a digital modulation system wherein a transmitting side inserts a group of predetermined synchronization symbols into a transmission signal at predetermined intervals to be transmitted. A receiving side calculates an electric power value of a received transmission signal. When a no-signal period (null section) in the synchronization symbol group is to be detected and decided from a magnitude of the received signal electric power value, a threshold for reference of decision for detecting the null section is calculated on the basis of an average electric power value for a predetermined period in the received signal electric power value and the threshold calculated in accordance with the received signal level of the transmission signal is used to detect synchronization stably.

Abstract: A method and system for updating clock references in a digital data stream is proposed, wherein all clock references present in the data stream are updated by means of a single system clock. A time recovery unit compares time tpcr transported in the clock reference (PCR) with the time of the system clock tclock and stamps the difference (tclock−tpcr) of the two times into the clock reference. After remultiplexing, a stamping unit reads out the time difference (tclock−tpcr) of the two times from the time stamp, subtracts it from the actual time in the system clock and stamps the value (tpcr+d) into the clock reference. Due to similarities in operation, the time recovery unit and stamping unit may share common circuitry.

Abstract: The present invention includes bit synchronizers and methods of synchronizing and calculating error. One method of synchronizing with a data signal in accordance with the present invention includes providing a data signal having a first portion and a second portion, generating a timing signal, first adjusting the timing signal during the first portion of the data signal, accumulating a history value during the first portion of the data signal, and second adjusting the timing signal during a second portion of the data signal using the history.

Abstract: A radio selective pager capable of preventing an erroneous synchronization with received signals of different transmission rates to avoid an erroneous switch operation from a power saving mode to a continuous receiving mode, improving power saving efficiency and prolonging life of an internal battery. A bit synchronizer synchronizes bits of demodulation data output from a receiver with an internal reference clock. A preamble detector detects a preamble of demodulation data output from the bit synchronizer, and a frame signal detector detects a frame synchronizing signal. When an address number of the demodulation data is coincident with an individual address number stored in an address comparator, a controller controls an indicator to indicate a selective paging to a user.

Abstract: A mobile wireless terminal comprises an RF receiving means for receiving a transmission radio wave received from a base station on a designated channel, a waveform equalizer for equalizing waveform distortion of a signal received by said RF receiving means, a unique word detector for detecting a unique word from a reception signal sequence whose waveform distortion has been equalized by said waveform equalizer, a channel switching controlling means for switching the current reception channel of said RF receiving means to another reception channel corresponding to a channel switch request, a carrier detector for detecting whether or not a transmission radio wave has been received by said RF receiving means and supplying a channel switch request to said channel switching controlling means when the transmission radio wave has not been received for a predetermined time period, and a sliding controlling means for performing an on/off control for the power of said waveform equalizer at predetermined intervals for a

Abstract: In a multi-value modulation system such as M bits/1 symbol, a pattern matching apparatus is arranged by a coincident bit number detecting circuit for detecting a coincident bit number between a reception symbol and the known pattern owned by a receiver within 1 symbol; a delay circuit for delaying a detection result; and an adder. Then, a coincident bit number between the received 1 symbol (M bits) and 1 symbol (M bits) of the known pattern is detected. This detected bit number is added to each other, so that when a length of a UW pattern is N bits, the total number of adders can be reduced to N/M.

Abstract: A method and system for receiving CIMT encoded data transmitted in simplex mode. The receiver (12) is adapted to receive a stream of digital data and analyze successive portions thereof to identify a predetermined pattern of data. The receiver (12) outputs the received digital data in response to a detection of the predetermined pattern of data and, in the alternative, outputs other data in response to a failure to detect the predetermined pattern of data. In the illustrative embodiment, the stream of digital data is transmitted as conditional invert master transition encoded simplex data. The receiver (12) includes a CIMT decoder (16) which analyzes the input data to identify a master transition therein. The receiver (12) uses a local clock to analyze successive portions of the received data stream and word alignment logic to identify a master transition therein.

Abstract: The back end position of a pulse, which is transmitted from a remote control, varies according to the transmission distance, and the pulse width changes. A remote control receiver of the present invention detects the pulse width of a header, which is formed at the head of each frame in a remote control signal from the remote control, so as to detect the transmission distance of the remote control signal and a change in back end position of each pulse in a data part, which is transmitted after the header. Then, the back end position of each pulse is corrected to original. This eliminates the change in pulse width resulting from a change in transmission distance, and increases the allowable range of the transmission distance of the remote control.

Abstract: Digital TV receiver including an antenna, a tuner for synchronizing one of a plurality of digital TV signals received at the antenna, the digital TV signal having data streams, and each data stream having a plurality of symbols, a comparing unit for comparing data streams of the synchronized digital TV signal to an already stored symbol pattern of a synchronizing signal in succession, to provide a positive number if found identical as a result of the comparison or either one of a negative value or a zero if found different as the result of the comparison, memories each having an identical initial value the memories corresponding to symbols in the data stream in one to one fashion, an adder for adding signals provided as many as a number of symbols in the data stream from the comparing unit in succession to corresponding initial values in the memories in succession when each of the data streams is received and keeping updating the initial values in the memories by storing the added signals to corresponding mem

Abstract: Disclosed is a peripheral device for reliably detecting synchronization patterns in CD-ROM media. The peripheral device has an internal circuitry for controlling and processing data that is read from a medium of the peripheral device is disclosed. The peripheral device comprises a digital signal processor, a decoder circuit, and a state machine. The digital signal processor is configured to receive the data that is being read from the medium of the peripheral device. The decoder circuit is coupled to the digital signal processor and forms a part of the internal circuitry. Further, the decoder circuit includes an internal RAM that is configured to store a sector of the data including a current sync pattern and a next sync pattern. The state machine resides in the decoder for analyzing the current sync pattern and the next sync pattern of the sector of the data. In the analysis mode, the state code is configured to determine whether a fatal error is present in the data.

Abstract: When an edge detecting unit detects a falling edge of a digital audio broadcasting (DAB) signal, a time instant of a timer, which has a periodic characteristic, is stored via a calculating unit into a memory. If there is one piece of data continued a number of times, when an output value of a timer becomes a value of this data offset by a frame time period, the calculating unit resets the timer. Subsequently, when the value of the timer becomes equal to the period length T, the calculating unit resets the timer and at the same time, outputs an L level to an output terminal only during a preselected time period after the timer is set to 0. Accordingly, even when another signal is mixed into a frame synchronizing signal of a DAB signal, the synchronizing signal timing is detected without increasing the time required to detect a frame header.

Abstract: In a communication system in which an asynchronous mode is employed as a media access control system, a synchronizing signal of digital data, which are sent out from a sender terminal apparatus and separated into the synchronizing signal and the bit stream data, is converted into block synchronizing signals which consist of a start signal indicating head position of bit stream data and an end signal indicating end position thereof, then the bit stream data and converted block synchronizing signals are converted into compressed block data by multiplexing them not to be overlapped on a time base respectively, and then the compressed block data are transmitted to a destination terminal apparatus via a data transmission line.

Abstract: A serial optical link for transmission of payload data is utilised so as to permit transmission of information facility data unrelated to the payload data. A superframe is constructed at the transmission facility made up of a serial series of data frames. Each data frame consists of serially arranged words including a number of payload data words and a non-payload word. One non-payload word of the superframe has information facility data which provides a communication channel from the transmitting facility to the receiving facility for information unrelated to the communication of payload data. Another non-payload word has alarm and status facility data. The information facility data is stored in a FIFO buffer when received. If the FIFO buffer is within two words of being full, a full signal is incorporated in the next alarm and status facility data word which causes the receiving end to suspend sending information facility data words.

Abstract: Repetitive packets in a voice/data stream, are detected and suppressed in the transmitting side of a network, after a predefined number of consecutive repetitive packets have been transmitted. Then, at the receiving side of the network, suppressed repetitive packets are reconstituted by filling the resulting gap in the voice/data stream with the repetitive pattern contained in the last received repetitive packet. When the input voice/data stream is compressed, only non-repetitive packets are compressed so that repetitive patterns are not corrupted by compression.

Abstract: A digital television (DTV) receiver receives a data signal that is divided into a plurality of segments each separated by a known data segment sync sequence. The receiver includes a data segment sync signal detector that receives the data signal and filters the signal to provide a filtered data signal. The detector computes the difference between samples of the filtered data signal and an average expected filtered signal value that is representative of a nominal filtered signal value in the middle of the segment sync sequence. The detector then computes the absolute value of the computed difference, and the resultant absolute value is summed with a sampled value from the previous segment and the summed value is stored into an accumulator. The process is repeated for several segments. The location of the data segment sync sequence within the segment is determined by comparing the summed values to determine the smallest summed value, which represents the center of the segment sync sequence.

Abstract: Method and device for detecting a synchronizing signal from a digital T.V. signal is disclosed. An initial value is stored as a maximum value in each of memories arranged to match to symbols consisting a datastream of the digital T.V. signal. A comparator has a symbol pattern stored therein in advance, which is identical to a symbol pattern of an actual synchronizing signal contained in the digital T.V. signal. Upon reception of the datastreams of the digital T.V. signal, the comparator compares the symbol pattern stored therein already to the symbols in the received datastream in sequence, to provide zero signals if identical and minus values if not identical. An adder adds a signal from the comparator and an initial value stored in a corresponding memory among the memories and stores in the corresponding memory, to update the initial value in each memory.

Abstract: A method and system for time aligning a frame (60) in a communication network (10) involves the steps of; i) determining if a frame needs to be advanced at a BTS (14), and ii) sending a shortened synchronization pattern from the BSC (12). The BTS (14) then determines if a short or long synchronization pattern has been sent by determining (256) if the received data stream matches a long synchronization pattern and setting a first flag when they do match. If the received data stream does not match the long synchronization pattern and the first flag is set (264), the data stream is compared (266) to the short synchronization pattern. When they match a second flag is set (268).

Abstract: A data sync signal detecting device with a simple configuration for detecting a sync signal having a few sync signal detection errors is disclosed. The detecting device is configured such that the output data of a most-likelihood decoder constituting a data discriminator is applied to a shift register bit cell and sequentially shifted and held in the bit cells of shift registers. The outputs of these bit cells are separated into an odd-numbered bit string and an even-numbered bit string and applied to first and second pattern matching circuits. The odd-numbered bit string is matched with "01001" as a predetermined sync signal pattern by a first pattern matching circuit which produces a first matching result. The even-numbered bit string is matched with "01011" as a predetermined sync signal pattern by a second pattern matching circuit which produces a second matching result. The first and second matching results are applied to a coincidence number adder/majority decision circuit.