Abstract: A method for determining a presence of a preamble for an orthogonal frequency division multiplexed (OFDM) complex valued sample stream may include capturing a portion of the OFDM complex valued stream and autoconvolving the portion of the OFDM complex valued sample stream to generate an autoconvolved portion. The method may further include determining a presence of a preamble in the OFDM complex valued sample stream if a peak is detected in the autoconvolved portion.

Abstract: Embodiments of the present invention include a method for performing joint time synchronization and carrier frequency offset estimation in a wireless communication system, comprising steps of: on a transmitter: performing frequency domain spreading and interleaving on input data by using a predetermined spreading factor (SF) to generate a frequency domain training symbol; performing Inverse Discrete Fourier Transformation (IDFT) on the generated frequency domain training symbol to generate a first time domain training symbol; reversely copying the generated first time domain training symbol to a second time domain training symbol such that a complete training sequence is formed; and on a receiver: detecting an average power of received signals to judge the coming of a training sequence, and performing coarse frame synchronization; performing joint fine frame synchronization and carrier frequency offset estimation based on a received training sequence; and compensating for the carrier frequency offset based on

Abstract: A method and apparatus are disclosed for detecting a synchronization mark in a received signal. The received signal is processed to compensate for a DC bias in the received signal, such as subtracting an average of a block of received samples from each sample in the block. A distance metric, such as a sum of square differences, is computed between the DC compensated received signal and an ideal version of the received signal expected when reading the synchronization mark. The synchronization mark is detected if the distance metric satisfies predefined criteria. The ideal version of the received signal can optionally be processed to compensate for a DC bias in the synchronization mark. A search for the synchronization mark search can be limited to time cycles that match a known phase.

Abstract: In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.

Abstract: This invention relates to signal processing in telecommunications, particularly but not exclusively for use in wireless TDMA systems. In particular, the invention concerns methods for use in communication systems making use of pilot symbols. The invention provides a method of placing pilot symbols in a data stream for telecommunication systems, wherein the pilot symbols are spaced in time using a range of different intervals between symbols. The intervals between the pilot symbols are substantially fractal in nature, the distribution of pilot symbols involving repetitions of irregular groupings of pilot symbols in the data stream. Preferably, the irregular groupings of pilot symbols are irregularly spaced in the data stream. The invention also provides a method and means for acquiring the time and frequency offset of a packet of data by using pilot symbols distributed within the packet as defined above.

Abstract: A method of acquiring a received spread spectrum signal, especially a GPS signal, is disclosed together with a spread spectrum signal receiver and a cellular telephone incorporating such a receiver. The method comprises the steps of: providing a replica signal containing a pseudorandom noise code, corresponding to that of the spread spectrum signal; providing a subject signal containing two fragments of the spread spectrum signal initially received during respective time periods between which a further time period elapses; and coherently correlating the replica signal with the subject signal over the two fragments.

Abstract: A method for transmitting data in the form of pulse sequences, including a signal synchronization step carried out by a receiver of dataframes DF, in the course of which at least one time window ?T(0) is scanned in search of the beginning PSB of a pulse sequence. The time window is then subdivided into a predefined number of sub-windows ?T(1). The sub-windows are then scanned during further signal detection steps until the beginning PSB of the pulse sequence has been detected within one of the sub-windows which will then be substituted for the previous time window AT(0), until the width of the resulting sub-windows becomes smaller than a predetermined minimum width.

Abstract: A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an integrated receiver module. The receiver module can take advantage of a known synchronization pattern such as the Bluetooth access code to determine an initial DC offset and to provide frame detection.

Abstract: In a frequency hopped wireless network, more robust method and system are disclosed for recovering clock synchronization. The method and system of the invention relies on the fact that correct decoding of a received packet occurs only when the same clock value is used to generate the decoding sequence at both the sender and the receiver. Several decoding sequences are tried based on different clock values to decode the packet. The different clock values used may be adjacent or nearby an initial estimated clock value. The clock value of the first decoding sequence to result in a correctly decoded packet is taken as the proper clock value for synchronization. Correct decoding is determined by checking the CRC of the packet.

Abstract: In carrying out a cell search, the received-signal level (RSSI) at each frequency is measured in the first place, by implementing asynchronous detection in steps of a predetermined frequency-step width over a predetermined search frequency range (from Fini to Fend), After measuring the RSSI, a cell search is carried out by implementing synchronous-detection processing over the frequency range that has a center frequency where the received-signal level is higher than a threshold value and that has the frequency-step width, it is an object of the present invention to obtain a communication terminal unit that can reduce a cell-search time.

Abstract: A harmonic detector including a pattern detector circuit responsive to a clock signal and a data signal configured to detect a target bit pattern from said data signal, and a time-out circuit responsive to said pattern detector circuit configured to detect the absence of said target bit pattern during a predetermined time-out parameter for indicating when said clock signal exceeds said data signal by a factor of two or more.

Abstract: The frame words of the embodiments are suitable for frame synchronization and/or channel estimation. By adding the autocorrelation and/or cross-correlation functions of frame words, double maximum values equal in magnitude and opposite polarity at zero and middle shifts are obtained. This property can be used to slot-by-slot, double-check frame synchronization timing, single frame synchronization and/or channel estimation and allows reduction of the synchronization search time. Further, the present invention allows a simpler construction of a correlator circuit for a receiver. A frame synchronization apparatus and method using an optimal pilot pattern is used in a wide band code division multiple Access (W- CDMA) next generation mobile communication system.

Abstract: Described is a system and method for providing a synchronization pattern in a communication system. The method includes generating a synchronization pattern with good randomness properties; packing a signal for transmission with m headers, each header consisting of the synchronization pattern 1/m symbol-time shifted from the previous header; and transmitting the signal. A further method provides for the sampling the transmitted signal with m headers of symbol-time shifted synchronization patterns; and determining symbol timing offset by computing and reordering correlation peaks from the synchronization patterns. A system includes a transmitting system, a receiving system, and a data channel. The transmitted signal includes m headers with 1/m symbol-time shifted synchronization patterns. The receiving system undersamples the transmitted signal with m synchronization patterns to simulate an oversampled synchronization pattern.

Abstract: A DSRC communication technology that prevents unique word detection errors even when the frame changes in data reception and the timing of the unique word detection window and the timing of the received data do not match, and that adjusts the data transmission timing in a flexible fashion when the slot timing deviates from the frame timing. In this technology, bit counter 111 generates the frame timing from the frame synchronization signal, and bit counter 112 generates the sot timing in response to the slot synchronization signal. The unique word detection window is generated from the frame timing and the received data operation timing and the data reception timing are generated from the slot timing. In addition, the data transmission timing and the transmission data operation timing are generated based on one of the frame timing and the slot timing chosen in selector 123.

Abstract: The present invention provides a serial data decoder without capacitor that can be made in the form of an integrated circuit without any additional external device. The integrated serial data decoder comprises a clock generator, a frame detector and a channel decoder. Demodulated serial data are inputted for being converted into parallel data periodically and repeatedly.

Abstract: A data detector detects an identification signal of a prescribed format from N-bit wide parallel input data (where N is a natural number). The data detector includes P first comparing sections (where P is a natural number), Q second comparing sections (where Q is a natural number), and a determining section. Each of the P first comparing sections compares one of first P data of continuous (P+Q) data in the parallel input data with a first pattern. Each of the Q second comparing sections compares one of Q data following the P data with a second pattern. The determining section determines whether the identification signal has been detected or not according to a comparison result of the P first comparing sections and a comparison result of the Q second comparing sections.

Abstract: A system and method for detecting a synchronization (sync) signal in a communication signal are disclosed. A received communication signal is stored in a memory and portions thereof are read from the memory and monitored to detect the sync signal. When a detected sync signal is determined to be invalid, previously read portions of the received communication signal, preferably beginning at a portion of the received signal immediately after a start of the detected sync signal, are again read and monitored to detect the sync signal. Such reading and monitoring of previously read portions of a received signal provide for recovery from so-called false triggering based on invalid sync signals.

Abstract: A synchronization signal detector includes: a first circuit configured to delay the data signal by a period of at least one data segment of the data signal to generate a delayed signal; a second circuit configured to produce a plurality of similarity signals according to the data signal and the delayed signal, each of the similarity signals representing the similarity between the data signal and the delayed signal, and a third circuit configured to determine the synchronization signal of the data signal according to the similarity signals. The present invention further provides a method corresponding to the signal detector.

Abstract: Described are a system, method and device to synchronize block data received in a data stream where the data stream is received on set data word increments. A synchronization header in each of a plurality of consecutive data word increments may be detected in a common location of a set portion or window of each consecutive fixed word increment. The data stream may be slipped by a fixed bit quantity in response to detecting an absence of the synchronization header in the common location of the set portion of a received data word increment.

Abstract: A cell searching apparatus and method in an asynchronous mobile communication system allocates an adjacent SCG to each base station according to adjacent degrees. When a mobile terminal is powered on, the mobile terminal receives PSCs and SSCs from the base stations. Multiple searching of SSCs is then performed based on each slot synchronization followed by a frame synchronization and SCG detection through the first searched SSC. If the detected SCG is not an SCG of a base station to which the mobile terminal belongs, the cell searching apparatus detects an SCG with a large size among the adjacent SCGs and detects an SC by using the greatest SCG. Frame synchronization and SCG detection are therefore quickly performed in a cell searching, resulting in a quick search searching.

Abstract: Method and apparatus for OFDM synchronization and channel estimation. In a temporal embodiment, received embedded system pilot symbols are inverse Fourier transformed at expected index locations and correlated with computed complex conjugates of inverse Fourier transforms of pilot symbols for providing a correlation function for the channel impulse response. In a frequency domain embodiment, embedded system pilot symbols are augmented with pilot-spaced inferred guard band symbols, multiplied by scaled complex conjugates of computed pilot systems, and inverse Fourier transformed into the channel impulse response. Time and frequency are synchronized in feedback loops from information in the channel impulse response. The channel impulse response is filtered, interpolated, and then Fourier transformed for determining channel estimates for equalization.

Abstract: This invention adds one extra bit which can be viewed as a shadow of most significant bit of the serial register. This extra register bit is referred as buffer_flop. When the receive data is coming in, the data bits keep shifting into the serial register of the serializer block bit by bit. The first bits enters into the most significant bit of the serial register and is shifted towards the least significant bit of the serial register. When a whole block of bits (32 bits) are received, the serializer is full and is read into the VBUS clock domain. The first bit of next block of bits is stored in the buffer flop. The second bit is stored in the most significant bit of the serializer and the buffer flop bit is copied into the second most significant bit of the serializer. Subsequent bits are received and right shifted by one.

Abstract: A transmitter comprising: a digital encoder for encoding incoming digital information; and a digital to analog converter for converting the encoded digital information into analog information is described. The transmitter further comprises an exact time framing block disposed between the digital encoder and the digital to analog converter. The exact time framing block receives the digitally encoded information and comprises a method for synchronization. The method including the steps of: providing a clock signal having at least two adjacent pulses; providing information subjected to transmission in the form of a set of frames; and accommodating a whole number of frames between the two adjacent pulses.

Abstract: A transmitting/receiving arrangement comprises a baseband module (1) and a radio-frequency module (3), which are connected to one another via a bidirectional data line (21) and a bit clock line (22) of a digital interface (2). In order to eliminate the influence of delay loops during the transmission of data in the opposite direction to the bit clock either the data bits are transmitted repeatedly or a bit clock frequency is set which is lower than the bit clock frequency for rectified transmission of bit clock signal and data signal.

Abstract: A receiver comprising a processor having an input to receive a sequence of transmission frames conforming to a transmission protocol to represent payload data, a memory arranged to store and to provide to the processor a transmission protocol, a code provider arranged to provide to the processor one or more predetermined codes for association in a predetermined distributed manner within a group of transmission frames of a transmission sequence to represent one or more particular positions in the group of transmission frames, and wherein the processor is arranged to compile at least a portion of one or more distributed codes from a group of transmission frames of a transmission sequence received at the input using the predetermined distributed manner of the one or more predetermined codes received from the code provider, and to compare one or more compiled portions of one or more codes with the one or more predetermined codes received from the code provider to determine one or more particular positions in t

Abstract: To obtain a frame synchronization device and a frame synchronization method capable of preventing a malfunction when a frame is synchronized by using a frame synchronization pattern varying sequentially. A bit serial signal at every frame is transmitted sequentially in a shift register composed of flip-flop circuits. When a bit in each of the stages is detected to be coincided with a corresponding bit in a frame synchronization pattern by coincidence circuits, existence of a synchronized frame is determined. Each bit in the synchronization pattern is also inputted into an all-zero detection circuit. If an all-zero state is detected, a first AND circuit does not output a synchronization pattern detecting signal even with a case where coincidence is detected from the coincidence circuits.

Abstract: A receiving apparatus for receiving signals in a digital telecommunication system and a synchronizing method for synchronizing the receiving apparatus. The receiving apparatus includes a receiver for receiving a reference symbol having at least two repetition patterns. One of the, repetition patterns is phase-shifted in relation to the other. The receiving apparatus is synchronized in the digital telecommunication system using the received reference symbol. The synchronization includes a cross correlation of at least one of two repetition patterns within a cross correlation window having a predetermined length. In this manner, the performance and the accuracy of a cross correlation peak detection can be enhanced for improved synchronization.

Abstract: A multiple frame rate synchronous detecting apparatus for synchronous-detecting received serial data having one frame rate among a plurality of predetermined frame rates is provided. The apparatus comprises a serial-to-parallel converter for serial-to-parallel converting the received serial data with matching with highest frame rate, a coincidence detector for comparing a portion of the converted parallel data corresponding to a predetermined region defined based on the frame rate, with a pattern for synchronous detection to detect coincidence, and a synchronous determiner for determining to have been synchronized with the frame rate when a periodic cycle of the coincidence detection is the same as a previous one.

Abstract: Using a combination of auto-correlation and cross-correlation techniques provides a symbol timing recovery in a Wireless Local Area Network (WLAN) environment that is extremely robust to wireless channel impairments such as noise, multi-path and carrier frequency offset. An auto-correlator provides an estimate for a symbol boundary, and a cross-correlator is subsequently used to more precisely identify the symbol boundary. Peak processing of the cross-correlation results provides further refinement in symbol boundary detection. In receiving a packet conforming to the IEEE 802.11a standard, the method requires a minimum of only three short symbols of the 802.11a short preamble to determine timing, and guarantees timing lock within the duration of the 802.11a short preamble. This method and system can be easily applied to any other preamble based system such as 802.11g and High Performance Radio LAN/2 (HIPERLAN/2).

Abstract: A WLAN device operating in an 802.11g mode can receive signals of different modulations. A technique is provided that quickly and accurately identifies signals of different modulation types when received by the WLAN device. This technique includes beginning demodulation of the received signal using components associated with potential types of modulation. One or more identification values can be provided to a voting block for potential types of modulation based on the received signal. The voting block can advantageously determine the most probable modulation based on such identification value(s). At this point, components associated with the determined modulation can be used to correctly decode the received signal and components not associated with the determined modulation can be deactivated, thereby saving valuable power resources in the device.

Abstract: A timing control circuit includes a synchronous detecting portion which detects a synchronous pattern data of a received signal which has been demodulated based on a first control signal and generates a detection result, a first counter portion which generates a first signal at each first cycle based on the detection result, a second counter portion which generates a second signal at each second cycle based on the detection result, and a first control portion which generates the first control signal based on the first and second signals.

Abstract: A method and apparatus for searching the synchronization signal of a next frame in encoded digital signal without the need of referring to a frame length indication signal. The encoded digital signal contains a plurality of frames, wherein each frame may have varying length and contain a synchronization signal. The method includes determining a search region, and locating the synchronization signal in the search region.

Abstract: Systems and methods are described for distribution of synchronization in a packet switched local area network environment. A method for extracting network synchronization timing from a data transmission burst includes: recovering a clock during the data transmission burst; and then holding over the clock after the data transmission burst ceases. A method for inserting network synchronization timing into a data transmission burst includes encoding data using a time-base reference signal governed clock.

Abstract: Input/output data transmission between a transmitting integrated circuit and a receiving integrated circuit requires a clock domain synchronizer to synchronize incoming data aligned to a clock signal of the transmitting integrated circuit to a clock signal of the receiving integrated circuit. During a start-up routine, the clock domain synchronizer propagates a pre-determined pattern of data bits through a first circuit path designed to reduce or eliminate metastability. During a normal operations mode, the clock domain synchronizer synchronizes the data signal to the clock signal of the receiving integrated circuit through a second circuit path.

Abstract: An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that includes one or more overhead fields (e.g., preamble and optional pilot blocks and one or multiple segments separated by pilot blocks). The module estimates carrier frequency and phase on a segment by segment basis and tracks frequency between segments. Carrier phase of the signal is estimated based upon the overhead field. Estimates carrier phase of random data field are determined based upon the estimated phase values from the overhead fields, and upon both the past and future data signals. Further, the frequency of the signal is estimated based upon the overhead fields and/or the random data field. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: A system, method and program are disclosed for achieving rapid bit synchronization in low power medical device systems. Messages are transmitted via telemetry between a medical device and a communication device. The synchronization scheme uses a portion of a unique preamble bit pattern to identify the communication device allowing for economical communications with a minimum expenditure of energy. A special set of preamble bit patterns are utilized for their unique synchronization properties making them particularly suited for rapid bit synchronization. These unique preamble bit patterns further provide simplification to the preamble error detection logic.

Abstract: Disclosed herein is a false lock detection circuit including: a data signal input section receiving an input of a data signal; a clock signal input section receiving an input of a clock signal generated from the data signal; a pattern detector obtaining the data signal on a basis of the clock signal, and detecting a data pattern in which adjacent pieces of data at at least three consecutive bits differ from each other; a phase period shift detector detecting a shift between periods of phases at a change point of the data signal and a change point of the clock signal; and a determining section determining whether a false lock has occurred on a basis of results of detection of the pattern detector and the phase period shift detector.

Abstract: The invention relates to power control of a cellular mobile communication system using TPC, and a power control circuit in a base station set and a radio terminal is equipped with a synchronism detecting unit for detecting synchronism data indicating synchronism establishment from radio data every frame; a synchronism/asynchronism judging unit for judging synchronism/asynchronism based on the synchronism data, an execution/unexecution judging unit for judging execution/unexecution of TPC based on the synchronism data, TPC bits extracting unit for detecting TPC bits contained in the radio data, and a selection control unit for selecting execution/unexecution of transmission power control using the TPC bits based on the judged result and the judged result. 3-Stage control of suspension, execution and unexecution of TPC becomes feasible every frame on the basis of quality, more stable quality can be secured, and increase in the quantity of channel interference can be prevented.

Abstract: A sync pattern detection apparatus includes a sync pattern detection unit configured to detect a sync pattern from an input signal, a plurality of sync pattern protection units configured to protect the sync pattern detected by the sync pattern detection unit, a reliability evaluation unit configured to evaluate the reliabilities of a plurality of sync pattern protection situations by the plurality of sync pattern protection units, and a selection unit configured to select a sync pattern protected by a predetermined sync pattern protection unit, on the basis of the reliability evaluation of the plurality of sync pattern protection situations by the reliability evaluation unit.

Abstract: A method for transmitting a digital data stream includes recovery of data clock information and data frame information from the digital data stream. The method includes providing a digital data stream having successive data stream units. Each data stream unit includes a data frame, a data block having data bits, and a frame synchronization word having frame synchronization bits. Successive frame synchronization words of the successive data stream units are then detected and data clock information is determined from a temporal spacing of the successive frame synchronization words. The data clock information is then output in a manner dependent on a temporal spacing of successive frame synchronization bits.

Abstract: A method and an apparatus for auto-tracking and compensating a clock frequency are disclosed. The method is suitable for being applied in USB controllers.

Abstract: In a DSRC communications controller equipped with a plurality of reception means for DSRC communications according to the invention, a reception reservation storage section 104 comprises means for detecting a communications frame start signal (unique word 1) of DSRC communications by using reception means not engaged in communications among the plurality of reception means and means for storing the control information of DSRC communications where the communications frame start signal is detected. On completion of DSRC communications by way of reception means, a controller uses the control information stored in the reception reservation storage section to establish next communications. This allows continuous reception of information from a plurality of roadside machines to be made efficiently even in case a plurality of communications areas overlap one another.

Abstract: In a data processor, a pickup head reads the data from a memory medium. Such data transferred in a plurality of parallel bits in synchronization with the clock signal to a controller unit from a read channel unit. The controller unit detects the predetermined mark for detecting synchronization included in the data in order to establish the synchronization of a series of data to be received from the read channel unit in order to demodulate the data other than the predetermined mark for detecting synchronization. The mark detecting unit in the controller unit detects the predetermined mark for detecting synchronization from the parallel data received with the shift register.

Abstract: Data communication system is provided that comprises a plurality of switches which each comprise a respective controller. Ports on the switch are connected to any one of a multiplicity of far-end devices. Physical media is used to connect each port to a far-end device. Various physical media may be routed through a common binder which can create electromagnetic interference problems. Each port controller is operable to calculate a unique preamble value to be assigned to each port within the switch. The unique preamble value is calculated using a linear feedback shift register function which can be implemented using convenient matrix multiplication operations on seed values stored within the port controllers.

Abstract: A method for processing an input burst signal comprising a first step for identifying an additive DC component and generating an output signal, which is representative for an estimated value of said DC component. The method further comprises a second step for detecting a predetermined signal portion from a plurality of possible signal portions included in the input burst signal and generating a control signal indicating the presence of the predetermined signal portion in the input burst signal. The method is characterized in that the first step and the second step are performed in parallel i.e. in a commonly defined time interval from a starting time of the burst.

Abstract: A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer.

Abstract: A data form converter allowing parallel-to-serial or serial-to-parallel conversion at various conversion ratios is disclosed. A frequency divider divides an input clock in frequency at a variable frequency division ratio to produce a single frequency-divided clock. A data shift circuit shifts serial input data according to the input clock to output n-bit parallel data, where n is determined depending on the variable frequency division ratio. A retiring section synchronizes the n-bit parallel data with the single frequency-divided clock to output parallel output data.

Abstract: The present invention provides an event edge synchronization system and a method of operating the same. In one embodiment, the event edge synchronization system includes: (1) a first clock zone device configured to generate an event signal based upon a first clock rate, (2) a second clock zone device configured to operate at a second clock rate, which is asynchronous with the first clock rate and (3) a synchronous notification subsystem configured to receive the event signal, synchronize the event signal to the second clock rate based upon an edge transition of the event signal and the second clock rate, and generate a synchronous notification signal therefrom.

Abstract: A synchronization detection circuit in which serial data received is collated to a predetermined matching pattern in a synchronization detection window to generate a detection level having a value corresponding to the degree of conformity to the matching pattern and in case a pattern is detected, whose detection level exceeds a preset threshold value, the pattern so detected is indicative of a synchronization signal. During the time before detection of the synchronization signal pattern, the maximum value of past detection level is retained. In case a pattern of the detection level of a value higher than the maximum value, as retained, is detected, the past detection level is updated and the detection of the pattern corresponding to the detection level of the higher value is considered to indicate detection of a provisional synchronization signal. Accordingly, a reset signal for re-synchronization of data take-in timing is output.

Abstract: An error protection method for multimedia improves data recovery and channel throughput in channels which cause a random error and a burst error by using a rate compatible punctured convolutional code (RCPC) and an automatic retransmission on request (ARQ). In a process of decoding a plurality of packets of given information, the error protection method includes the steps of a) decoding one of the plurality of packets, b) decoding another packet when an error occurs during the decoding in step a), c) decoding a combination of the packets from steps a) and b) or a third packet when an error occurs in step b), and d) repeating step c) until the decoding error no longer occurs. The error protection method has the characteristics of both Type-1 and Type-2 ARQ methods. Therefore, one can obtain constant channel throughput in a channel containing burst errors, a channel containing random errors, and a channel in which the two types of error patterns coexist simultaneously.