Abstract: A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.

Abstract: A method that includes determining a first clock gap for a first block of an integrated circuit based on a performance factor of the first block or an external factor and adjusting a clock signal to the first block based on the first clock gap. The method also includes determining a second clock gap for a second block of the integrated circuit based on (i) the first clock gap and (ii) a performance factor of the second block or the external factor. The second clock gap is different from the first clock gap. The method further includes adjusting the clock signal to the second block based on the second clock gap.

Abstract: A clock and data recovery circuit includes a phase interpolation circuit that adjusts a phase of a reference clock signal generated by a reference clock generation circuit to generate a reception clock signal, a filter that performs filter processing on a data signal output from an ADC that converts an analog data signal to a digital data signal in synchronization with the clock signal, a phase comparison circuit that outputs phase difference data between a transmission-side clock signal and the reference clock signal based on an output of the filter, and a loop filter that generates phase data to be set in the phase interpolation circuit. The filter includes an FIR filter with a tap number N, and an FIR filter with a tap number N+1 that outputs a signal delayed by half a clock than the former FIR filter.

Abstract: An audio decoder decodes a bit stream of encoded audio data, which bit stream represents a sequence of audio sample values and includes a plurality of frames, wherein each frame includes associated encoded audio sample values. The audio decoder includes a determiner configured to determine whether a frame of the encoded audio data is a special frame including encoded audio sample values associated with the special frame and additional information, wherein the additional information include encoded audio sample values of a number of frames preceding the special frame, wherein the encoded audio sample values of the preceding frames are encoded using the same codec configuration as the special frame, wherein the number of preceding frames is sufficient to initialize the decoder to be in a position to decode the audio sample values associated with the special frame if the special frame is the first frame upon start-up of the decoder.

Abstract: Embodiments of the present disclosure provide an apparatus including: a phase detector for detecting a write frequency of a deserializer and a read frequency of a serializer, such that the phase detector outputs a first code sequence in response to the write frequency being greater than the read frequency, or a second code sequence at the rotator input in response to the write frequency being less than the read frequency; and a phase rotator for receiving the first code sequence or the second code sequence from the phase rotator to transmit a pacing signal having the read frequency to the deserializer, wherein the pacing signal causes the read frequency to increase or decrease based on whether the read frequency is different from the write frequency.

Abstract: Methods, systems, and devices for clock locking for frame-based communications of memory devices are described. A memory system may include a memory device and a host device. The memory device may receive one or more frames of data from the host device, the one or more frames of data communicated by the host device using a first frame clock. The memory device may generate a second frame clock aligned with the one or more frames on receiving the one or more frames and align one or more operations of the memory device with the second frame clock. In some examples, the host device may receive a second set of frames from the memory device based on transmitting the first set of frames. The host device may align one or more operations of the host device with the second set of frames received from the memory device.

Abstract: An example method may include receiving, at a device, a first frame over a wireless network and constructing a preliminary data portion of a second frame. The second frame may be configured for transmission over the wireless network. The method may also include in response to the receiving of the first frame at the device, beginning transmission of a header portion of the second frame over the wireless network and after the beginning transmission of the header portion of the second frame, constructing, based on the preliminary data portion, a finalized data portion of the second frame for transmission over the wireless network.

Abstract: Aspects of the embodiments are directed to systems, methods, and devices that can activate forward error correction (FEC) based on the channel loss of a channel. The channel's loss can be characterized as a high loss channel if the channel loss exceeds a predetermined threshold value. For channels with high loss and for those that operate at high data rates (e.g., data rates commensurate with PCIe Gen 4 or Gen 5), FEC can be activated so that the channels can achieve higher data rates.

Abstract: Various embodiments of the present disclosure describe devices, systems, and processes for testing capacitors. For an embodiment, a system includes a digital signal processor configured to execute non-transient computer executable instructions for testing a device over at least three operating modes. The operating modes may include a start-up mode, during which the digital signal processor is configured to control initial charging of the device to a desired initial condition, a charge mode, during which the digital signal processor is configured to control replenishment of electrical energy in the device, and a test mode, during which the digital signal processor is configured to control testing of the device in accordance with at least one testing protocol. The device may include an energy capture circuit configured to capture recovered energy arising during a first test cycle and to provide the recovered energy to the device for use during a second test cycle.

Abstract: The disclosure relates to detecting phase slips that may occur in a multi-lane serial datalink. Phase slips may occur when a lane experiences lane skew, which may introduce a phase slip with respect to another lane. To detect phase slippage, the system may select a reference lane from among the lanes. The system may generate a pre-deskew delta value based on a difference between the FIFO filling level of the reference lane before a deskew and the FIFO filling level of a second lane before the deskew. The system may generate a post-deskew delta value based on a difference between the FIFO filling level of the reference lane after the deskew and the FIFO filling level of the second lane after the deskew. The system may use a difference between the post-deskew delta and the pre-deskew delta to detect phase slip on the second lane relative to the reference lane.

Abstract: Embodiments of systems and methods for clock synchronization for transmission of audio information are disclosed herein. In one example, a System on Chip (SoC) includes a Universal Serial Bus (USB) transceiver, an oscillator circuit free of a crystal, a frequency divider, and a clock synchronization calibrator. The USB transceiver is configured to extract a first synchronization clock associated with data received by the USB transceiver. The oscillator circuit free of a crystal is configured to generate an original clock. The frequency divider is configured to generate a second synchronization clock based on the original clock. The clock synchronization calibrator configured to generate a first set of frequency control data based on a frequency difference between the first synchronization clock and the second synchronization clock.

Abstract: A method, system, program control code, and hardware circuit are provided for predicting performance of an system-on-chip (SoC) (100) having a processor (105) and a master device (106) having shared access to a single-port memory (104) by activating a timer (102) in a Performance Monitoring Unit (PMU) (101) to measure a specified number of cycles of the processor in a defined measure instance and by activating a memory access counter (103) in the PMU to measure a first count of memory access requests to the single-port memory by the processor in the defined measure instance and to measure a second count of memory access requests to the single-port memory by the master device in the defined measure instance, so that the first and second counts are stored in memory.

Abstract: A test instrument tests an optical component of a fiber optic network. The test instrument determines signal parameters describing pulses to be emitted by lasers of the test instrument to test the optical component, and directly modulates the lasers to repeatedly emit the pulses at different wavelengths on a single fiber optic cable in a time division multiplexing manner. The test instrument triggers powering measurements to coincide with the emitted pulses, and determines performance parameters of the optical component based on the triggered power measurements.

Abstract: An audio decoder decodes a bit stream of encoded audio data, which bit stream represents a sequence of audio sample values and includes a plurality of frames, wherein each frame includes associated encoded audio sample values. The audio decoder includes a determiner configured to determine whether a frame of the encoded audio data is a special frame including encoded audio sample values associated with the special frame and additional information, wherein the additional information include encoded audio sample values of a number of frames preceding the special frame, wherein the encoded audio sample values of the preceding frames are encoded using the same codec configuration as the special frame, wherein the number of preceding frames is sufficient to initialize the decoder to be in a position to decode the audio sample values associated with the special frame if the special frame is the first frame upon start-up of the decoder.

Abstract: A communication interface includes one or more input/output circuitries, each input/output circuitry including a pointer generation block that controls write pointers of a respective input/output circuitry and read pointers of the respective input/output circuitry. Each input/output circuitry also includes input/output buffers communicatively coupled to the pointer generation block. Each input/output circuitry further includes a receive delay-locked loop that provides a clock signal to the plurality of input/output buffers. Each input/output circuitry also includes one or more transmit delay-locked loops that delay the clock signal.

Abstract: An image display device includes a communication device transmits a transmission request to each of the image transmission devices and receives a frame including differential data transmitted by each image transmission device in response to the transmission request. A measurement unit measures, for each image transmission device, a first required time interval, which is the time required from the start of transmission of the transmission request until the start of reception of the frame, and a second required time interval, which is the time required from the start of reception until the completion of reception of the frame. A control unit causes transmission requests to be sent to each of the image transmission devices at predetermined transmission intervals, causes measurement unit to measure the first and second required time intervals, and changes the transmission interval of the transmission request based on the measurement results.

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.

Abstract: A system substantially updates all the phase shifter values of a phased array antenna by using two “global writes” to update these parameters to all phased-array transformation circuits simultaneously via a serial bus. Antenna elements, each controlled by a phased-array transformation circuit, are individually configured to transform phase and gain according to a register array. The register array has a local register group and a central register group, the local registers physically placed close in proximity to RF chains which each correspond to an element of array antenna, whereby each set of local registers control an individual antenna element and a central register controlling overall beam steering function. Gain values are hierarchically distributed. The apparatus is configured to efficiently elaborate phase shift weights into a submodule of a phase array antenna system with low noise and bandwidth.

Abstract: An audio decoder decodes a bit stream of encoded audio data, which bit stream represents a sequence of audio sample values and includes a plurality of frames, wherein each frame includes associated encoded audio sample values. The audio decoder includes a determiner configured to determine whether a frame of the encoded audio data is a special frame including encoded audio sample values associated with the special frame and additional information, wherein the additional information include encoded audio sample values of a number of frames preceding the special frame, wherein the encoded audio sample values of the preceding frames are encoded using the same codec configuration as the special frame, wherein the number of preceding frames is sufficient to initialize the decoder to be in a position to decode the audio sample values associated with the special frame if the special frame is the first frame upon start-up of the decoder.

Abstract: A configurable multi-protocol transceiver implemented in an integrated circuit (“IC”) includes configurable deskew circuitry. The transceiver has various configurable deskew settings to facilitate effectively adapting transmit and/or receive communications corresponding to a selected one of a plurality of high-speed communication protocols and/or adapt to different implementations in which a deskew block addresses either just static skew or both static and dynamic skew. Configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. Configurable circuitry is adapted to control a deskew character transmit insertion frequency. A programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition.

Abstract: An audio decoder decodes a bit stream of encoded audio data, which bit stream represents a sequence of audio sample values and includes a plurality of frames, wherein each frame includes associated encoded audio sample values. The audio decoder includes a determiner configured to determine whether a frame of the encoded audio data is a special frame including encoded audio sample values associated with the special frame and additional information, wherein the additional information include encoded audio sample values of a number of frames preceding the special frame, wherein the encoded audio sample values of the preceding frames are encoded using the same codec configuration as the special frame, wherein the number of preceding frames is sufficient to initialize the decoder to be in a position to decode the audio sample values associated with the special frame if the special frame is the first frame upon start-up of the decoder.

Abstract: There is provided a frame converter that writes input data included in an input frame to a buffer to accumulate the input data and outputs data read from the buffer as output data included in an output frame, the frame converter includes a setting unit configured to set a time interval from start of resizing of data rate of the input data to start of resizing of data rate of the output data when resizing of an accumulation amount in the buffer is performed in which data rates of the input data and the output data vary, and an adjustment unit configured to adjust to approximate the data rate of the output data to the data rate of the input data after the time interval has elapsed since the start of resizing of data rate of the input data.

Abstract: Techniques and a network edge device are provided herein to extend local area networks (LANs) and storage area networks (SANs) beyond a data center while converging the associated local area network and storage area network host layers. A packet is received at a device in a network. It is determined if the packet is routed to a local or remote storage area network or local area network. In response to determining that the packet routed to a remote storage area network, storage area network extension services are performed with respect to the packet in order to extend the storage area network on behalf of a remote location. In response to determining that the packet is routed to a local local area network traffic, local area network extension services are performed with respect to the packet in order to extend the local area network on behalf of the remote location.

Abstract: A gearbox IC is incorporated into an optical communications system to enable an optical link that incorporates the system to achieve data rates that are at least double that which are currently achievable in optical links. The gearbox IC is compatible with ASIC designs currently used in optical fiber links. The gearbox IC enables the data rate of the optical fiber link to be dramatically increased without requiring a redesign of the ASIC that is currently used in the optical fiber link. The gearbox IC performs data rate conversion and phase alignment for bit streams being transferred via the gearbox IC between the ASIC and an optical transceiver module of the optical communications system.

Abstract: A method relates generally to a receiver. In such a method, a check of a clock and data recovery block of the receiver for a metastable state is performed. A phase input to a phase interpolator of the receiver is changed to cause the clock and data recovery block of the receiver to exit the metastable state within a time limit. To check for the metastable state, a phase difference in received data is determined, and the phase difference is determined to be less than a threshold for the clock and data recovery block being in the metastable state.

Abstract: A system for locking subrate clocks includes a module that the system phase-locks an incoming subrate clock from a Data Communication Equipment device. A Circuit Emulation Services over Packet transmission network is used to connect the Data Communications Equipment device to a Data Terminal Equipment device. Synchronization between end points is maintained by the system.

Abstract: A source-synchronous capture unit on a receiving circuit includes a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal to generate a synchronized write enable signal that is synchronized with a first free running clock associated with a memory external to the receiving circuit. The write enable sign is generated in response to a read operation by the receiving circuit. The source-synchronous capture unit also includes a second FIFO unit operable to store data from the memory in response to the first free running clock and the synchronized write enable signal, and to output the data in response to a second free running clock associated with the receiving circuit and a read enable signal.

Abstract: A method for generating a de-mapping clock for service data is provided, comprising: receiving a data frame and obtaining a payload value from the data frame; obtaining distribution of valid service data in a certain time cycle according to the payload value in the data frame; generating a data writing clock according to the distribution of the valid service data, performing a homogenization treatment on the data writing clock, and obtaining the data writing virtual clock; comparing a non-gap statistical quantity of the data writing virtual clock with a non-gap statistical quantity of the service clock gap, and generating a de-mapping clock gap according to the comparison result; generating a service clock gap according to the de-mapping clock gap; and performing a phase-locked loop process on the de-mapping clock gap, so as to obtain a recovery clock signal required by a de-mapping process.

Abstract: Systems and methods are provided that facilitate power management in a processing device. The system contains a power management component and a coupled to the processing device. The power management component determines and input rate and target voltages and/or frequency. The power management component can scale voltages and/or frequencies based on target voltages and/or frequencies. Accordingly, power consumption can be reduced and processing devices can be more efficient.

Abstract: An optical communications system and method at least doubles the data rate of the optical fiber link without requiring a redesign of the backplane ASIC. This is made possible in part through the incorporation of at least one gearbox integrated circuit (IC) is incorporated into the system that is compatible with the current ASIC design. The gearbox IC receives N lanes of electrical data signals from the ASIC, with each electrical data signal having a data rate of X Gbps, and outputs N/2 lanes of electrical data signals, with each electrical data signal having a data rate of 2X Gbps. The high-speed optical transceiver module receives the N/2 electrical data signals output from the gearbox IC and produces N/2 respective optical data signals having a data rate of 2X Gbps for transmission over the optical fiber link.

Abstract: An apparatus and a method for frequency locking are provided. The apparatus includes a phase-locked loop (PLL), a local clock generator, a data buffer unit and a control unit. The PLL locks the phase and the frequency of a radio frequency signal to generate a recovery clock signal and received data. The data buffer unit writes the received data into an elastic buffer of the data buffer unit according to the frequency of the recovery clock signal, and reads the received data from the elastic buffer according to the frequency of a local clock signal generated by the local clock generator. The control unit obtains a write-in address and a read-out address in the elastic buffer, and sends a control signal to the local clock generator for adjusting the frequency of the local clock signal according to relationship between the write-in address and the read-out address.

Abstract: In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming data in transit to the data sink. The electronic device also includes a clock drift compensation controller coupled to the buffer, wherein the clock drift compensation controller is configured to apply either of two predetermined clock drift compensation values to a clock rate for the buffer whenever a buffer fullness status value is offset from a predetermined threshold.

Abstract: A reception circuit that receives data in serial communications through a plurality of lanes includes a plurality of buffers provided for each of the plurality of lanes that each stores data received through corresponding lane, a multilane control circuit that detects the skew between the lanes, and outputs an adjustment instruction for adjusting a read address of a buffer and a deskew information indicating that a skew adjustment between which buffer the lanes is to be performed based on the detected skew, and a plurality of address control circuits provided for each of the plurality of lanes that each transmits the adjustment instruction to a corresponding buffer when receiving the deskew information, wherein the buffer that has received the adjustment instruction adjusting its read address.

Abstract: Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

Abstract: A decoder includes a buffer configured to incrementally transport a synchronous data stream through a path of the decoder. A control circuit is configured to control a depth parameter associated with the buffer and to provide a substantially predictable delay of the synchronous data stream through the path of the decoder.

Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.

Abstract: In a clock-adjustment circuit, a phase-detection circuit receives a first clock associated with a first clock domain and a second clock associated with a second clock domain, and determines a phase relationship between the first clock and the second clock. Then, the phase-adjustment circuit in the clock-adjustment circuit adjusts a phase of the first clock relative to the second clock if the determined phase relationship is associated with a metastable range of a first-in first-out (FIFO) buffer that transfers data from the first clock domain to the second clock domain, thereby reducing latency associated with the FIFO buffer.

Abstract: A one-wire communication bus for transferring a sequence of digital data from a transmitter to a receiver includes (a) an ECDD signal modulation circuit to create an electrical pulse train wherein each pulse's edge is used as clock signal and each pulse's duty cycle is used to represent digital value of zero and one; (b) an ECDD signal demodulation circuit to receive the ECDD pulse train using a group of sampling cells and to decode the sampled results using a majority voting circuit; (c) an electrical connection between a transmitter wherein the ECDD signal modulation circuit resides and a receiver wherein the ECDD signal demodulation circuit resides. Said ECDD signal is sent from the transmitter to the receiver through the electrical connection. Methods of creating the ECDD pulse train in the transmitter and decoding the ECDD pulse train in the receiver are also disclosed.

Abstract: A method and apparatus for processing input data signals transmitted in a continuous mode, or in a burst mode, of signal transmission, such as in a satellite or a computer network communications system. A receiver receives input data signals and a buffer stores the received input data. Processing circuitry generates frame timing synchronization control signals for writing the frames of the input data for storage, generates timing error control signals corresponding to a processing delay for the input data, for synchronizing reading out the stored data from the buffer based on a timing difference between the timing error control signals and the frame timing synchronization control signals to adjust for an arbitrary delay in processing the input data. The processing circuitry can include a tap gradient update circuit for generating a tap gradient corresponding to the read out data, based on equalizer error signals generated by the processing circuitry.

Abstract: An overhead processor for data transmission in digital communications is disclosed. Incoming data is transmitted along a datapath. If there are two or more groups of incoming data, arriving separately, the initial group(s) of received data can be held in an elastic store until the arrival of additional group(s) of data, and upon the arrival of additional group(s) of data, all received data are combined and transmitted into flip-flop(s). The data is transmitted from said flip-flop(s) to a logic element to determine the new data context of imminent incoming data prior to any additional incoming bytes arriving along the datapath. Therefore, the number of overhead processors required for multi-byte data transmission is reduced, potentially reducing the number of required overhead processors in digital communications to 1.

Abstract: Instant discloser is a method to transmit multiple data-streams of varying capacity data using Virtual Concatenation (VCAT) over Synchronous Digital Hierarchy (SDH) network, comprising acts of determining number of data bytes to be requested for each Virtual Concatenation Group (VCG) in a row-time of the aggregated bandwidth and storing it in a VCG request configuration memory, reading the requested number of data bytes from each data-stream in order in to a Row Buffer for each row time of an SDH frame, reading data stored in the Row Buffer from memory address determined by one or more connection memory wherein the connection memory is programmed to carry out sequencing of bytes of the Row Buffer based on the VCAT numbering, and inserting path overhead (POH) and pointer information in to the read data streams in previous step to transmit multiple data-streams of varying capacity data using VCAT over SDH network.

Abstract: A mechanism for dynamic skew correction in a multi-lane communication link includes a receiver unit including, for each of the lanes, a first-in first-out (FIFO). The FIFO may store received symbols to locations pointed to by a write pointer and output to downstream logic, symbols stored at locations pointed to by a read pointer. The receiver may also include a symbol drop unit that disables the write pointer in response to receiving a start alignment symbol, and enables the write pointer in response to receiving an end alignment symbol. The receiver also includes an alignment unit that disables the read pointer in response to detecting that the end symbol has been received at least one lane but not all lanes. In addition, the alignment unit may enable the read pointer in response to a determination that the end symbol has been received on all lanes.

Abstract: A method for operating an automation system with a plurality of communication users linked for communication purposes via a serial connection, of which at least one functions as sender and at least one as a receiver, includes determining at a sender an offset value between an occurrence of a synchronous signal and a communication clock cycle, transmitting the determined offset value in a data transmission to the at least one receiver, waiting at the at least one receiver until a time period commensurate with the offset value has elapsed, and generating at the at least one receiver an output signal after the time period has elapsed.

Abstract: A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. The CDR circuit further includes a delay locked loop (DLL) configured to receive the clock signal from the LCVCO and generate multiple clock phases and a first charge pump configured to control the LCVCO. The CDR circuit further includes a phase detector configured to receive a data input and the multiple clock phases from the DLL, and to align a data edge of the data input and the multiple clock phases.

Abstract: A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer at the first rate, and read from the first and second buffer, at the second rate. Underflow of the first buffer is signaled to the second buffer, thereby avoiding the need to insert defined clock compensation symbols at the second rate. Symbols received at the second buffer while underflow is signaled may be ignored. Conveniently, the second buffer may also be used to align symbol data across multiple symbol streams using periodic alignment symbols. An exemplary embodiment conforms to the PCI Express standard.

Abstract: Methods and apparatus are provided for determining one or more channel compensation parameters based on data eye monitoring. According to one aspect of the invention, a method is provided for evaluating the quality of a data eye associated with a signal. The received signal is sampled for a plurality of different phases, for example, using at least two latches, and the samples are evaluated to identify when the signal crosses a predefined amplitude value, such as a zero crossing. It is determined whether the points of predefined amplitude crossing satisfy one or more predefined criteria. One or more parameters of one or more channel compensation techniques can optionally be adjusted based on a result of the determining step. One or more parameters of an adjacent transmitter can also be adjusted to reduce near end cross talk based on a result of the determining step.

Abstract: A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an asynchronous gapped clock derived from a first clock having a first frequency. The gapped clock has an average second frequency less than the first frequency. The input serial stream of data is loaded at a rate responsive to the gapped clock. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock, averaged, and an averaged numerator (A and an averaged denominator (AD) are generated. The first frequency is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency. The FIFO memory accepts the jitter-attenuated second clock and supplies data from memory at the second frequency. A framer accepts the data from the FIFO memory and the jitter-attenuated second clock.

Abstract: An output signal adjustment system includes a signal adjustment unit, a reference slope generating unit, a slope detecting unit, a voltage-to-current conversion unit, and a control unit. The slope detecting unit compares the slope of the rising and falling edges of the output signal of the reference slope generating unit with that of the signal adjustment unit and outputs a voltage signal. The voltage-to-current conversion unit converts the voltage signal into a current signal. Based on the current signal, the control unit outputs a control signal for controlling the adjustment of the signal adjustment unit to the slope of the rising and falling edges of the output signal. The output signal adjustment system can automatically adjust the slope of the rising and falling edges of the output signal, so that the output signal is insensitive to the packaging, the printed circuit board, the transmission line and other sender loads.

Abstract: A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller.

Abstract: An apparatus and method of generating a pseudo noise (PN) code is provided. The apparatus for generating the PN code includes: a memory device unit including a plurality of memory devices; an exclusive-OR (XOR) operation unit receiving output values of at least two memory devices among output values of the plurality of memory devices to output an XOR operation value with respect to the received output values; and a PN code generation unit generating the PN code based on an output value of the XOR operation unit.