Elastic Buffer Patents (Class 375/372)
  • Patent number: 10412341
    Abstract: An image display device includes a communication device transmits a transmission request to each of the image transmission devices and receives a frame including differential data transmitted by each image transmission device in response to the transmission request. A measurement unit measures, for each image transmission device, a first required time interval, which is the time required from the start of transmission of the transmission request until the start of reception of the frame, and a second required time interval, which is the time required from the start of reception until the completion of reception of the frame. A control unit causes transmission requests to be sent to each of the image transmission devices at predetermined transmission intervals, causes measurement unit to measure the first and second required time intervals, and changes the transmission interval of the transmission request based on the measurement results.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: September 10, 2019
    Assignee: NEC DISPLAY SOLUTIONS, LTD.
    Inventor: Eisaku Ishii
  • Patent number: 10310585
    Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: June 4, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shaul Yohai Yifrach, Amit Gil, James Lionel Panian, Ofer Rosenberg, Richard Dominic Wietfeldt
  • Patent number: 10270507
    Abstract: A system substantially updates all the phase shifter values of a phased array antenna by using two “global writes” to update these parameters to all phased-array transformation circuits simultaneously via a serial bus. Antenna elements, each controlled by a phased-array transformation circuit, are individually configured to transform phase and gain according to a register array. The register array has a local register group and a central register group, the local registers physically placed close in proximity to RF chains which each correspond to an element of array antenna, whereby each set of local registers control an individual antenna element and a central register controlling overall beam steering function. Gain values are hierarchically distributed. The apparatus is configured to efficiently elaborate phase shift weights into a submodule of a phase array antenna system with low noise and bandwidth.
    Type: Grant
    Filed: July 23, 2016
    Date of Patent: April 23, 2019
    Assignee: TUBIS TECHNOLOGY INC
    Inventors: James Wang, Chak Chie
  • Patent number: 10229694
    Abstract: An audio decoder decodes a bit stream of encoded audio data, which bit stream represents a sequence of audio sample values and includes a plurality of frames, wherein each frame includes associated encoded audio sample values. The audio decoder includes a determiner configured to determine whether a frame of the encoded audio data is a special frame including encoded audio sample values associated with the special frame and additional information, wherein the additional information include encoded audio sample values of a number of frames preceding the special frame, wherein the encoded audio sample values of the preceding frames are encoded using the same codec configuration as the special frame, wherein the number of preceding frames is sufficient to initialize the decoder to be in a position to decode the audio sample values associated with the special frame if the special frame is the first frame upon start-up of the decoder.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: March 12, 2019
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Daniel Fischer, Bernd Czelhan, Max Neuendorf, Nikolaus Rettelbach, Ingo Hofmann, Harald Fuchs, Stefan Doehla, Nikolaus Faerber
  • Patent number: 10216219
    Abstract: A configurable multi-protocol transceiver implemented in an integrated circuit (“IC”) includes configurable deskew circuitry. The transceiver has various configurable deskew settings to facilitate effectively adapting transmit and/or receive communications corresponding to a selected one of a plurality of high-speed communication protocols and/or adapt to different implementations in which a deskew block addresses either just static skew or both static and dynamic skew. Configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. Configurable circuitry is adapted to control a deskew character transmit insertion frequency. A programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: February 26, 2019
    Assignee: Altera Corporation
    Inventors: Divya Vijayaraghavan, Curt Wortman, Chong H. Lee, Vinson Chan
  • Patent number: 9928845
    Abstract: An audio decoder decodes a bit stream of encoded audio data, which bit stream represents a sequence of audio sample values and includes a plurality of frames, wherein each frame includes associated encoded audio sample values. The audio decoder includes a determiner configured to determine whether a frame of the encoded audio data is a special frame including encoded audio sample values associated with the special frame and additional information, wherein the additional information include encoded audio sample values of a number of frames preceding the special frame, wherein the encoded audio sample values of the preceding frames are encoded using the same codec configuration as the special frame, wherein the number of preceding frames is sufficient to initialize the decoder to be in a position to decode the audio sample values associated with the special frame if the special frame is the first frame upon start-up of the decoder.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: March 27, 2018
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Daniel Fischer, Bernd Czelhan, Max Neuendorf, Nikolaus Rettelbach, Ingo Hofmann, Harald Fuchs, Stefan Doehla, Nikolaus Faerber
  • Patent number: 9762986
    Abstract: There is provided a frame converter that writes input data included in an input frame to a buffer to accumulate the input data and outputs data read from the buffer as output data included in an output frame, the frame converter includes a setting unit configured to set a time interval from start of resizing of data rate of the input data to start of resizing of data rate of the output data when resizing of an accumulation amount in the buffer is performed in which data rates of the input data and the output data vary, and an adjustment unit configured to adjust to approximate the data rate of the output data to the data rate of the input data after the time interval has elapsed since the start of resizing of data rate of the input data.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: September 12, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Makoto Shimizu, Shota Shinohara
  • Patent number: 9379906
    Abstract: Techniques and a network edge device are provided herein to extend local area networks (LANs) and storage area networks (SANs) beyond a data center while converging the associated local area network and storage area network host layers. A packet is received at a device in a network. It is determined if the packet is routed to a local or remote storage area network or local area network. In response to determining that the packet routed to a remote storage area network, storage area network extension services are performed with respect to the packet in order to extend the storage area network on behalf of a remote location. In response to determining that the packet is routed to a local local area network traffic, local area network extension services are performed with respect to the packet in order to extend the local area network on behalf of the remote location.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: June 28, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Samar Sharma, Chandramouli Radhakrishnan, Sameer Merchant, Anand Parthasarathy, Murali Basavaiah
  • Patent number: 9236946
    Abstract: A gearbox IC is incorporated into an optical communications system to enable an optical link that incorporates the system to achieve data rates that are at least double that which are currently achievable in optical links. The gearbox IC is compatible with ASIC designs currently used in optical fiber links. The gearbox IC enables the data rate of the optical fiber link to be dramatically increased without requiring a redesign of the ASIC that is currently used in the optical fiber link. The gearbox IC performs data rate conversion and phase alignment for bit streams being transferred via the gearbox IC between the ASIC and an optical transceiver module of the optical communications system.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: January 12, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Faouzi Chaahoub, Georgios Asmanis
  • Patent number: 9209960
    Abstract: A method relates generally to a receiver. In such a method, a check of a clock and data recovery block of the receiver for a metastable state is performed. A phase input to a phase interpolator of the receiver is changed to cause the clock and data recovery block of the receiver to exit the metastable state within a time limit. To check for the metastable state, a phase difference in received data is determined, and the phase difference is determined to be less than a threshold for the clock and data recovery block being in the metastable state.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: December 8, 2015
    Assignee: XILINX, INC.
    Inventors: Caleb S. Leung, Alan C. Wong, Christopher J. Borrelli, Yu Xu, Yohan Frans, Kun-Yung Chang
  • Patent number: 9209964
    Abstract: A system for locking subrate clocks includes a module that the system phase-locks an incoming subrate clock from a Data Communication Equipment device. A Circuit Emulation Services over Packet transmission network is used to connect the Data Communications Equipment device to a Data Terminal Equipment device. Synchronization between end points is maintained by the system.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: December 8, 2015
    Assignee: Cornet Technology, Inc.
    Inventor: James Crews
  • Patent number: 9201449
    Abstract: A source-synchronous capture unit on a receiving circuit includes a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal to generate a synchronized write enable signal that is synchronized with a first free running clock associated with a memory external to the receiving circuit. The write enable sign is generated in response to a read operation by the receiving circuit. The source-synchronous capture unit also includes a second FIFO unit operable to store data from the memory in response to the first free running clock and the synchronized write enable signal, and to output the data in response to a second free running clock associated with the receiving circuit and a read enable signal.
    Type: Grant
    Filed: April 19, 2014
    Date of Patent: December 1, 2015
    Assignee: Altera Corporation
    Inventor: Ryan Fung
  • Patent number: 9178638
    Abstract: A method for generating a de-mapping clock for service data is provided, comprising: receiving a data frame and obtaining a payload value from the data frame; obtaining distribution of valid service data in a certain time cycle according to the payload value in the data frame; generating a data writing clock according to the distribution of the valid service data, performing a homogenization treatment on the data writing clock, and obtaining the data writing virtual clock; comparing a non-gap statistical quantity of the data writing virtual clock with a non-gap statistical quantity of the service clock gap, and generating a de-mapping clock gap according to the comparison result; generating a service clock gap according to the de-mapping clock gap; and performing a phase-locked loop process on the de-mapping clock gap, so as to obtain a recovery clock signal required by a de-mapping process.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: November 3, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Hui Yin
  • Patent number: 9170642
    Abstract: Systems and methods are provided that facilitate power management in a processing device. The system contains a power management component and a coupled to the processing device. The power management component determines and input rate and target voltages and/or frequency. The power management component can scale voltages and/or frequencies based on target voltages and/or frequencies. Accordingly, power consumption can be reduced and processing devices can be more efficient.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: October 27, 2015
    Assignee: Applied Micro Circuits Corporation
    Inventors: Kjeld P. Svendsen, Arun Jangity
  • Patent number: 9048958
    Abstract: An optical communications system and method at least doubles the data rate of the optical fiber link without requiring a redesign of the backplane ASIC. This is made possible in part through the incorporation of at least one gearbox integrated circuit (IC) is incorporated into the system that is compatible with the current ASIC design. The gearbox IC receives N lanes of electrical data signals from the ASIC, with each electrical data signal having a data rate of X Gbps, and outputs N/2 lanes of electrical data signals, with each electrical data signal having a data rate of 2X Gbps. The high-speed optical transceiver module receives the N/2 electrical data signals output from the gearbox IC and produces N/2 respective optical data signals having a data rate of 2X Gbps for transmission over the optical fiber link.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: June 2, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Faouzi Chaahoub, Georgios Asmanis, Samir Aboulhouda, Michael A. Robinson
  • Publication number: 20150131766
    Abstract: An apparatus and a method for frequency locking are provided. The apparatus includes a phase-locked loop (PLL), a local clock generator, a data buffer unit and a control unit. The PLL locks the phase and the frequency of a radio frequency signal to generate a recovery clock signal and received data. The data buffer unit writes the received data into an elastic buffer of the data buffer unit according to the frequency of the recovery clock signal, and reads the received data from the elastic buffer according to the frequency of a local clock signal generated by the local clock generator. The control unit obtains a write-in address and a read-out address in the elastic buffer, and sends a control signal to the local clock generator for adjusting the frequency of the local clock signal according to relationship between the write-in address and the read-out address.
    Type: Application
    Filed: December 20, 2013
    Publication date: May 14, 2015
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Kuan-Yu Chen, Yuan-Min Hu
  • Patent number: 9014321
    Abstract: In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming data in transit to the data sink. The electronic device also includes a clock drift compensation controller coupled to the buffer, wherein the clock drift compensation controller is configured to apply either of two predetermined clock drift compensation values to a clock rate for the buffer whenever a buffer fullness status value is offset from a predetermined threshold.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Laurent Le Faucheur, Eric Louis Pierre Badi
  • Patent number: 9001954
    Abstract: A reception circuit that receives data in serial communications through a plurality of lanes includes a plurality of buffers provided for each of the plurality of lanes that each stores data received through corresponding lane, a multilane control circuit that detects the skew between the lanes, and outputs an adjustment instruction for adjusting a read address of a buffer and a deskew information indicating that a skew adjustment between which buffer the lanes is to be performed based on the detected skew, and a plurality of address control circuits provided for each of the plurality of lanes that each transmits the adjustment instruction to a corresponding buffer when receiving the deskew information, wherein the buffer that has received the adjustment instruction adjusting its read address.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: April 7, 2015
    Assignee: Fujitsu Limited
    Inventors: Ryuji Iwatsuki, Kazumi Hayasaka
  • Patent number: 8989331
    Abstract: Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: March 24, 2015
    Assignee: Broadcom Corporation
    Inventors: Sam H. Liu, Zhiqing Zhuang, Chaoyang Zhao, Vinay Bhasin, Chenmin Zhang, Lawrence J. Madar, III, Vafa J. Rakshani
  • Patent number: 8971471
    Abstract: A decoder includes a buffer configured to incrementally transport a synchronous data stream through a path of the decoder. A control circuit is configured to control a depth parameter associated with the buffer and to provide a substantially predictable delay of the synchronous data stream through the path of the decoder.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: March 3, 2015
    Assignee: Imagine Communications Corp.
    Inventor: Junius Adonis Kim
  • Patent number: 8964922
    Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Matthew Felder, Mark Summers
  • Patent number: 8958517
    Abstract: In a clock-adjustment circuit, a phase-detection circuit receives a first clock associated with a first clock domain and a second clock associated with a second clock domain, and determines a phase relationship between the first clock and the second clock. Then, the phase-adjustment circuit in the clock-adjustment circuit adjusts a phase of the first clock relative to the second clock if the determined phase relationship is associated with a metastable range of a first-in first-out (FIFO) buffer that transfers data from the first clock domain to the second clock domain, thereby reducing latency associated with the FIFO buffer.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: February 17, 2015
    Assignee: Oracle International Corporation
    Inventor: Jianghui Su
  • Patent number: 8929467
    Abstract: A one-wire communication bus for transferring a sequence of digital data from a transmitter to a receiver includes (a) an ECDD signal modulation circuit to create an electrical pulse train wherein each pulse's edge is used as clock signal and each pulse's duty cycle is used to represent digital value of zero and one; (b) an ECDD signal demodulation circuit to receive the ECDD pulse train using a group of sampling cells and to decode the sampled results using a majority voting circuit; (c) an electrical connection between a transmitter wherein the ECDD signal modulation circuit resides and a receiver wherein the ECDD signal demodulation circuit resides. Said ECDD signal is sent from the transmitter to the receiver through the electrical connection. Methods of creating the ECDD pulse train in the transmitter and decoding the ECDD pulse train in the receiver are also disclosed.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: January 6, 2015
    Inventor: Liming Xiu
  • Patent number: 8929501
    Abstract: A method and apparatus for processing input data signals transmitted in a continuous mode, or in a burst mode, of signal transmission, such as in a satellite or a computer network communications system. A receiver receives input data signals and a buffer stores the received input data. Processing circuitry generates frame timing synchronization control signals for writing the frames of the input data for storage, generates timing error control signals corresponding to a processing delay for the input data, for synchronizing reading out the stored data from the buffer based on a timing difference between the timing error control signals and the frame timing synchronization control signals to adjust for an arbitrary delay in processing the input data. The processing circuitry can include a tap gradient update circuit for generating a tap gradient corresponding to the read out data, based on equalizer error signals generated by the processing circuitry.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: January 6, 2015
    Assignee: Hughes Network Systems, LLC
    Inventors: Krishnaraj Varma, Tony Huang, Sri Bhat
  • Patent number: 8923441
    Abstract: An overhead processor for data transmission in digital communications is disclosed. Incoming data is transmitted along a datapath. If there are two or more groups of incoming data, arriving separately, the initial group(s) of received data can be held in an elastic store until the arrival of additional group(s) of data, and upon the arrival of additional group(s) of data, all received data are combined and transmitted into flip-flop(s). The data is transmitted from said flip-flop(s) to a logic element to determine the new data context of imminent incoming data prior to any additional incoming bytes arriving along the datapath. Therefore, the number of overhead processors required for multi-byte data transmission is reduced, potentially reducing the number of required overhead processors in digital communications to 1.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: December 30, 2014
    Assignee: Altera Canada Co.
    Inventor: Wally Haas
  • Patent number: 8923337
    Abstract: Instant discloser is a method to transmit multiple data-streams of varying capacity data using Virtual Concatenation (VCAT) over Synchronous Digital Hierarchy (SDH) network, comprising acts of determining number of data bytes to be requested for each Virtual Concatenation Group (VCG) in a row-time of the aggregated bandwidth and storing it in a VCG request configuration memory, reading the requested number of data bytes from each data-stream in order in to a Row Buffer for each row time of an SDH frame, reading data stored in the Row Buffer from memory address determined by one or more connection memory wherein the connection memory is programmed to carry out sequencing of bytes of the Row Buffer based on the VCAT numbering, and inserting path overhead (POH) and pointer information in to the read data streams in previous step to transmit multiple data-streams of varying capacity data using VCAT over SDH network.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: December 30, 2014
    Assignee: Tejas Networks Limited
    Inventor: Kanwar Jit Singh
  • Patent number: 8913705
    Abstract: A mechanism for dynamic skew correction in a multi-lane communication link includes a receiver unit including, for each of the lanes, a first-in first-out (FIFO). The FIFO may store received symbols to locations pointed to by a write pointer and output to downstream logic, symbols stored at locations pointed to by a read pointer. The receiver may also include a symbol drop unit that disables the write pointer in response to receiving a start alignment symbol, and enables the write pointer in response to receiving an end alignment symbol. The receiver also includes an alignment unit that disables the read pointer in response to detecting that the end symbol has been received at least one lane but not all lanes. In addition, the alignment unit may enable the read pointer in response to a determination that the end symbol has been received on all lanes.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: December 16, 2014
    Assignee: Oracle International Corporation
    Inventor: Bruce J. Chang
  • Patent number: 8897408
    Abstract: A method for operating an automation system with a plurality of communication users linked for communication purposes via a serial connection, of which at least one functions as sender and at least one as a receiver, includes determining at a sender an offset value between an occurrence of a synchronous signal and a communication clock cycle, transmitting the determined offset value in a data transmission to the at least one receiver, waiting at the at least one receiver until a time period commensurate with the offset value has elapsed, and generating at the at least one receiver an output signal after the time period has elapsed.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: November 25, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventor: Peter Jänicke
  • Patent number: 8885787
    Abstract: A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. The CDR circuit further includes a delay locked loop (DLL) configured to receive the clock signal from the LCVCO and generate multiple clock phases and a first charge pump configured to control the LCVCO. The CDR circuit further includes a phase detector configured to receive a data input and the multiple clock phases from the DLL, and to align a data edge of the data input and the multiple clock phases.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 8867683
    Abstract: A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer at the first rate, and read from the first and second buffer, at the second rate. Underflow of the first buffer is signaled to the second buffer, thereby avoiding the need to insert defined clock compensation symbols at the second rate. Symbols received at the second buffer while underflow is signaled may be ignored. Conveniently, the second buffer may also be used to align symbol data across multiple symbol streams using periodic alignment symbols. An exemplary embodiment conforms to the PCI Express standard.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: October 21, 2014
    Assignee: ATI Technologies ULC
    Inventor: Haran Thanigasalam
  • Patent number: 8861580
    Abstract: Methods and apparatus are provided for determining one or more channel compensation parameters based on data eye monitoring. According to one aspect of the invention, a method is provided for evaluating the quality of a data eye associated with a signal. The received signal is sampled for a plurality of different phases, for example, using at least two latches, and the samples are evaluated to identify when the signal crosses a predefined amplitude value, such as a zero crossing. It is determined whether the points of predefined amplitude crossing satisfy one or more predefined criteria. One or more parameters of one or more channel compensation techniques can optionally be adjusted based on a result of the determining step. One or more parameters of an adjacent transmitter can also be adjusted to reduce near end cross talk based on a result of the determining step.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: October 14, 2014
    Assignee: Agere Systems LLC
    Inventors: Christopher J. Abel, Mohammad S. Mobin, Gregory W. Sheets, Lane A. Smith
  • Patent number: 8855258
    Abstract: A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an asynchronous gapped clock derived from a first clock having a first frequency. The gapped clock has an average second frequency less than the first frequency. The input serial stream of data is loaded at a rate responsive to the gapped clock. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock, averaged, and an averaged numerator (A and an averaged denominator (AD) are generated. The first frequency is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency. The FIFO memory accepts the jitter-attenuated second clock and supplies data from memory at the second frequency. A framer accepts the data from the FIFO memory and the jitter-attenuated second clock.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: October 7, 2014
    Assignee: Applied Micro Circuits Corporation
    Inventors: Viet Do, Simon Pang
  • Patent number: 8848851
    Abstract: An output signal adjustment system includes a signal adjustment unit, a reference slope generating unit, a slope detecting unit, a voltage-to-current conversion unit, and a control unit. The slope detecting unit compares the slope of the rising and falling edges of the output signal of the reference slope generating unit with that of the signal adjustment unit and outputs a voltage signal. The voltage-to-current conversion unit converts the voltage signal into a current signal. Based on the current signal, the control unit outputs a control signal for controlling the adjustment of the signal adjustment unit to the slope of the rising and falling edges of the output signal. The output signal adjustment system can automatically adjust the slope of the rising and falling edges of the output signal, so that the output signal is insensitive to the packaging, the printed circuit board, the transmission line and other sender loads.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: September 30, 2014
    Assignee: IPGoal Microelectronics (SIChuan) Co., Ltd.
    Inventors: Zhaolei Wu, Guosheng Wu
  • Patent number: 8837655
    Abstract: A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: September 16, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hong Beom Pyeon
  • Patent number: 8787514
    Abstract: An apparatus and method of generating a pseudo noise (PN) code is provided. The apparatus for generating the PN code includes: a memory device unit including a plurality of memory devices; an exclusive-OR (XOR) operation unit receiving output values of at least two memory devices among output values of the plurality of memory devices to output an XOR operation value with respect to the received output values; and a PN code generation unit generating the PN code based on an output value of the XOR operation unit.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: July 22, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seung Il Myong, Jong Sub Cha, Sang Hyun Mo, Jae Heum Lee, Heyung Sub Lee, Jong Suk Chae
  • Patent number: 8775701
    Abstract: A source-synchronous capture unit on a receiving circuit includes a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal to generate a synchronized write enable signal that is synchronized with a first free running clock associated with a memory external to the receiving circuit. The write enable sign is generated in response to a read operation by the receiving circuit. The source-synchronous capture unit also includes a second FIFO unit operable to store data from the memory in response to the first free running clock and the synchronized write enable signal, and to output the data in response to a second free running clock associated with the receiving circuit and a read enable signal.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 8, 2014
    Assignee: Altera Corporation
    Inventor: Ryan Fung
  • Patent number: 8744032
    Abstract: Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: June 3, 2014
    Assignee: STMicroelectronics NV
    Inventors: Steven R. Norsworthy, Jason Rupert Redgrave
  • Patent number: 8736326
    Abstract: A frequency synthesizer and a frequency synthesis method thereof are provided. The frequency synthesizer includes a phase-locked loop unit, a voltage-controlled oscillating unit, and a frequency mixing unit. The phase-locked loop unit receives a reference signal and a feedback injection signal and generates a first oscillating signal according to the reference signal and the feedback injection signal. The voltage-controlled oscillating unit receives the feedback injection signal and generates a second oscillating signal according to the feedback injection signal. The frequency mixing unit is coupled to the phase-locked loop unit and the voltage-controlled oscillating unit, receives the first oscillating signal and the second oscillating signal, and mixes the first oscillating signal and the second oscillating signal to generate the feedback injection signal and an output signal.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: May 27, 2014
    Assignee: National Sun Yat-sen University
    Inventors: Tzyy-Sheng Horng, Chung-Hung Chen, Fu-Kang Wang
  • Patent number: 8737625
    Abstract: A receiving apparatus according to the present invention is able to normally decode reception data even when a part of an initialization symbol during training is corrupted. The receiving apparatus includes an initialization signal generation unit that generates an initialization signal, and a descrambling circuit that descrambles reception data by a descrambler initialized by the initialization signal. The reception data includes a training data set for establishing connection of high-speed serial communication, the training data set including one or more TSn ordered sets. The TSn ordered set includes one or more COM symbols and one or more pieces of data other than COM symbols. The initialization signal generation unit generates the initialization signal at an initialization last timing at which at least the last COM symbol among the COM symbols forming the last TSn ordered set included in the training data set is input to the descrambling circuit.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: May 27, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Motoshige Ikeda, Tadahiro Watanabe, Masahiro Iio
  • Patent number: 8724763
    Abstract: A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. The transmitter predicts the number of encoded frames, Fpred, in the buffer having a limited level and transmits the value, Fpred, to the receiver with the frame. If the transmitter determines that the decoder buffer level is high, the frames being generated by the encoder are small and additional bits are allocated to each frame for each of the N programs. Likewise, if the transmitter determines that the decoder buffer level is becoming low, the frames being generated by the encoder are big and fewer bits are allocated to each frame for each of the N programs. The transmitted predicted buffer level, Fpred, can also be employed to (i) determine when the decoder should commence decoding frames; and (ii) synchronize the transmitter and the receiver clock using feedback depending on the compared level of the decoder to the actual level to Fpred.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: May 13, 2014
    Assignee: Agere Systems LLC
    Inventors: Christof Faller, Raziel Haimi-Cohen
  • Patent number: 8675799
    Abstract: A circuit includes an oversampling logic unit, an alternating current estimator, and a logic processor. The oversampling logic unit generates a plurality of alternating current terms according to an oversampling clock, and outputs a plurality of alternating current terms corresponding to an output clock from the plurality of alternating current terms according to the output clock. The alternating current estimator executes a discrete cosine transform and a discrete sine transform on a plurality of alternating current terms outputted from the oversampling logic unit within a first predetermined time to generate a first value and a second value respectively. The logic processor compares a number of first values and a number of second values within a second predetermined time, and generates a clock data recovery phase locked indicator according to a comparing result.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: March 18, 2014
    Assignee: Etron Technology, Inc.
    Inventors: Huei-Chiang Shiu, Hsuan-Ching Chao, Kuo-Cyuan Kuo, Ming-Kia Chen
  • Patent number: 8666011
    Abstract: A system and method are provided for generating a jitter-attenuated clock using an asynchronous gapped clock source. The method accepts a first reference clock having a first frequency. Using the first reference clock, an asynchronous gapped clock is generated having an average second frequency less than the first frequency. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock. Then, DN and DD are averaged. In response to the averaging, an averaged numerator (AN) and an averaged denominator (AD) are generated. Finally, the first frequency (first reference clock) is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: March 4, 2014
    Assignee: Applied Micro Circuits Corporation
    Inventors: Viet Do, Simon Pang
  • Patent number: 8605846
    Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: December 10, 2013
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Matthew Felder, Mark Summers
  • Patent number: 8588358
    Abstract: A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 8582711
    Abstract: A clock change method includes: converting the serial data synchronized to a first clock into parallel data; latching the serial-to-parallel converted data into a designated data storing circuit with a latch timing that occurs once in every a number of clock cycles of a second clock; and converting the latched parallel data into the serial data synchronized to the second clock, and wherein: each time a packet of serial data synchronized to the first clock is received, a timing adjustment is performed to adjust the latch timing so that the latch timing occurs a predetermined time after occurrence of a conversion timing for converting the serial data synchronized to the first clock into the parallel data.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Limited
    Inventor: Katsuya Tsushita
  • Patent number: 8542788
    Abstract: A blind scan system in a DVB-S system includes a spectrum parameter extractor to fetch and calculate a coarse carrier frequency offset and coarse symbol rate of a signal; a digital mixer to depend on the coarse frequency offset to shift the center of a spectrum of the signal to a position where a DC part of a working spectrum of a digital matched filter locates, so as to produce an offset signal; and an interpolator to perform a down-sampling on the offset signal according to the coarse symbol rate in order to improve the in-band signal-to-noise ratio of the digital matched filter and mitigate impacts due to adjacent channel interferences. Thus, the fine carrier frequency offset and fine symbol rate estimation can be performed accurately.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: September 24, 2013
    Assignee: Sunplus Technology Co., Ltd.
    Inventors: Chun-Chieh Tseng, Po-Fang Huang
  • Patent number: 8532243
    Abstract: A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: September 10, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Srisai R. Seethamraju, Jerrell P. Hein, Kenneth Kin Wai Wong, Qicheng Yu
  • Patent number: 8526558
    Abstract: A method and apparatus for detecting out-of-specification data streams and voltage controller oscillator operation. Data may be received over evaluation periods. Each evaluation period is segmented into n sub-periods. Each n sub-period has the same length. Each n sub-period spans a portion of the data. The corresponding data period starting at each of the n sub-period is evaluated. The sub-period interval counts may be stored in a first-in-first-out register.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: September 3, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventor: Edward L. Grivna
  • Patent number: 8520788
    Abstract: A receiving device includes: a buffer temporarily accumulating receive data received through a network; a data processing means for processing the receive data; a short-time variation value acquisition means for acquiring a short-time variation value indicating variation of accumulated quantity of the receive data sequentially accumulated in the buffer in a first unit time; a long-time variation value acquisition means for acquiring a long-time variation value indicating variation of accumulated quantity in a second unit time; and a clock control means for controlling a clock frequency for performing processing of the receive data by the data processing means in accordance with evaluation results of the acquired long-time variation value. The clock control means stops adjustment of the clock frequency when an error of the network or the receive data is detected, and starts the adjustment again after a given adjustment stop time passes from the detection of the error.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 27, 2013
    Assignee: Sony Corporation
    Inventor: Masayuki Imanishi
  • Patent number: 8477897
    Abstract: Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register for shifting the serial data signal through a number of stages at least equal to (and in many cases, preferably more than) the number of bits in a byte. The output signal of any shift register stage can be selected as the output of this “bit slipping” circuitry so that any number of bits over a fairly wide range can be “slipped” to produce or help produce appropriately aligned bytes. The disclosed bit slipping circuitry is alternatively or additionally usable in helping to align (“deskew”) two or more serial data signals that are received via separate communication channels.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: July 2, 2013
    Assignee: Altera Corporation
    Inventor: Richard Yen-Hsiang Chang