Abstract: A clock signal recovery device has a digital data signal input for the input of a digital data signal and a clock signal output for the output of a recovered clock signal. The digital data signal has a given nominal clock signal frequency. The clock signal recovery device is a digital circuit.

Abstract: An electronic device is provided for generating or utilizing one or more cycle-swallowed clock signals derived based on one or more first clock signals. The device includes a module configured to receive a first clock signal having a first frequency. The module is configured to generate a second clock signal having a second frequency and configured to swallow one or more clock cycles of the first clock signal in generating the second clock signal. The first clock signal has even cycles, and the second clock signal has uneven cycles. The first frequency is greater than the second frequency. The module may include a cycle-swallowing counter. A method and a computer-readable medium are also provided.

Abstract: An up/down detection unit samples a received data signal and determines in which of first through third areas of the data signal the logic level of the data signal transitions, wherein the data sampling clock signal, the first edge sampling clock signal, and the second edge sampling clock signal are sequentially activated. A lower limit detection unit detects a lower limit of the first area if the logic level of the data signal transitions in the first area. An upper limit detection unit detects an upper limit of the third area if the logic level of the data signal transitions in the third area. A phase detection unit determines a delay amount indicating the amount by which the data signal is to be delayed according to the upper limit and lower limit detected. A buffer unit delays the data signal by the delay amount determined by the phase detection unit.

Abstract: A clock data recovery comprises a phase detector, a phase interpolator, an initial phase detector, and an initial phase decoder. The phase detector receives an incoming data stream and an interpolated clock signal and output an early/late value indicating timing relationship between the incoming data stream and the interpolated clock signal. The phase interpolator receives the early/late signal and at least one reference clock signal and generate an interpolated clock signal considering the early/late value and the at least one reference clock signal. The initial phase detector receives the incoming data stream and output a first data indicating a phase of the incoming data stream. The initial phase decoder receives data indicating a phase of the incoming data stream and select the at least one reference clock signal from a plurality of clock signals considering the data indicating a phase of the incoming data stream.

Abstract: In one method, an uplink signal carrying at least one block of transmitted samples is transmitted, and a distorted copy of the uplink signal is received as a downlink signal. A plurality of blocks of received samples are generated based on the received downlink signal, and a time delay and frequency offset between the uplink and downlink signals are determined based on a correlation between the block of transmitted samples and at least one of the plurality of blocks of received samples.

Abstract: A method and apparatus for synchronising a serial data signal to a reference clock signal, the data signal comprising frames of equal length each comprising a known frame alignment word (FAW) and a payload, the frame alignment word being in a consistent position within each frame, the method comprising: storing the signal in a FIFO wander buffer as it is received in order to compensate for any wander that may occur; outputting the data signal stored in the FIFO wander buffer synchronised to the reference clock signal; searching for at least a portion of the frame alignment word in the data signal as it is received; and when it is determined that the frame alignment word has been found, realigning the data signal within the wander buffer. The step of realigning the data may comprise replacing at least a portion of the data signal in the wander buffer with a locally-held copy of at least a portion of the frame alignment word. The method may be used in any synchronous serial data stream, such as SDH or SONET.

Abstract: A method and a circuit for obtaining asynchronous demapping clock. The method includes: obtaining a smoothed clock with even gaps in accordance with data to be demapped and a corresponding clock signal; performing phase locking in accordance with a signal reflecting writing and reading conditions of data of a First In First Out (FIFO), to obtain a clock signal required for demapping. The method can effectively filter off jittering created during asynchronous mapping/demapping processes and may ensure a high-performance clock output. Furthermore, the method is applicable to not only mapping from OTN to SDH but also other asynchronous demapping processes, e.g., mapping from SDH to OTN, and thereby effectively improving the performance of data demapping.

Abstract: Data compression and decompression methods for compressing and decompressing data based on an actual or expected throughput (bandwidth) of a system. In one embodiment, multiple access profiles are utilized to assist in compressing data according to various compression rates and compression ratios.

Abstract: A semiconductor memory device is capable of controlling a tAC with a timing margin in an output data process. The semiconductor memory device includes a delay locked loop circuit, a tAC control unit, a reference signal generating unit, and a data output block. The delay locked loop circuit produces delay locked clock signals through a delay locking operation. The tAC control unit adjusts a delay value of the delay locked clock signals in order to control a tAC timing, thereby generating output reference signals. The reference signal generating unit produces a latch reference signal in response to the delay locked clock signals. The data output block latches data in response to the latch reference signal and for outputting the latched data in response to the output reference signals.

Abstract: A transmitter using pseudo-orthogonal code includes a serial-to-parallel converter for converting serial transmission data into 9-bit parallel data, and a pseudo-orthogonal code memory for receiving the parallel data from the serial-to-parallel converter and outputting 16-bit pseudo-orthogonal code by using the received data as addresses. The pseudo-orthogonal code memory has the relationship of the input address and output code, as expressed in the following equation: c(i)=0.5×((?1)b2?(i1b1)?(i0b0) (?1)b5?i2?(i1b4)?(i0b3) (?1)b8?i3?(i1b7)?(i0b6) (?1)( b2?b5?b8)?i3?i2?(i1(b1?b4?b7))?(i0(b0?b3?b6))) where C(i) is a pseudo-orthogonal code value, i is each bit of the pseudo-orthogonal code, 0?i?15, and b0-b8 are a transmission data bit stream input in the memory as addresses. Accordingly, the transmission efficiency of the transmitter/receiver using orthogonal code can be remarkably improved.

Abstract: The invention relates to a method of transmitting time information relating to the clock of the source of a sending part consisting in using a fixed latency indicator signal to authorize the source to insert time information used to slave the clock of the decoder of the associated receiving part to its clock.

Abstract: A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

Abstract: In one embodiment, the present invention includes a deinterleaver having an input interface to receive orthogonal frequency division multiplexing (OFDM) symbols from a demodulator, a memory coupled to the input interface to store the OFDM symbols, an output interface coupled to the memory to receive the OFDM symbols stored in the memory, and a digital phase lock loop (PLL) to control and adjust a reading rate of data from the memory responsive to dynamic and static channel conditions.

Abstract: Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: A PLL control circuit, which outputs a PLL clock in response to a reference clock, is provided with a frequency adjustment circuit which performs frequency adjustment such that the PLL clock frequency is substantially constant even when the reference clock varies. The frequency adjustment circuit changes a set value in a counter, which determines the PLL clock frequency, in accordance with the variation in the reference clock frequency.

Abstract: A method for digital clock smoothing is provided. The method comprises: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a FIFO two-port memory block; (B) obtaining FIFO depth B by subtracting modulo B for each stored symbol a symbol output address from a symbol input address; (C) inputting FIFO depth B into a programmable look-up table (LUT); (D) obtaining a phase detector error signal; (E) scaling the phase detector error signal to obtain a scaled error factor; (F) adding the scaled error factor to a nominal phase step to obtain a phase update; (G) obtaining a smoothed symbol rate; and (H) reading out each output symbol from FIFO under control of an output FIFO address control register at the smoothed symbol rate.

Abstract: In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.

Abstract: A communication system includes a transmitter that transmits multiple data streams to a receiver in the communication system. Each of the data streams includes data and a skip ordered set. The receiver includes a data buffer for each data stream that stores a minimal skip ordered set based on the skip ordered set in the data stream received by the data buffer. Each of the minimal skip ordered sets has a same number of symbols. Additionally, each buffer stores data of the data stream received by the data buffer. The receiver aligns the data among the data buffers based on the minimal skip ordered sets in the data buffers and outputs the aligned data. In this way, the receiver deskews the data in the data streams.

Abstract: A data output apparatus accumulates received sound data in an accumulating unit (jitter buffer), and reproduces sound based on the accumulated sound data. Then, for a predetermined period of time from the time point at which reception of data starts, the data output apparatus restricts or prohibits discarding of data based on an upper accumulation limit amount as a basis for discarding the accumulated data. Moreover, prior to starting reception of sound data after a transfer of a transmission right, dummy data such as soundless data is accumulated in the accumulating unit. Further, the set values of the upper accumulation limit amount, etc. optimized in the previous communication are stored, and the settings stored in association with a transmitting source apparatus are set as the upper accumulation limit amount, etc. after the transfer of the transmission right.

Abstract: Interface circuitry that is used to interface data between two different clock regimes that may have somewhat different speeds includes the ability to determine which of the clock regimes is faster. Depending on which clock regime is found to be faster, the baseline (nominal difference between data write and data read addresses of a FIFO memory in the interface circuitry) is shifted (i.e., toward the full or empty condition of the FIFO, as is appropriate for which of the clock regimes has been found to be faster). Adjustments may also be made to the threshold(s) used for such purposes as character insertion/deletion and overflow/underflow indication. This technique may allow use of a smaller FIFO and reduce latency of the interface circuitry.

Abstract: An improved reception port for receiving packet data based on the IEEE 1394 standard. The reception port includes a synchronization FIFO memory for receiving reception data in accordance with a reception clock signal and synchronizing the reception data with an internal clock signal, a decoder for decoding the synchronized reception data, and a shaping FIFO memory for outputting the decoded reception data at a fixed timing.

Abstract: A transmission rate adjustment device for supplying MPEG-TS at a desired transmission rate includes: a buffer; a buffer write unit for both sequentially writing to the buffer transport packets of the transport stream that have been read from an MPEG2-TS file and detecting time stamps in the transport stream; and a buffer read unit for transmitting to the MPEG decoder transport packets that have been sequentially read from the buffer at a transmission rate determined by a clock obtained by frequency-dividing a system clock of the MPEG decoder by a frequency division rate designated by a frequency division rate signal. The buffer read unit not only inserts NULL packets between transport packets, but also rewrites time stamps when adjustment cannot be realized by merely inserting the NULL packets.

Abstract: The present invention relates to an apparatus and method for maintaining voice call quality over a packet network by providing optimal de jitter buffer depth and rate of change of depth. Buffer depth and rate of change of buffer depth may be initially determined by classifying the incoming call. Classification of the incoming calls may be accomplished by categorizing calls into groups based on characteristics of the calls. The buffer depth and rate of change of depth may be further optimized at the start of calls based on voice-path delay and packet loss probability measurements over one or more calls of the same class such that the voice-path delay is minimized while maintaining a certain packet loss probability, the packet loss probability is minimized while maintaining a certain voice-path delay, or an R-factor, which is an objective measure of voice quality, is maximized.

Abstract: A clock synchronizer for generating a local clock signal synchronized to a received clock signal. The clock synchronizer incorporates a reference oscillator providing a reference signal, and a synthesizer circuit arranged to synthesize a local clock signal from the reference signal. The synthesizer circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchronizer also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and received clock signals. A control link is arranged to link the clock comparison circuit to the divider.

Abstract: Systems and methods for transporting client data received at a first rate over an interconnect at a second, higher rate, wherein the client data is combined with dummy data according to a pattern that minimizes the amount of buffer space required to store the received client data. In one embodiment, a method comprises receiving client data at the first rate, buffering the client data, retrieving the client data, combining the client data with dummy data according to the pattern, and transmitting the combined data at the second rate. The pattern comprises K blocks, of which a first number contain P w-bytes of client data, and of which the remainder contain P+1 w-bytes of client data. The remainder of the space in the blocks is stuffed with dummy data. The pattern may also include a residual slot that contains one or more bytes of client data.

Abstract: A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

Abstract: Methods for transmitting first packets encapsulated in second packets in a transmission system in which part of the first packets contain a first timing reference for synchronization of a receiver clock and at least part of said second packets contain a second timing reference for reducing transmission jitter of the second packets at the receiver is described. This method provides, at the transmitter, collecting first packets, determining whether a collected first packet contains a first timing reference and triggering transmission of a second packet encapsulating collected first packets including the first packet containing the first timing reference in response to a positive determination.

Abstract: A symmetrical range controller for phase-locked loop circuits includes a first counter coupled to a first signal line, where the first counter is configured to count state transition edges of the first signal, inhibit logic coupled to the first counter, where the inhibit logic is configured to inhibit an output signal of a second counter in response to a predetermined count of the first counter, and reset logic coupled to the first counter, where the reset logic is configured to reset the second counter in response to a full count of the first counter.

Abstract: A packet sending apparatus that improves packet transmission quality by preventing loss of packet information, while minimizing a reduction in transmission rate. A clock frequency deviation correction calculation section calculates a valid packet sending period in which valid packets packet information of which is not lost due to clock frequency deviation between the packet sending apparatus and a packet receiving apparatus are included and the number of valid packets included in the valid packet sending period.

Abstract: The present invention relates to a demodulating device and method in an orthogonal frequency division multiple access (OFDMA) communication system. A demodulating device according to an exemplary embodiment of the invention uses only one demodulator, one slot buffer, and one channel decoder to demodulate a plurality of data bursts included in one frame. In addition, in order to reduce a memory size required to demodulate a plurality of data bursts, a memory is managed in the units of sub-channels, instead of classifying memory cells so as to correspond to the data bursts. According to the demodulating device, it is possible to simplify a hardware structure and to reduce a memory size required to demodulate data bursts. As a result, it is possible to reduce manufacturing costs and decrease the number of signal lines of a channel decoder required for an interface.

Abstract: A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal.

Abstract: A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.

Abstract: Variable phase ring oscillators are described that provide a linear phase progression between adjacent elements in an antenna array by providing a symmetric ring configuration of tuned amplifiers and a single phase shifter. The ring topology is coupled to a single PLL that allows for direct modulation and demodulation of arbitrary waveforms without using RF up/down converting mixers. The PLL distributes the transmit waveforms to all antenna elements in the transmit mode and combines the received waveforms in the receive mode without any complicated power distribution network. Ultra-wideband architectures and methods are described that utilize a first reference signal source, a VPRO, and a second reference signal source. Related methods are controlling an array and beam steering are also described.

Abstract: Embodiments of the present disclosure allow for a linear phase progression between adjacent elements in array by providing a symmetric ring configuration of tuned amplifiers and a single phase shifter. This ring topology is coupled to a single phase locked loop (“PLL”) that allows for direct modulation and demodulation of arbitrary waveforms without using RF up/down converting mixers. In addition, the PLL distributes the transmit waveforms to all antenna elements in the transmit mode and combines the received waveforms in the receive mode without any complicated power distribution network.

Abstract: A system and method for generating signals providing a synthesized wavefront phase to at least one receiver is disclosed. The system includes a buffer having a length of registers and a controller that sequences data through the length of registers. The controller determines at least two dynamically assignable registers along the length of registers to output the data. First and second signal generators are configured to receive the data from respective dynamically assignable registers. Using a clocking signal to sequence the data through the length of registers, the first and second signal generators provide the synthesized wavefront phase, based on the data received from the two dynamically assignable registers.

Abstract: Synchronization of downlink streaming data is performed by estimating the likelihood of an underflow or an overflow in an output buffer upon receipt of each encoded data frame to determine if synchronization will be needed. After each encoded data frame is decoded it is then synchronized if the estimate indicated synchronization would be needed. Synchronization of uplink steaming data is performed by estimating the likelihood of an underflow or an overflow in an input buffer upon sending of each encoded data frame to an output modem for transmission to determine if synchronization will be needed. If needed, synchronization will be performed later on a portion of data samples taken from the input buffer that are used to form a frame of un-encoded data samples.

Abstract: PCR jitter is improved when writing an input stream TS having a packet with a PCR in a memory 10 and reading it at a high speed. An oscillator 44 oscillates a local clock signal having a frequency of a reference clock for the input TS and a counter 46 counts the local clock signal. When a PCR detection section 38 detects the PCR in the input TS, a latch circuit 42 latches a counted value of the counter and a PCR exchange section 40 exchanges the original PCR with a result of subtracting the latched count value from the PCR of the input TS.

Abstract: A method and system for a PCI-Express device is provided. The PCI-Express device includes a buffer memory placed in a receive path for receiving an incoming data stream from a Fibre Channel network, wherein the buffer memory is written in a first clock domain and read in a second clock domain using at least two read pointers that are generated by a read pointer logic module, and read pointer values are adjusted based on whether a character is inserted or deleted to avoid buffer memory underflow and/or overflow conditions.

Abstract: Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.

Abstract: A method, core node, ingress edge node, and egress edge node for matching a bit rate of data input into an optical burst switching network with that of data output from the optical burst switching network are provided. The method includes calculating a difference between a frequency of optical data received on a node and a natural frequency of the node; including the calculated difference into control information; and transmitting the control information. The core node includes a calculator to calculate a difference between frequency of optical data and the natural frequency of the optical data; and a controller to add the difference and a difference included in control information, and output the added difference. The ingress edge node includes a data processor; and a controller. The egress edge node includes an ingress edge node clock recovery phase lock loop; a de-mapper; and a storage unit.

Abstract: Methods and apparatuses for compensating for differences in communication system transmit and receive clock signal frequencies include buffer timing modification and sample addition. In buffer timing modification, a buffer clock signal is interrupted as needed to slow the rate of data through the buffer. In sample addition, pseudo samples are inserted into a data stream to compensate for timing differences.

Abstract: A dual reference input receiver, and a method of receiving, wherein the input receiver includes a first input buffer which is synchronized with and enabled by a clock signal, senses a difference between the input data signal and a first reference voltage, and amplifies the sensing result; a second input buffer which is synchronized with and enabled by the clock signal, senses a difference between a second reference voltage and the input data signal, and amplifies the sensing result; and a phase detector which detects a difference between a phase of output signals of the first and second input buffers, and outputs a signal corresponding to the detection result. The first and second reference voltages may respectively be higher and lower than a median voltage of the input data signal. Thus, a single input data signal is advantageously used and a wide input data eye is provided.

Abstract: Provided is a data delivery system including a transmitter which transmits data stream via a network, and a receiver which receives the data stream and stores it into a reception buffer thereof, and decodes the stored data stream. The network has predetermined therein a necessary amount of data stored in the reception buffer for decoding the received data stream continuously irrespectively of a variation of a time taken for data transfer from the transmitter to the receiver. The receiver starts, after reception of the latter and before the data has been stored up to the predetermined necessary stored amount, decoding of the data stream at a rate lower than assumed at the time of data encoding at the transmitter. When the data has been stored into the reception buffer up to the predetermined necessary stored amount, the receiver changes the decoding data to the assumed rate for decoding further data.

Abstract: An Orthogonal Frequency Division Multiplexing (OFDM) synchronization module includes a window generator module, a symbol timing estimator module, and a reliability metric calculator. The window generator module generates a sampling window that bounds a plurality of samples of OFDM symbols. The symbol timing estimator module generates an estimated symbol timing from the plurality of samples before a fast Fourier transform operation is performed on the plurality of samples. The reliability metric calculator calculates a reliability metric for the estimated symbol timing based on the estimated symbol timing. The window generator module changes at least one parameter of the sampling window based on the reliability metric.

Abstract: A data reproducing system includes: a receiver that receives streaming data via a network; a buffering device that buffers the received data; a reproducing unit that reproduces the data by reading the data from the buffering device; and a controller that controls a reproducing speed of the reproducing unit in response to excess and deficiency of an amount of buffer from a predetermined target value to maintain the amount of buffer of the buffering device at the target value.

Abstract: A digital data processing system receives compressed variable length encoded digital data in the form of variable length codewords in contiguous variable speed Blocks of data. The boundary signals between adjacent codewords are determined and a demultiplexer sequentially sorts the serial digital data among a plurality of parallelly connected buffers for reducing the bit read speed of the buffers. A corresponding plurality of variable length decoders decodes the data from the buffers and outputs the data in parallel form to a multiplexer where it is reassembled into a serial expanded data stream. The incoming data includes selector information in fixed length headers that are separated, buffered and variable length decoded for controlling the demultiplexer. In one aspect of the invention, the data is sorted into substantially equal sized groups of integral codewords for equalizing the loading of the parallel buffers.

Abstract: A digital data processing system receives compressed variable length encoded digital data in the form of variable length codewords in contiguous variable speed Blocks of data. The boundary signals between adjacent codewords are determined and a demultiplexer sequentially sorts the serial digital data among a plurality of parallelly connected buffers for reducing the bit read speed of the buffers. A corresponding plurality of variable length decoders decodes the data from the buffers and outputs the data in parallel form to a multiplexer where it is reassembled into a serial expanded data stream. The incoming data includes selector information in fixed length headers that are separated, buffered and variable length decoded for controlling the demultiplexer. In one aspect of the invention, the data is sorted into substantially equal sized groups of integral codewords for equalizing the loading of the parallel buffers.

Abstract: An apparatus and method for compensating audio signals to be recorded on an optical disc to optimize usage of memory in an audio decoding circuit, and to neutralize invalid audio data to produce good audio quality. A determination is made with regard to whether audio data signals contain normal data or invalid data. Invalid data is adjusted into normal audio data, and stored in the memory. The volume of the data stored in the memory is monitored to detect overflow and underflow conditions of the memory, a data transmitting stopping signal being sent during an overflow condition of the memory, a data transmitting requesting signal being sent during an underflow condition. The audio data reproduced from the memory is decoded, and the decoded audio data is output. Undesired errors are prevented by monitoring the reproduced audio data for invalid data and by adjusting invalid data into normal data when detected.

Abstract: An apparatus and method for compensating audio signals to be recorded on an optical disc to optimize usage of memory in an audio decoding circuit, and to neutralize invalid audio data to produce good audio quality. A determination is made with regard to whether audio data signals contain normal data or invalid data. Invalid data is adjusted into normal audio data, and stored in the memory. The volume of the data stored in the memory is monitored to detect overflow and underflow conditions of the memory, a data transmitting stopping signal being sent during an overflow condition of the memory, a data transmitting requesting signal being sent during an underflow condition. The audio data reproduced from the memory is decoded, and the decoded audio data is output. Undesired errors are prevented by monitoring the reproduced audio data for invalid data and by adjusting invalid data into normal data when detected.

Abstract: An apparatus and method for compensating audio signals to be recorded on an optical disc to optimize usage of memory in an audio decoding circuit, and to neutralize invalid audio data to produce good audio quality. A determination is made with regard to whether audio data signals contain normal data or invalid data. Invalid data is adjusted into normal audio data, and stored in the memory. The volume of the data stored in the memory is monitored to detect overflow and underflow conditions of the memory, a data transmitting stopping signal being sent during an overflow condition of the memory, a data transmitting requesting signal being sent during an underflow condition. The audio data reproduced from the memory is decoded, and the decoded audio data is output. Undesired errors are prevented by monitoring the reproduced audio data for invalid data and by adjusting invalid data into normal data when detected.