Abstract: A data transfer apparatus receives from an upper station a data stream that includes a plurality of types of repeat data, each type of repeat data being repeatedly transmitted by the upper station, and transfers the repeat data to a lower station, the data transfer apparatus including a storage unit having a storage area; an extraction unit for extracting the types of repeat data from the received data stream; a writing unit for writing the extracted repeat data to the storage area; a data structure ratio determination unit for determining a ratio between the types of repeat data to be output in a data stream per fixed length of time; and a data output unit for reading the repeat data stored in the storage unit, and outputting the read repeat data at the determined ratio.

Abstract: The present invention discloses a multiple-stage FIFO mechanism capable of receiving data signals correctly. The circuit includes a write-enable pulse sequencer for sequentially generating a plurality of write-enable signals. An N-stage FIFO sequentially stores an input data and outputs the input data. An output stage selector sequentially generates a control signal. And a multiplexer selectively outputs the input data from the N-stage FIFO.

Abstract: The desynchronizer of the present invention includes two FIFOs. The first FIFO has two address counters (write and read), an intermediate count register, circuitry for calculating the difference between the write and intermediate counts and the intermediate and read counts, a logic block for performing pointer leak and other arithmetic functions, and a digitally controlled oscillator (DCO). The second FIFO has read and write counters, a phase-frequency detector, and an internal VCO controlled by length measurements of the second FIFO. The desynchronizer receives data bits, pointer movement indications, and stuff indications from a DS-3/E3 demapper and, using the first FIFO, the address counters, etc., removes the low frequency components, including SONET/SDH systemic gapping in order to provide the second FIFO with a DS-3/E3 signal having a high frequency phase modulation. The second FIFO removes the remaining high frequency gapping jitter.

Abstract: A testing unit (10) for testing a device under test—DUT—(30) comprises a signal generator (20) for applying a stimulus signal to the DUT (30), a receiving unit (50) for receiving a response signal from the DUT on the applied stimulus signal, and a synchronizing unit (40) for synchronizing a data flow of the response signal between the DUT (30) and the receiving unit (50). The synchronizing unit (40) receives a first clock signal (DUT-CLK) from the DUT (30) and a second clock signal (CLK) of the testing unit (10). The synchronizing unit (40) comprises a buffer (70) for buffering data, a write unit (80) for writing data from the DUT (30) into the buffer (70), and a read unit (90) for reading out data from the buffer (70) to be provided to the receiving unit (50). A write access onto the buffer (70) is controlled by the first clock signal (DUT-CLK), while a read access onto the buffer (70) is controlled by the second clock signal (CLK).

Abstract: A system and method of buffering data of a wireless communication system. The system and method maintain synchronization, end-to-end signaling and coding overhead bits needed to encapsulate data frames sent over wireless media. Additionally, the system and method compensate for transmitting and receiving clock variations. In one embodiment, the system uses framing of data with preamble, stuffing and signaling bits transmitted synchronously at a high data rate in the Industrial, Scientific and Medical (ISM) bands.

Abstract: A sampling frequency conversion apparatus which easily controls the phase difference (time difference) between the input data and the output data in converting the sampling frequency, and comprises storage means 13 for continuously writing the input data or the data obtained by over-sampling the input data and for continuously reading out the data written maintaining a predetermined address difference relative to the write address, and interpolation processing means 14 for interpolating the data read out from the storage means 13 to obtain data of which the sampling frequency is converted. In converting the sampling frequency, an address difference between a write address and a read address in the storage means 13 is optimized, the address difference being optimized without limitation for a predetermined period of time from the start of supplying the input data and, then, being optimized by imposing a predetermined limitation after the passage of the predetermined period of time.

Abstract: A method and apparatus for providing data for sample rate conversion includes processing that begins by generating a data request interrupt based on a system clock and a sample rate conversion value. The processing continues by receiving a data ready control signal from a data processor. The processing proceeds to responding to the data request interrupt by providing a read signal to a temporary memory device. Based on the read signal, a 1st word of data is read from the temporary memory device and provided to a sample rate conversion module. The processing resumes by responding to the data ready control signal by providing a light signal to the temporary memory device. In accordance with the write signal, a 2nd word of data is written to the temporary memory device by the data processor.

Abstract: A method for the selection (puncturing) of data bits from a data word in a data processing system, notably a communication system, wherein, within one cycle of operation of a working processor, the data bit or data bits of the data word that comprises n data bits are selected on the basis of a selection bit register which comprises n selection bits which indicate whether a data bit of the data word is to be selected.

Abstract: A technique provides data from an information signal. The technique involves receiving the information signal in the forwarded clock device synchronously with a forwarded clock signal. The technique further involves recovering data contained within the information signal synchronously with a recovery clock signal such that the data is recovered with (i) a particular cycle latency when the recovery clock signal has an optimal rate for the forwarded clock device, and (ii) a different cycle latency when the recovery clock signal has a sub-optimal rate. The particular cycle latency may include more cycles than the different cycle latency. As such, the time latency may be shorter when the recovery clock signal has the sub-optimal rate.

Abstract: An output driver includes an adjustable main output stage and a control circuit with a digital delay locked loop (digital DLL) circuit and an adjustable scaled output stage. The main output stage and the scaled output stage are both configured to adjust their strengths in response to a control signal generated by the control circuit. The control circuit receives a clock signal and propagates a transition through the scaled output stage. The DLL circuit compares the propagation time through the scaled output stage with a reference signal (that is dependent on the clock signal frequency) and generates the control signal as a function of comparison. The main output stage, receiving the same control signal, adjusts its strength in a corresponding manner.

Abstract: Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a “sub-bit” comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term “sub-bit” means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit.

Abstract: A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. In particular, a system and method for dual loop data synchronization using a granular FIFO fill level indicator is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL, which represents a fill level of a FIFO. A granular FIFO fill level indicator of the DLL provides input to the phase shifter to adjust the frequency of the PLL accordingly. Thus, the frequency of the data input rate can be controlled and a constant fill level of the FIFO can be maintained. A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

Abstract: A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

Abstract: An apparatus for resynchronizing data signals by using dual port data buffer storage, which prevents data corruption and subsequent system disruption from happening by employing a mechanism to keep an adequate distance between read and write address pointers. An input unit receives an incoming data stream having a cyclic data structure of N bytes. A data writing unit sequentially writes each data word of the received data stream into a storage unit with a capacity of 2N bytes in synchronization with a first clock. A data reading unit sequentially reads out each data word from the storage unit in synchronization with a second clock. A detection unit tests whether the write and read address pointers have come within a predetermined threshold distance. A relocation unit moves the read address pointer by N bytes to increase the distance between the read and write address pointers, when the detection unit has detected that the write and read address pointers have come within the threshold distance.

Abstract: In a data communication network, a system clock rate can be inferred at a receiver by measuring the data rate during successive periods. This information is used to adjust or adapt a receiver output clock to the inferred system clock. To adapt a receiver buffer output clock frequency to the buffer input clock frequency, the level of the buffer is periodically monitored. If the fill level is greater than an upper threshold, the output clock frequency is incremented. If the fill level is less than a lower threshold, the output clock frequency is decremented. A count is maintained of the number of successive adjustment operations performed while the fill level is outside the range bounded by the thresholds. When the fill level returns to the bounded range, a number of reverse frequency adjustments are performed. The number of reverse frequency adjustments are less than the number of earlier opposite frequency adjustments, preferably by a factor of two.

Abstract: A system and method for maintaining a constant delay when a switch between two or more possible input data streams is made. Data received on a selected stream is buffered as it is received, the timing of this buffering being based on link timing recovered from the selected stream. Stable local timing information is generated from the link timing. It is stable in the sense that it is subject to only a very small shift when a switch in the selected data stream is made. Data is then read from the buffer on the basis of the local timing information thereby producing an output stream with a constant delay.

Abstract: A method and apparatus for controlling bit slips in a high-speed, two-way, communications channel. More particularly, the entire communications system, comprising, inter alia, a receiver, a transmitter and the physical communications channel is operated as a feedback loop. That is, the detection of bit slips is performed continuously in the receiver and a bit slip signal is generated that indicates the number of bit slips and the direction, i.e., forward or backward, of the bit slip. Thus, the bit slip signal is communicated to the transmitter and certain actions are performed to introduce bit adjustments in the bit stream to eliminate the effects of any future bit slips. The bit slip signal contains an indication of the number of bit slips which have occurred, the time between bit slips, and the direction of the slip. As a function of this information from the bit slip signal, bit adjustments are made in the communications stream to correct for the bit slips and mitigate any effect in future transmission.

Abstract: An elastic buffer structure and process to avoid overflow or underflow in serial protocol communications using spread spectrum transmit and receive clocks or other separate transmit and receive clocks which may be running at different frequencies. Overflow and underflow are averted by storing received data in a FIFO at different addresses using a receive address pointer incremented at a receive clock rate. Other circuitry senses which addresses have nonessential primitives or nonessential data that can be deleted. Data is transmitted out of the FIFO at a transmit clock rate using a transmit address pointer incremented at the transmit clock rate. Control logic compares the transmit pointer to the receiver pointer, and when the distance between the pointers becomes too large or two small, inserts additional nonessential primitives or nonessential data or deletes nonessential primitives or nonessential data so as to maintain the distance between the pointers at a constant, selected value.

Abstract: An asynchronous data conversion system enables high conversion efficiency and reliability to be secured because it is capable of preventing lack of the data or redundancy of the data, and if lack of the data or redundancy of the data occurs, it is capable of detecting it by way of error. In a system where a write clock is asynchronized with a read clock, from the state relationship of HIGH/LOW in between a write enable signal and a read enable signal, a write ready signal with a writing to a latching section as holding state, a read ready signal with a reading-out as holding state are generated at a ready signal generating section synchronizcd with the write clock. When it is incapable of writing to latching section newly, outputting a write error signal from a write error detecting section. When the data for reading-out to the latch section does not exist, outputting the read error signal from the read error detecting section.

Abstract: A control interface for the bit rate of digital data to be recorded as well as a control interface for the bit rate of digital data emanating from a reading device, particularly when the digital data constitutes a high bit rate uninterrupted data stream such as a video data stream in the MPEG II format. Each control interface comprises a memory circuit for storing the data to be recorded or to be read and a device for storing the data to be recorded or read in the memory circuit so as to fill the memory circuit to a predetermined level. The storing device includes a gauge for generating an information item giving the fill level of the memory.

Abstract: A jitter reducing apparatus using a digital modulation technique includes: an elastic store storing data flowed in from an SDH network; a pattern generator controlling a data read speed so the elastic store maintains a constant data storing amount; a modulation sequencer generating a digital signal wave having a constant period and amplitude; and a phase level detector controlling the pattern generator using the digital signal wave of the modulation sequencer.

Abstract: A high speed interface type device can reduce power consumption and a circuit area, and transmit/receive a 4 bit data in one clock period. The high speed interface type device includes a DRAM unit for generating first clock and clock bar signals which do not have a phase difference from a main clock signal, and second clock and clock bar signals having 90° phase difference from the first clock and clock bar signals in a write operation, storing an inputted 4 bit data in one period of the main clock signal according to the first clock to second clock bar signals, synchronizing the stored data with data strobe signals according to the first clock to second clock bar signals in a read operation, and outputting a 4 bit data in one period of the main clock signal, and a controller for transmitting a command, address signal and data signal synchronized with the main clock signal to the DRAM unit in the write operation, and receiving data signals from the DRAM unit in the read operation.

Abstract: A communication device (101) includes multiple antennas (201-203), multiple receivers (222-224), and a processor (225). The communication device receives a first radio frequency (RF) signal via a first antenna (201) of the multiple antennas and a second RF signal via a second antenna (202) of the multiple antennas. The communication device determines a signal metric for the first RF signal and a signal metric for the second RF signal, compares the determined signal metrics to produce a signal metric comparison, and generates an error signal based on the signal metric comparison. The error signal may be remotely monitored for prompt corrective action.

Abstract: An asynchronous sample rate tracker based on a phase-locked loop quickly locks to an input sample rate, even when the input sample rate equals the resident, or internal, sample rate of an asynchronous digital sample rate converter. The phase difference between the input write data and output read data is maximized to reduce data lost due to excursions in the input sample rate. In one embodiment, a binary shift register is used to generate a read pointer step size according to the derivative of the difference between a write pointer position and a read pointer position.

Abstract: One aspect of the present invention provides a packer-unpacker (PUP) for a digital serial interface which allows a plurality of processors to access time slot registers of a serial data stream relating to the digital serial interface. A configuration register is maintained either by one of the plurality of processors or by each of the processors to arbitrate access to the individual time slot registers. Another aspect of the invention allows one or more processors to efficiently access and/or write more bits to a resource such as a time slot register than the width of the processor's respective data bus allows. Extra bits registers are maintained for at least one of the read and write direction data busses. The extra bits correspond to the least significant bits conventionally ignored in changing from a data bus of one width to a data bus of a narrower width. The extra bits in the write direction are accessed, e.g.

Abstract: A method for fixing the propagation delay between a user terminal and another station in a non-synchronous LEO satellite communications system, to adjust plural signals to have substantially similar times-of-arrival, uses an elastic buffer to insert a variable delay in the received signal processing, so as to cause a fixed time for each data/vocoder bit, from the time that bit enters the transmit modulation process until the time that same data/vocoder bit is output to a user.

Abstract: A signal receiving circuit is provided which is capable of receiving sample data, even if a number of sample data to be transmitted from a transmitting terminal does not coincide with that of sample data to be received by a receiving terminal without an occurrence of discontinuity in received sample data.

Abstract: A method and apparatus is provided that solves the problem of data overrun and underrun, for example in a system that exchanges data using the Gigabit Ethernet protocol. A single 8-bit data path is provided as output and the main protocol state machines are kept running in the clock domain of the rest of the circuit, after an elasticity FIFO, so that no additional synchronization is necessary. The invention makes no demands upon the receive clock other than those specified in the relevant standard for duty cycle and accuracy. The invention correctly combines the two effective data streams back into a single data stream, only modifying the FIFO when it is acceptable to do so, and in a way that does not corrupt data packets passing through the FIFO. By providing a minimal set of logic running in the receive clock domain, it is possible to simplify the design of the main protocol state machines. Only a very small portion of the design must be aware of the dual-clock nature of the physical interface.

Abstract: An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate (S).

Abstract: The invention relates to data transfers between devices having asynchronous clocks. A FIFO having multiple levels holds the data while en route from a sender to a receiver. The invention monitors the FIFO. When all levels become full, the invention issues a FIFO_FULL signal. When all levels become empty, the invention issues a FIFO_EMPTY signal. In these signals, there are four events whose timing is important. (1) The ACTUATION of the FIFO_FULL is immediate; (2) the ACTUATION of the FIFO_EMPTY signal is immediate; (3) the DE-ACTUATION of the FIFO_FULL signal is synchronous with the clock of the computer reading the FIFO; (4) the DE-ACTUATION of the FIFO_EMPTY signal is synchronous with the clock of the computer writing to the FIFO. The invention allows throughput through the FIFO to proceed at a very high speed, even though the sender and receiver are asynchronous.

Abstract: A system and method of buffering data of a wireless communication system. The system and method maintain synchronization, end-to-end signaling and coding overhead bits needed to encapsulate data frames sent over wireless media. Additionally, the system and method compensate for transmitting and receiving clock variations. In one embodiment, the system uses framing of data with preamble, stuffing and signaling bits transmitted synchronously at a high data rate in the Industrial, Scientific and Medical (ISM) bands.

Abstract: In a frequency control arrangement 200 of the type comprising an oscillator 270, a mark or space counter 210, a frequency detector 220 and an error signal calculator 230-260, 290 and in which it is desired to control the oscillator 270 to resonate at a frequency substantially equal to the frequency of a received data stream, the oscillator 270 is implemented as a four phase ring oscillator (FIG. 1, ref 110) arranged to provide phased clock signals to the mark or space counter (FIG. 1, ref 100). This allows the mark or space counter to be arranged to measure the length of the marks or spaces of the data with increased resolution.

Abstract: A system and method of buffering data of a wireless communication system. The system and method maintain synchronization, end-to-end signaling and coding overhead bits needed to encapsulate data frames sent over wireless media. Additionally, the system and method compensate for transmitting and receiving clock variations. In one embodiment, the system uses framing of data with preamble, stuffing and signaling bits transmitted synchronously at a high data rate in the Industrial, Scientific and Medical (ISM) bands.

Abstract: An asynchronous signal input apparatus includes a memory device which writes data that are input at a predetermined frequency, in response to a write signal, and reads data in response to a read signal. A data quantity measuring device measures a data quantity representing a quantity of data stored in the memory device. A read signal generating device generates the read signal at a frequency that varies depending upon the measured data quantity. A sampling frequency conversion apparatus comprises the memory device, data quantity measuring device, and read signal generating device employed in the asynchronous signal input apparatus. Further, the read signal generating device includes a converter which performs non-linear conversion on the data quantity measured by the data quantity measuring device.

Abstract: A method and arrangements for extracting a plurality of clock signals for signal-processing circuits, in particular for a digital modem, from a supplied clock signal, for the clock signals to be extracted to be formed in each case from an output signal of an accumulator of predefined bit width n. The accumulator accumulates in each case an increment in the clock pulse of the supplied clock signal and, in the process, performs a modulo2n operation.

Abstract: A net sample is added or removed from an audio sample stream by fading in or out fractional samples over many sample periods. A sample-rate converter has a FIFO that is written with an input sample by an input clock synchronized to the input audio stream. The samples are read from the FIFO by a derived clock. The derived clock is generated from an output clock using a nominal ratio of Q/P. Read and write counters for the FIFO are compared. When the write counter is ahead of the read counter by exactly a target amount the derived clock is a ratio of Q/P of the output clock. When the write counter is ahead of the read counter by more than the target, the read rate is increased by removing one net sample over many sample periods. When the write counter is ahead of the read counter by less than the target amount, the read rate is decreased by adding one net sample over many sample periods.

Abstract: A retiming arrangement for use in a demultiplexer in an SDH data transmission system uses Bit Justification data, and not Pointer data, to modify a recovered clock signal and generate a clock signal for retiming purposes. The invention is especially for use in enabling third party users to carry primary rate timing data across an SDH network.

Abstract: A hearing aid with different assemblies for picking up, further processing and adjusting an acoustic signal to the hearing ability of a hearing impaired person, wherein a digital signal processing is performed in the hearing aid, has a buffer storage unit which shifts or transposes a defined frequency region into another frequency region which is better detectable by the wearer of the hearing aid. The buffer storage unit has individual storage segments for receiving and storing digital data representing acoustic content of an incoming audio signal, and the read-in and read-out frequency of the buffer storage unit differs by a defined factor.

Abstract: An output buffer circuit includes an adjustable delay time and is coupled to a reference output buffer which includes an adjustable delay time and a fixed delay time. In one embodiment, a synchronous delay line circuit provides a reference signal having a predetermined delay time. The time delay is equal to 1/N of a clock signal cycle. The reference output buffer uses the reference signal to set a cumulative delay time for the reference output buffer equal to 1/N. The adjustable delay time of the output buffer is set equal to the adjustable time delay of the reference output buffer.

Abstract: Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a “sub-bit” comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term “sub-bit” means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit.

Abstract: A multiple-channel data communication buffer includes a transmit first-in-first-out (“FIFO”) circuit and a receive FIFO circuit. The transmit and receive FIFO circuits each include a write pointer array, a read pointer array and a single memory device having a data input, a data output, a write address input, a read address input and a plurality of logical channels from the data input to the data output. The write pointer array has a write pointer for each of the logical channels and applies a selected one of the write pointers to the write address input based on a write channel number input. The read pointer array has a read pointer for each of the logical channels and applies a selected one of the read pointers to the read address input based on a read channel number input.

Abstract: A jitter resistant clock regenerator for receiving program data transmitted on a transmission channel in synchronism with a transmission clock signal and cancelling jitter, having occurred on the channel, to restore from the transmitted program data a highly accurate program clock signal from which the jitter is removed. The regenerator includes a buffer for temporarily storing transmitted data received over the channel. A read clock selector monitors the buffer to determine the amount of the transmitted data stored in the buffer, and selects one of read clock signals in response to the data amount. A program clock acquisition circuit reads out the transmitted data from the buffer in response to a read clock signal selected by the selector, and restores the clock signal of the program data from the transmitted data.

Abstract: A digital signal processing circuit comprising a memory means for storing a digital signal obtained from a playback channel; a control means for writing the digital signal in the memory means at a first rate and reading out the digital signal from the memory means at a second rate lower than the first rate; and a processing means for executing a desired process relative to the digital signal thus read out from the memory means. The digital signal is written in the memory means at a first rate by the memory control means and is read out therefrom at a second rate lower than the first rate. And then a desired signal process is executed relative to the digital signal read out from the memory means. Therefore the required digital processing rate becomes lower than the transmission rate of the playback channel, whereby the transmission rate can be raised despite the condition that the time required for the desired signal process such as demodulation is rendered longer.

Abstract: A one stage first-in-first-out synchronizer includes a producer side and a consumer side. The producer side includes a first write buffer, a not full output, a write input, a second write buffer and a write clock input. The first write buffer stores a write pointer. The not full output indicates whether new data may be written. The write input is asserted to write data. The second write buffer receives as input a read pointer. The write clock input is used to provide a clock signal to the first write buffer and the second write buffer. The consumer side includes a first read buffer, a not empty output, a read input, a second read buffer, and a read clock input. The first read buffer stores the read pointer. The not empty output indicates whether stored data may be read. The read input is asserted to read data. The second read buffer receives as input the write pointer. The read clock input is used to provide a clock signal to the first write buffer and the second write buffer.

Abstract: A data stream (DS) comprises a time multiplex of coded data (D) and control data (C). The data stream (DS) may be, for example, of the MPEG type representing a sequence of pictures. The coded data (D) is transcoded (T) so as to obtain transcoded data (DT) which differs in size from the coded data (D). The control data (C) is adapted for the transcoded data (DT) so as to obtain adapted control data (CA) which does not substantially differ in size from the control data (C). The transcoded data (DT) and the adapted control data (CA) are written into a transcoder output buffer (TOB) and read from the transcoder output buffer (TOB) so as to obtain a transcoded data stream (DST). This allows an efficient use of a transmission channel via which the transcoded data stream (DST) is to be transmitted and, consequently, it allows a satisfactory transcoding quality.

Abstract: The bit stream reproducing apparatus is comprised of a frame length counter for measuring a data length of one frame; a first calculator for calculating a data length “L1” defined from a header to a scale factor; a second calculator for calculating a data length “L2” of an audio sample; and a third calculator for executing a calculation of E=F−(L1+L2×12) based upon calculation results of the first calculator and of the second calculator, and for sending out a control signal to a muting circuit so as to instruct a muting operation in the case of E<0.

Abstract: A device for synchronization of a block counter in an RDS receiver, the decoder of which, after synchronization has been effected, is capable of performing an error correction in the received bits. The process steps which can lead to synchronization of the block counter are integrated into the process steps for error correction, and are repeated in each bit period.

Abstract: The invention dynamically compensates for differences in data rates for multistreamed systems. Any or all of the streams in a multistreamed system may be individually compensated at one time. In one embodiment, the status of an input buffer is monitored and used to change the number of oversamples within a frame of one of the number of streams. In another embodiment, a high frequency clock in the system is used to stall one of the streams for one or more clock cycles. In both ways, distortion due to differences in data rates is reduced.

Abstract: One-bit digital signal processing apparatus for generating an output one-bit signal by switching from a first to a second one-bit signal in response to a detection that m consecutive bits of the first and second signal are identical, the apparatus comprising means for varying m in dependence on the urgency of the switching operation.

Abstract: A timing signal supplying device in a doubled timing synchronous system includes: a timing signal adjusting portion which feeds back a timing signal of a timing signal receiving circuit and a frequency signal of a transmitting buffer to regenerate a timing signal and compares the timing signal with an external input timing signal to detect and correct an error of the timing signal; and a timing signal transmitting portion which sequentially transmits the corrected signal of the timing signal adjusting portion and the regenerated timing signal to the timing signal receiving circuit.