Abstract: A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.

Abstract: A method and apparatus are provided for transmitting and receiving a plurality of individual tributary signals in multiplex form via a common line. At the transmitting end, the tributary signals, each of which has a similar initial frequency, are converted into a compound signal having a frame structure with a common data rate. At the receiving end, each individual tributary signal is retrieved from the compound signal with its initial frequency. A phase information signal portion including a respective phase difference between each tributary signal and the compound signal is formed and inserted into the compound signal in the shape of respective coded bits. The initial frequency of each tributary signal is recovered from the phase information signal portion included in the respective coded bits belonging to the respective tributary signals.

Abstract: Methods and apparatuses for compensating for differences in communication system transmit and receive clock signal frequencies include buffer timing modification and sample addition. In buffer timing modification, a buffer clock signal is interrupted as needed to slow the rate of data through the buffer. In sample addition, pseudo samples are inserted into a data stream to compensate for timing differences.

Abstract: Disclosed is an apparatus and method for transforming data transmission speed that transforms data transmission speeds of data transmitting apparatuses that have different data transmission speeds using a DPRAM. By using a DPRAM to transform transmission speeds, the apparatus and method for transforming data transmission speed is simplified, thereby improving the procedure for transforming data transmission speed. Furthermore, it is possible to prevent data from being lost at the time of transforming data transmission speed.

Abstract: An integrated circuit arrangement clocked by a single clock having variable delays to different regions of said arrangement such that said regions are partially synchronized to each other, the arrangement comprising: a data transfer buffer for buffering a data stream for transfer between respective first and second ones of said regions, and a data transfer controller, associated with said data transfer buffer and said respective regions, configured to control transfer of said data stream by: initially synchronizing between said respective regions at a start of said data stream, receiving data, in said buffer, from said first region, at a predetermined rate, and outputting said data stream to said second region at said predetermined rate in accordance with said initial synchronization. The arrangement allows deterministic data patterns to arrive at the receiving domain at minimal hardware cost.

Abstract: Signal processing apparatus, including a circuit which processes signals received on multiple channels so as to extract therefrom at least first and second sequences of symbols, and a FIFO, which receives and stores at least one bit of each of the symbols in a first interval of the first sequence and a second interval of at least the second sequence, the second interval at least partially overlapping the first interval. The apparatus includes a predictor, which determines, for each of the symbols in the first interval of the first sequence an expected value of the at least one bit in a corresponding one of the second symbols in the second interval, and logic, which compares the expected value with the at least one bit of each of the second symbols in the FIFO, so as to determine a relative skew between the first and at least the second channel.

Abstract: A system and method for aligning data transferred across circuit boundaries having different clock domains. The system includes a buffer circuit comprising a latch for receiving data clocked in a first clock domain and latching the received data in a second clock domain by one of a first edge of a second clock signal, or a second opposite edge of the second clock signal. The first and second clock signals are of the same frequency but operating out of phase. A control circuit receives the first and second clock signals and determines a phase relationship therebetween. The control circuit generates a control signal based on the determined phase relationship which is implemented for selecting one of a rising edge of the second clock signal, or a falling edge of the second clock signal, for latching action in the second clock domain. Reliable data transfer operation is provided for all possible phase relationships of the first and second clock signals.

Abstract: A receiver for digital data is provided. The receiver comprises a ring buffer operable to store received data. The receiver also comprises a write pointer controller for the buffer, operable to control the writing of received data into the buffer, and a read pointer controller for the buffer, operable to control the reading of data from the buffer. The receiver further comprises a pointer adjustment controller operable, in response to a detection of a special data indicator, to control at least one of the write pointer controller and the read pointer controller using forward looking operable to foresee a data location within the buffer corresponding to a future read location of the buffer.

Abstract: An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.

Abstract: A technique includes providing a butter to receive data from a processor of a wireless device in response to an active mode of the processor and selectively coupling an input terminal of a filter to the buffer based on a status of the buffer. The techniciue may be used with a wireless system that includes a digital signal processor, a buffer, a wireless interface and a switch. The buffer receives data from the digital signal processor in response to an active mode of the digital signal processor. The switch selectively couples a terminal of the wireless interface to the buffer in response to a determination of a status of the buffer.

Abstract: A desired FIFO buffer fill level is continuously derived during mapping or demapping of plesiosynchronous data signals into synchronized data signals, or vice-versa. One of j predefined integer values Ii is repetitively consecutively produced during each consecutive one of j FIFO buffer write clock cycles, where i=1, . . . , j and where j and the integer values Ii are selected such that ? i = 1 j ? ? I i j closely approximates the number of bits read from the FIFO buffer per FIFO buffer write clock cycle. During each kth consecutive FIFO buffer write clock cycle, a Bits_Read value Ik+Ik-1 is produced where k=1, . . . , p; a Bits_Written value is produced; a Gap_Pattern value is derived by subtracting the Bits_Read value from the Bits_Written value; and, the Gap_Pattern is added to a predefined value representative a FIFO buffer center fill level to produce the desired FIFO buffer fill level.

Abstract: The present invention is for an apparatus that receives input data at a non-uniform first data rate carried by a system clock, and provides output data at a substantially uniform second data rate that is nominally equal to the first data rate and is also carried by the system clock. The system clock is faster than the first or second data rates and accordingly, a write enable signal controls the input data that is written into a saturating elastic store and a read enable signal controls the reading and output of data from the saturating elastic store. The saturating elastic store includes a plurality of storage locations and provides a storage fill level indicative of the amount of storage locations currently holding data. A digital filter receives the storage fill level and filters the storage fill level to provide a control word to a digitally controlled read enable signal generator.

Abstract: A semiconductor integrated circuit includes first and second data paths, first to third flip flops and logic circuits. The first data path transfers input data. The first flip flop is coupled to the first data path for temporally storing data received from the first data path in response to a first clock signal that is delayed from a reference clock signal. One of the logic circuits receives data from the first flip flop and another logic circuit outputs output data. The second flip flop is connected between the logic circuits for transferring signal between them in response to the reference clock signal. The third flip flop is connected to another logic circuit for outputting the output data in response to a second clock signal that is advanced from the reference clock signal. The second data path transfers data received from the third flip flop.

Abstract: An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one “symbol group” at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from the buffers having start symbols is temporarily suspended.

Abstract: Disclosed herein are circuits in which a plurality of clock signals are generated by corresponding clock generators from one or more common clock references. The clock generators accept control values that specify the phases of the individual clocks. The actual phase of each clock signal potentially varies during operation, and the phases of the various clock signal are generally independent of each other. To detect or measure phase relationships, the disclosed circuits evaluate or compare the control values using arithmetic logic.

Abstract: A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

Abstract: Data, such as data received by a memory I/O from a memory unit in a DDR SDRAM system, is captured using a trigger signal, which may be a non free-running clock signal such as a DQS signal in a DDR SDRAM system, and is transferred to a host system, which may be part of an ASIC, using the host system's clock. The memory I/O includes a data capture register that latches the data received from the memory unit using DQS. The memory I/O also includes a FIFO buffer that latches the data output by the data capture register using a delayed version of DQS. A single edge of the delayed DQS is available to the FIFO for latching each set of data that corresponds to a single pulse of DQS. The FIFO transfers the data to the host system using the host system's clock, which represents a different clock domain than DQS.

Abstract: A digital communications system that can asynchronously map/de-map digital signals from one clock domain to another, while reducing mapping jitter levels and permitting higher levels of integration. The digital communications system includes an asynchronous stuff bit insertion circuit, an asynchronous stuff bit removal circuit, and a communications network connected therebetween. The asynchronous stuff bit insertion circuit includes a first elastic store, a barrel shifter, and a stuffing circuit. The asynchronous stuff bit removal circuit includes a de-stuffing circuit, a second elastic store, and a frequency control path including a phase-locked loop having a variable divider circuit, the operation of which is controlled based on the presence/absence of stuff bits in the data provided to the de-stuffing circuit.

Abstract: A synchronization interface transfers multi-bit digital data or signal between multiple clocked logic domains while maintaining data or signal integrity. When deployed in a processor-based system, in one embodiment, a plurality of data units may be received at a source location in a first clocked domain. To control writing of the plurality of data units from the source location to a target location in a second clocked domain, an enable signal may be detected. This enable signal may be synchronized with respect to the second clocked domain. Finally, in response to the synchronized enable signal, the plurality of data units may be transferred from the first clocked domain to the target location in the second clocked domain. The synchronization interface may comprise a data path to capture the multi-bit digital data or signal based on a control logic implementing a mechanism (e.g.

Abstract: An elastic store circuit includes a set/reset flip-flop circuit corresponding to plural pieces of input data and an AND circuit for receiving the output of each flip-flop circuit. Upon receipt of a frame pulse indicating the head of each piece of input data, the flip-flop circuit outputs a signal to the AND circuit. The AND circuit outputs an H signal when it receives signals from all flip-flop circuits, and detects the receipt of the data having the longest delay time. According to the output signal of the AND circuit, data is read from each unit of elastic store memory.

Abstract: An audio apparatus for performing digital data processing on voice and audio signals through interrelated data sampling and processing. A predetermined mixing processing in the audio apparatus is performed by a first digital processing circuit on both (a) digital received-voice signals converted into the signals sampling processed at a frequency n×fs by a first sampling frequency conversion circuit, and (b) digital audio signals converted into the signals sampling processed at the frequency n×fs by a third sampling frequency conversion circuit. Another predetermined mixing processing is performed by a second digital processing circuit on both (i) digital audio signals converted into the signals sampling processed at a frequency N×Fs by a second sampling frequency conversion circuit, and (ii) digital voice signals converted into the signals sampling processed at the frequency N×Fs by the third sampling frequency conversion circuit.

Abstract: A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially the same phase as that of the input signal. To generate the phase matched signal, PR may use a clock signal provided by a single side band oscillator, CMU, or a clock signal having substantially the same level of jitter as that of the input signal to generate the phase matched signal. FIFO may sample the phase matched signal and store such samples. CMU may request and output samples from the FIFO at a frequency determined by a reference clock signal.

Abstract: A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially the same phase as that of the input signal. To generate the phase matched signal, PR may use a clock signal provided by a single side band oscillator, CMU, or a clock signal having substantially the same level of jitter as that of the input signal to generate the phase matched signal. FIFO may sample the phase matched signal and store such samples. CMU may request and output samples from the FIFO at a frequency determined by a reference clock signal.

Abstract: An apparatus and a method for transmitting data between transmission systems using clock sources having dissimilar phases is disclosed. After monitoring a state of a transmission system of the other party, when the transmission system of the other party is in a normal state, a write address is generated according to a first system clock, and generation of a read address is enabled after a prescribed time interval has elapsed from the generation time of the write address. By generating the write address and a read address with a certain time interval, it is possible to prevent a write address and a read address from being generated at the same time, and accordingly address collision and data loss caused by address collision can be prevented.

Abstract: A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.

Abstract: In real time communication, long interruption of a media data signal caused by underflow or overflow of a buffer is reduced. A monitoring unit 35a monitors a state of the buffer 34 periodically. When the number of encoded data in the buffer 34 shows tendency of increasing from a standard data storage number, successively a predetermined number of times, then, it is judged that the buffer tends to overflow. And, the decoding unit 35 is made to skip at least one encoded data to be read and processed this time from the buffer 34. Further, when the number of encoded data in the buffer 34 shows tendency of decreasing from the mentioned standard data storage number, successively the predetermined number of times, then, it is judged that the buffer tends to underflow. And, the processing unit 35 is made to suspend operation during at least one period of the above-mentioned reproduction period.

Abstract: A jitter measurement circuit is described comprising delay elements arranged in a serially-connected chain, and first and second sets of circuitry. Each delay elements has an associated delay, an input and an output that produces a delayed version of the signal at the input. The first set of circuitry is configured to detect propagation of the significant instant of the input clock signal through each of the delay elements and produces a pulse in response thereto. The width of the pulse is approximately equal to the delay of the corresponding delay element. The second set of circuitry has one storage element corresponding to each output of the first set of circuitry, for receiving a trigger signal that is timed to correspond to a delay which is approximately half of the total delay of the chain, and for recording in the corresponding storage element any pulse that is active at the time of occurrence of the trigger signal.

Abstract: The present invention relates to an apparatus and method for maintaining voice call quality over a packet network by providing optimal de-jitter buffer depth and rate of change of depth. Buffer depth and rate of change of buffer depth may be initially determined by classifying the incoming call. Classification of the incoming calls may be accomplished by categorizing calls into groups based on characteristics of the calls. The buffer depth and rate of change of depth may be further optimized at the start of calls based on voice-path delay and packet loss probability measurements over one or more calls of the same class such that the voice-path delay is minimized while maintaining a certain packet loss probability, the packet loss probability is minimized while maintaining a certain voice-path delay, or an R-factor, which is an objective measure of voice quality, is maximized.

Abstract: A wireless telephone includes first and second baseband processors. The first baseband processor functions as system master, and the second processor functions as system slave. The first baseband processor interfaces to system controls, such as power supply, man-machine interface (MMI), and the like. The master processor implements a first pair of buffers in the downlink direction and a second pair in an uplink direction. The buffers in the pairs are swapped periodically, based on an internal counter running on the master processor. The timing of the master processor is continuously adjusted to that of the slaved co-processor, by counting a number of samples received from the microphone respectively fed to the earpiece between the beginning of consecutive frames. The timing of the master processor is then adjusted accordingly. The output of the counter may be lowpass filtered to separate jitter from frequency deviation.

Abstract: There is provided a data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising: a first circuit for holding the bus data which is synchronous with the first clock and is input at each predetermined timing; a second circuit for generating a first timing signal which is synchronous with the first clock and is corresponding to the predetermined timing; a third circuit for generating a second timing signal which is synchronous with the second clock, from the first timing signal; and a fourth circuit for receiving the bus data output from the first circuit based on the second timing signal, to output the bus data in synchronism with the second clock.

Abstract: A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock signal, one of the clock termination circuits applies the terminating impedance to the transmission path that carries the clock signal while the other clock termination circuit(s) applies a high impedance to the transmission path. The receiver also includes a plurality of high rate serial bit stream buffers and a clock signal buffer along with the clock termination circuitry. In other embodiments, the receiver includes a deserializer and may include a controller. The receiver may service a dual link Digital Visual Interface.

Abstract: An integrated circuit and a method for tuning an internal clock signal with respect to data that is to be emitted includes an adjustment circuit with a compensating circuit for synchronizing the internal clock signal with respect to the data that is to be emitted. Setting data, which is dependent on first adjustment data and on second adjustment data, is applied to the compensating circuit. The first adjustment data is determined using a tuning method during the front-end test, and is stored in a read only memory. The second adjustment data is determined in a fine-tuning method in the finished manufactured component, and is stored in a read/write memory.

Abstract: An elastic buffer for buffering a stream of data blocks includes a controller and a memory space, wherein multiple data blocks can be written and read during a single write or read clock cycle, respectively. Multiple read addresses are used for each read operation, allowing read access to non-contiguous memory locations during a single read cycle when desired. Therefore, the elastic buffer can perform clock correction and channel bonding operations on data streams that include correction and alignment data block sequences that do not match the width of the memory space. A stagger bit can be used to indicate the timing of read address adjustments during clock correction and channel bonding operations.

Abstract: A method for the selection (puncturing) of data bits from a data word in a data processing system, notably a communication system, wherein, within one cycle of operation of a working processor, the data bit or data bits of the data word that comprises n data bits are selected on the basis of a selection bit register which comprises n selection bits which indicate whether a data bit of the data word is to be selected.

Abstract: A method and apparatus for buffering data samples in a software-based ADSL modem. The method includes receiving samples of data in a buffer and determining if the received samples of data will exceed the storage capacity of the buffer. Selected samples of data from the buffer are deleted in response to the storage capacity being exceeded. The selected samples of data that were deleted are then reconstituted.

Abstract: A method of transmitting digital signals which are passed via a communication system by means of a retimer between an input and an output, whereby according to the invention the data packet applied to the input is scanned with respect to the individual bits and within the individual bits and preferably at the center and the scanned data level is transmitted immediately to the output.

Abstract: A digital AV signal processing apparatus includes a buffer for storing digital data input to the digital AV signal processing apparatus, and outputting the digital data as output digital data, a D/A converter for converting the output digital data to analog data, a voltage-controlled oscillator for generating a clock signal to control a conversion rate of the D/A converter, and a voltage-controlled oscillator controller for detecting a data amount of the digital data stored in the buffer, and controlling a frequency of the clock signal based on a deviation in the detected data amount from a first predetermined value and a time integral of the deviation value.

Abstract: A method includes receiving an indication of incoming data from a first serial bus and buffering the bits to accommodate a difference between a first rate of the incoming data and a second rate of outgoing data. During the buffering, the method includes detecting if at least some of the bits indicate a synchronization field.

Abstract: The present invention discloses a multiple-stage FIFO mechanism capable of receiving data signals correctly. The circuit includes a write-enable pulse sequencer for sequentially generating a plurality of write-enable signals. An N-stage FIFO sequentially stores an input data and outputs the input data. An output stage selector sequentially generates a control signal. And a multiplexer selectively outputs the input data from the N-stage FIFO.

Abstract: In the field of optical communications, the need to remove jitter from a Synchronous Digital Hierarchy (SDH) or Synchronous Optical NETwork (SONET) datastream is recognized. Consequently, the present invention provides a First-In-First-Out (FIFO) buffer having a read-out clock frequency that is controlled in response to a depth error of the FIFO buffer. The control of the read-out clock frequency is achieved by a hardware control loop coupled to the FIFO buffer. The period of the control loop is a product of the frequency at which the depth error of the FIFO buffer is acquired and another factor. The another factor is the number of states of logic employed by the control loop raised to an integer power.

Abstract: The invention provides a novel scheme to match the clock rates along a single transmission channel. The rate matching aspect of this invention receives a character stream synchronized by a first clock and buffers the character streams. Buffered characters are then transmitted over an output channel synchronized by a second clock. The rate matching system removes one or more filler or removable characters from the output channel if an overflow condition is detected and inserts one or more filler or removable characters in the output channel if an underflow condition is detected.

Abstract: Synchronization and desynchronization of a data signal transported in a synchronous frame across a synchronous communications network, such as SONET/SDH, reduces waiting-time jitter. A timing estimate (F) indicative of a relationship between a data rate (f1) of the data signal and a reference frequency (f2) of the synchronous communications network is calculated and communicated through the synchronous communications network, for example in the Synchronous Payload Envelope of a SONET frame. The data signal is recovered using a desynchronizer Phase-Locked Loop steered by the timing estimate (F). The timing estimate (F) can be any one or more of: a ratio between the data rate (f1) and the reference frequency (f2); a difference between the data rate (f1) and the reference frequency (f2); and a phase difference between a recovered data clock signal associated with the data rate (f1) and a reference clock signal associated with the reference frequency (f2).

Abstract: A first serial buffer having a delivering end may deliver first data from a first position. A second serial buffer having a delivering end may deliver second data from a second position. The first position relative to the delivering end of the first serial buffer may be different than the second position relative to the delivering end of the second serial buffer.

Abstract: In a method for adaptive synchronization of a data sink device to a data source device coupled by a USB, data is received and stored in a buffer of the sink device at an average data rate representative of the data rate of the source device. A data level for the buffer is determined based on input packet size and output packet size. An accumulated data level for the buffer is compared with a threshold level. A clock frequency for the sink device is corrected when the accumulated data level exceeds the threshold level.

Abstract: A method and apparatus for adaptively adjusting the parameters of a timing loop based upon frequency errors between a data signal and a receiver's clock that is being used to sample the data signal are provided by the present invention. In accordance with the invention, the timing loop parameters are first set to an initial set of parameter values. A current frequency error between the data signal and the receiver's clock is calculated. The approximate average value of the frequency error is then determined. After a predetermined amount of time, the absolute value of the difference between the average frequency error and the current frequency error is examined. If the absolute value of the difference is less than a specified threshold, the timing loop parameters are reset to a second set of parameter values contained in a memory. The timing loop parameters are then reset to a third set of parameter values after a second interval of time.

Abstract: A clock generation circuit capable of generating a high-frequency clock with a simple circuit configuration, together with a data transfer control device and an electronic instrument using the same. The clock generation circuit has: serially-connected inversion circuits IV0 to IV4 in which an output of IV4 is connected to an input of IV0 by a feedback line FL; and buffer circuits BF0 to BF4 which receives outputs from IV0 to IV4. The inversion circuits IV0 to IV4 are disposed along a line LN1 and the buffer circuits BF0 to BF4 are disposed along a line LN2 that is parallel to the feedback line FL but different from LN1. Dummy lines DL0 to DL3 each of which having parasitic capacitance that is equal to that of the feedback line FL are connected to the inversion circuits IV0 to IV3, to equalize the phase differences between clocks CK0 to CK4. The feedback line FL and the dummy lines DL0 to DL3 are disposed in a region between the inversion circuits IV0 to IV4 and the buffer circuits BF0 to BF4.

Abstract: A system and method for compensating for differences between a recovered receive clock and an internal transmit clock in an elastic buffer and thereby preventing corruption of data. In one embodiment, the system comprises a circularly accessed buffer coupled to read and write logic. The read and write logic read and write to locations within the circular buffer as indicated by respective read and write pointers. The system further comprises control logic which compares the pointers to determine whether the buffer is approaching an underflow or overflow condition and adds or deletes fill words between frames of data to compensate for the underflow or overflow condition. In one embodiment, the system includes fill word logic which is configured to add a fill word bit to each received word and to set or clear the fill word bit to indicate whether or not the corresponding word is a fill word.

Abstract: According one embodiment, an apparatus and method are disclosed for a dynamic phase aligning input interface. In the embodiment, a first device provides data to a second device. According to the embodiment, the interface is counter clocked, the second device being clocked by a first clock signal and providing a second clock signal source to the first device for clocking the data. The first device transmits the second clock signal and the data to the second device, with the second clock signal being delayed by the period of time required for the second clock signal source to propagate through the first device. The second device detects the phase of the first clock signal and the second clock signal and modifies the phase of the second clock signal source to align the phase of the first clock signal and the phase of the second clock signal.

Abstract: An apparatus including a frame buffer memory; a set of frame synchronizers coupled to the frame buffer memory; and, a set of receivers coupled to the buffer memory and a corresponding frame synchronizer in the set of frame synchronizers. Each receiver is configured to receive a data stream having a first clock rate, and detect changes in the data stream using a second clock rate.

Abstract: A jitter reducing apparatus using a digital modulation technique includes: an elastic store storing data flowed in from an SDH network; a pattern generator controlling a data read speed so the elastic store maintains a constant data storing amount; a modulation sequencer generating a digital signal wave having a constant period and amplitude; and a phase level detector controlling the pattern generator using the digital signal wave of the modulation sequencer.