Abstract: A solution to the word alignment problem in a Serializer Deserializer (SERDES)/Media Access Controller environment is to have for each SERDES lane: a recovered clock, a Write Pointer counter and a FIFO. Misaligned words are simply stored in their FIFO's according to the respective recovered clocks and straightforward increments of the various Write Pointers WP_i. One of the lanes is selected as a reference, and the contents of the other FIFO's are inspected to determine the nature of their misalignment, if any. Then the values from the Read Pointer counters RP_i are individually offset by corresponding amounts to compensate for the misalignment, so that when data is read it is indeed aligned. These offsets by corresponding amounts are simply individual per lane adjustments to the various Read Pointers, and cooperate with the adjustments to those Read Pointer for rate matching.

Abstract: Disclosed are a signal control apparatus, a transmission system and a signal resynchronization control method, which efficiently prevent the occurrence of slipping and execute high-quality signal resynchronization control. The signal control apparatus comprises a serial/parallel converting section, a window setting section and a parallel/serial converting section. The serial/parallel converting section performs serial/parallel conversion on an input signal to yield parallel data. The window setting section sets a small window having a readout guarantee area narrowed at an optimal position at the time of reading the parallel data when an operational state is unstable, and sets a large window having the readout guarantee area widened from the optimal position when the operational state is stable.

Abstract: An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device Initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one “symbol groups” at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from buffers having start symbols is temporarily suspended.

Abstract: A method for transmitting data via a data bus with minimized digital control and data inter-symbol interference. The voltage level on the bus is not permitted to reach the bus negated quiescent voltage level set by the bus terminator voltage. Additional time is provided for data detection circuitry to detect a first segment of data transferred over the bus. A pause time is enabled after the bus has been at idle/paused for a prolonged period. After the first segment of data has been transferred, the method returns to normal operation by pausing for a normal period of time for data detection circuitry to detect subsequent segments of data transferred over the bus. Additionally, during prolonged synchronous data transfers with unchanged data bits, the data bus is inverted and driven for further regulating the data bus voltage.

Abstract: A jitter buffer controller allows the depth of the jitter buffer to be adjusted dynamically according to the varying jitter of the current sequence. The contents of the jitter buffer are examined during a transmission. If the delay or average delay within the buffer drops to a predetermined threshold, then the size or depth of the jitter buffer is increased.

Abstract: A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially the same phase as that of the input signal. To generate the phase matched signal, PR may use a clock signal provided by a single side band oscillator, CMU, or a clock signal having substantially the same level of jitter as that of the input signal to generate the phase matched signal. FIFO may sample the phase matched signal and store such samples. CMU may request and output samples from the FIFO at a frequency determined by a reference clock signal.

Abstract: A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially the same phase as that of the input signal. To generate the phase matched signal, PR may use a clock signal provided by a single side band oscillator, CMU, or a clock signal having substantially the same level of jitter as that of the input signal to generate the phase matched signal. FIFO may sample the phase matched signal and store such samples. CMU may request and output samples from the FIFO at a frequency determined by a reference clock signal.

Abstract: The present invention provides a simple smaller-sized elastic integrated circuit having a lower power, to which data synchronized with a first clock is input and which outputs data synchronized with a second clock. The elastic integrated circuit includes a read address counter which operates with an internal clock to output a read address count value; a delay circuit to which the read address count value is input and which delays and outputs the read address count value by a predetermined time period; a write address counter which operates using the read address count value output from the delay circuit with a clock externally input so as to output a write address count value; and a memory circuit which writes data input thereto by the write address count value and reads data written therein by the read address count value.

Abstract: An elastic store circuit using a first in/first out buffer (FIFO) to accurately control the phase delay in a waveform using the write (WR) and read (RD) clocks is provided. The FIFO reads the input data at the WR clock rate. The data exits the FIFO in response to the RD clock. Large delays are accomplished by changing the relationship between the WR and RD clocks in whole clock intervals. Delays and adjustments of less than a whole clock interval are accomplished by changing the phase relationship of the RD clock with respect to the WR clock. The present invention generates the WR and RD clocks through synthesis using a lower frequency reference clock. The RD clock phase change results from phase-locking the RD clock to a phase offset version of the reference clock. A method of introducing precise delays through phase delay of the RD clock with respect to the reference clock is also provided.

Abstract: The present invention is for an apparatus that receives input data at a non-uniform first data rate carried by a system clock, and provides output data at a substantially uniform second data rate that is nominally equal to the first data rate and is also carried by the system clock. The system clock is faster than the first or second data rates and accordingly, a write enable signal controls the input data that is written into a saturating elastic store and a read enable signal controls the reading and output of data from the saturating elastic store. The saturating elastic store includes a plurality of storage locations and provides a storage fill level indicative of the amount of storage locations currently holding data. A digital filter receives the storage fill level and filters the storage fill level to provide a control word to a digitally controlled read enable signal generator.

Abstract: In a clock signal reproducing circuit in a pulse stuffed synchronizing system, a destuffing circuit removes stuff pulses and unnecessary bits from a higher order group signal to output a lower order group signal, and outputs stuff data indicating existence or non-existence of positive stuff or negative stuff in the higher order group signal. A storage circuit stores the lower order group signal outputted from the destuffing circuit. A stuff rate determining circuit determines a stuff rate from a difference between the number of positive stuffs and the number of negative stuffs to a stuffing possible period of the higher order group signal based on the stuff data outputted from the destuffing circuit. A variable frequency divider frequency-divides a clock signal of the higher order group signal based on the control signal outputted from the control circuit.

Abstract: A serial data receiving circuit includes a serial-to-parallel converter and a data selector. The serial-to-parallel converter converts the oversampled data fed from an oversampling circuit to m×n bit parallel data. The data selector, receiving (m×n+&agr;) bits of data simultaneously from the serial-to-parallel converter, where &agr; is a natural number indicating the bit number of the data selected from the previous and/or subsequent oversampled data to be added to the m×n-bit data, evaluates all the (m×n+&agr;) bits of data as candidates to be likely selected, and outputs the n-bit parallel data from the (m×n+&agr;) bits of data. The serial data receiving circuit can output the right data in spite of jitter included in the data or clock signal.

Abstract: A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e.g., including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver.

Abstract: A digital variable-frequency oscillator has an output frequency thereof variable in dependence upon a frequency control variable. Externally input data are stored in a data storage device, from which the data are generated in accordance with the output of the digital variable-frequency oscillator. A remaining data amount of the data storage device is detected in response to an externally input timing signal that is received in synchronism with the data received by the data storage device such that synchronization is performed based on the timing signal. A filtering operation is performed on values of the frequency control variable so as to calculate an average value of the frequency control variable. A new value of the frequency control variable is calculated based on the calculated average value and the difference between the detected remaining data amount of the data storage device and a target data amount thereof.

Abstract: An apparatus comprising three sampling circuits to sample incoming data and a quarter clock. A clock generation unit is included to generate at least three sampling clocks from a local clock. Each of the three sampling clocks are configured to sample the incoming data and the quarter clock. A phase detector is also included to detect a phase difference between the quarter clock and the local clock and to generate a recovered quarter clock. A delay line is further included to delay the sampled incoming data and the recovered quarter clock by the detected phase difference.

Abstract: A reception interface unit in a transmission system wherein time series data is divided into data groups and a data packet with reproduction specification time data specifying a time at which each data piece in the data groups should be reproduced, added to the data groups is transmitted on a transmission bus in a time division manner.

Abstract: A technique includes providing a first clock signal to a parallel-to-serial data conversion circuit and providing a second clock signal to a memory storing data for conversion by the conversion circuit. One of the first and second clock signals is selectively synchronized to a reference clock signal.

Abstract: A method and apparatus for multiplexing and demultiplexing multiple serial data streams provide double the data throughput on a single media channel, such as Fibre Channel (EC). A first incoming data stream is routed to a first synchronizer unit, which receives a 0-degree phase signal of a local clock operating at the same basic frequency as that of the incoming data. The first synchronizer unit establishes and maintains synchronization of the first data stream with the 0-degree phase signal. A second incoming data stream is routed to a second synchronizer unit, which receives a 180-degree phase signal of the local clock. The second synchronizer unit establishes and maintains synchronization of the second data stream with the 180-degree phase signal. The synchronizer units maintain synchronization of the respective data streams by applying an elasticity function to the data streams.

Abstract: The present invention is directed to an improved telecommunication receiver for receiving wireless multi-path communication signals. A novel RAKE receiver and a time diverse integration system for the calculation of the relative power of received signal samples are provided. Preferably, the receiver is embodied in a UE or base station of a CDMA wireless telecommunication system, such as a 3GPP system.

Abstract: An integrated circuit device for use in forming a communication interface for an enterprise server including a system controller, at least one CPU, a system bus communicatively interconnecting the controller and the CPU, a system memory, a first optical interface for facilitating data transport between the device and SONET based networks, and a second optical interface for facilitating data transport between the device and ethernet/Fibre Channel based networks.

Abstract: A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock signal, one of the clock termination circuits applies the terminating impedance to the transmission path that carries the clock signal while the other clock termination circuit(s) applies a high impedance to the transmission path. The receiver also includes a plurality of high rate serial bit stream buffers and a clock signal buffer along with the clock termination circuitry. In other embodiments, the receiver includes a deserializer and may include a controller. The receiver may service a dual link Digital Visual Interface.

Abstract: Complementary signals on a pair of first signal lines are transferred onto a pair of second signal lines in synchronization with a clock signal by a buffer circuit. The buffer circuit includes an equalize circuit to equalize a pair of internal nodes to a prescribed potential, a transfer gate circuit activated, when the equalize circuit completes equalization, to couple the pair of first signal lines and the pair of internal nodes, an amplifier circuit to differentially amplify the signals on the internal nodes when the transfer gate completes the transfer operation, an output transfer circuit to transmit the signals on the pair of internal nodes onto the pair of second signal lines in synchronization with the clock signal, and a control circuit to control the operation of the equalize circuit, the transfer gate circuit and the amplifier circuit. After the pair of internal nodes is equalized to the prescribed potential, the signals from the pair of first signal lines are received and amplified.

Abstract: A data transmitter is having a source of data. The data is transmitted in response to clock pulses provided by a clock pulse generator. A buffer having a fixed data storage capacity is provided for storing the data transmitted by the source of data, such data being stored in response to the clock pulses. A framer is provided for retrieving the stored data in response to a data strobe signal produced by the framer and fed to the buffer. The buffer produces a control signal representative of the level of the buffer. A level signal is fed to the clock pulse generator. A superframe strobe signal samples the level of the buffer and produces a level signal representative of the sampled level of the buffer. A clock pulse generator is provided for producing the clock pulses for the data source and the buffer at a rate selected in accordance with the level of the buffer.

Abstract: Signal processing apparatus, including a circuit which processes signals received on multiple channels so as to extract therefrom at least first and second sequences of symbols, and a FIFO, which receives and stores at least one bit of each of the symbols in a first interval of the first sequence and a second interval of at least the second sequence, the second interval at least partially overlapping the first interval.

Abstract: An apparatus comprising a first programmable circuit configured to present (i) a first parallel data signal and (ii) a first control signal in response to one or more serial data signals and a second programmable circuit configured to generate a second parallel data signal in response to (i) the first parallel data signal, (ii) the first control signal and (iii) a second control signal.

Abstract: An NGIO Elastic Buffer is provided for enabling link data received from an NGIO link to be synchronized into a receiver clock domain of a data receiver responsible for processing that data in a computer network. Such Elastic Buffer may comprise a memory coupled to receive link data from a data transmitter and to store the link data in a plurality of addressable memory locations; a write control mechanism which operates at a link clock for selecting as a write address the address of a memory location of the memory to store the link data, and for preventing an IDLE signal included in the link data from being stored in the memory so as to prohibit data overflow in the memory; and a read control mechanism which operates at a receiver clock for selecting as a read address the address of a memory location of the memory to retrieve the link data as receiver data, and for inserting No-Operation (NOP) sequences into the receiver data when the memory is determined empty so as to prohibit data underflow in the memory.

Abstract: The present invention provides a signal integrity measurement method and apparatus which allows for signal characteristics to be measured by obtaining samples taken at the midpoint of the data stream. The invention provides a measurement device that is suitable for use in the field to provide a measurement of signal characteristics within transmitted data streams. The invention is particularly suitable for field measurement of signal characteristics of data streams or continuous in-line monitoring of signal characteristics within transmitted data streams. The signal characteristics include, but are not limited to eye opening jitter, noise, slope efficiency, average power and peak-to-peak amplitude.

Abstract: An apparatus and a method for transmitting data between transmission systems using clock sources having dissimilar phases is disclosed. After monitoring a state of a transmission system of the other party, when the transmission system of the other party is in a normal state, a write address is generated according to a first system clock, and generation of a read address is enabled after a prescribed time interval has elapsed from the generation time of the write address. By generating the write address and a read address with a certain time interval, it is possible to prevent a write address and a read address from being generated at the same time, and accordingly address collision and data loss caused by address collision can be prevented.

Abstract: A desynchonizer for a synchronous digital communications system serves to recover a useful signal from a synchronous digital input signal. It comprises a buffer for temporarily storing the input signal, a write circuit for writing the input signal into the buffer, a clock-generating circuit for generating a clock signal, and a read circuit for reading the contents of the buffer at the recovered clock rate. According to the invention, the clock-generating circuit includes a calculating circuit for determining an average over the interval between two pointer actions of the input signal, and derives from the average a tuning signal which serves to adjust the recovered clock signal. In this manner, jitter caused by pointer actions which result from a constant offset of the effective bit rate of the received virtual containers is eliminated.

Abstract: A spread spectrum modulated signal generator is disclosed that reduces the storage requirement for storing values representing filter responses of input signal samples in a digital filter by taking advantage of time-reversal symmetry of the responses. Moreover, the disclosed signal generator supports up-ramping and down-ramping for smooth transmission of spread spectrum modulated signals.

Abstract: A reception interface unit in a transmission system wherein time series data is divided into data groups and a data packet with reproduction specification time data specifying a time at which each data piece in the data groups should be reproduced, added to the data groups is transmitted on a transmission bus in a time division manner.

Abstract: A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

Abstract: In a method for reducing latency in packet telephony caused by buffering at the conversion stage between analog audio signals and digital audio data, analog audio is sampled at a rate far greater than necessary for telephony. The increased sampling rate allows the audio data to pass much more rapidly through the data conversion buffer. After passing through the buffer, the data is downsampled to a rate normally used for telephony. To handle audio data for speaker output, the data is upsampled to a rate far in excess of the rate necessary for processing telephony-grade voice signals. The increased sampling rate allows the audio data to pass much more rapidly through the data conversion buffer. After passing through the buffer, the data is converted into an analog audio signal for sending to the speaker. In this way, latency due to the buffering that accompanies the process of converting audio signals to digital data, or vice versa, is minimized.

Abstract: The present invention provides a receiver apparatus for receiving digital data in which stuff data have been inserted by stuffing synchronization. The receiver apparatus has a memory unit having a plurality of memory cells. The digital data other than the stuff data are written in the memory unit in synchronization with a write clock signal, and read from the memory cell in synchronization with a read clock signal. The cycle of the read clock signal is adjusted on the basis of an interval from a reading address to an writing address of the memory cell.

Abstract: An apparatus and method for compensating audio signals to be recorded on an optical disc to optimize usage of memory in an audio decoding circuit, and to neutralize invalid audio data to produce good audio quality. A determination is made with regard to whether audio data signals contain normal data or invalid data. Invalid data is adjusted into normal audio data, and stored in the memory. The volume of the data stored in the memory is monitored to detect overflow and underflow conditions of the memory, a data transmitting stopping signal being sent during an overflow condition of the memory, a data transmitting requesting signal being sent during an underflow condition. The audio data reproduced from the memory is decoded, and the decoded audio data is output. Undesired errors are prevented by monitoring the reproduced audio data for invalid data and by adjusting invalid data into normal data when detected.

Abstract: A jitter suppression apparatus in a data transmission system includes a phase detector circuit to determine a plurality of phase errors between sync pulses of a data line and sync pulses of a reference line, and an adapted phase error offset circuit, coupled to the phase detector circuit, to generate a plurality of phase error offsets and adaptively offset the plurality of phase error offsets. The jitter suppression apparatus may also include a stuff/delete slicer, coupled to the adapted phase error offset circuit, to generate a plurality of stuff/delete signals such that a framer can determine what type of data frames to send to a communication channel of the data transmission system. A jitter suppression method includes steps of detecting a phase error, computing a phase error offset, and filtering out the phase error offset. An integrator may be used to filter out the phase error offset input to the stuff/delete slicer.

Abstract: A method for processing received voice data in a voice data processing system including a receiving buffer.

Abstract: A synchronization device for a synchronous digital message transmission system producing a synchronous output signal including successive transport modules synchronized to a frame clock from a digital input signal. The synchronization device includes a receiver unit for receiving the input signal, a packet assembly device for packaging the input signal into subassemblies of the transport modules, a buffer memory, a writer for writing data bits of the input signal out of the subassemblies into the buffer memory with a write clock, a reader, for reading data bits out of the buffer memory with a read clock in order to form the output signal, and a sending unit (SO) for sending synchronous output signals. The effective bit rate of the subassemblies compared to the standardized value is either lowered or raised by selecting the write clock lower than the read clock.

Abstract: An apparatus receives and demodulates digital signals encoded in multiple formats. The apparatus includes multiple processor units and a memory embedded with the processor units, and a cache connected to each of the processor units. The cache for communicating between the plurality of processors. The embedded memory can include data and instruction memory. The processor units and memory are configured as a multi-mode receiver demodulator front-end capable of receiving digitally modulated signals in multiple formats, and demodulating the signals in real-time in response any one of the multiple formats.

Abstract: Data reception circuit for receiving a serial input data stream with a high data transfer rate, where the data reception circuit has a data stream separation circuit (4) for separating the serial input data stream into a plurality of separate data streams with a reduced data transfer rate, a reference clock signal generation circuit (13) for generating a reference clock signal whose clock frequency corresponds to the data transfer rate of the separate data streams, a delay circuit (12) having a delay element chain (27) which comprises a plurality of series-connected delay elements, the first delay element (27-1) in the delay element chain (27) receiving the generated reference clock signal, and each delay element outputting a delayed reference clock signal via a signal output (11) in the delay circuit (12), a first, asynchronously clocked register array (8) which comprises a plurality of register banks (26), each register bank (26) in the first register array (8) being asynchronously clocked by an associated

Abstract: The invention provides an apparatus, and related method, for receiving and synchronizing parallel data transmitted over multiple serial data channels. The synchronization technique uses a channel lock FIFO buffer on each received serial data channel. The FIFO buffers are configured to tolerate a significant amount of jitter between channels and clock tree delay within the synchronization apparatus.

Abstract: An address generator for generating addresses in an prescribed order in the case of writing/reading data to/from predetermined storage means, comprises a first address data generating means for generating a plurality of first address data which have predetermined address intervals, a second address data generating means for generating a plurality of second address data representing sequentially shifted positions of the first address data one row by one row within address intervals, and an addition means for generating addresses which have predetermined intervals in order by adding the second address data to the first address data.

Abstract: A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. The decoder buffer level limits are specified in terms of a maximum number of encoded frames (or duration). The transmitter can predict the number of encoded frames, Fpred, in the decoder buffer and transmit the value, Fpred, to the receiver with the audio data. If the transmitter determines that the decoder buffer level is becoming too high, the frames being generated by the encoder are too small and additional bits are allocated to each frame for each of the N programs. Likewise, if the transmitter determines that the decoder buffer level is becoming too low, the frames being generated by the encoder are too big and fewer bits are allocated to each frame for each of the N programs. The transmitted predicted buffer level, Fpred, can also be employed to (i) determine when the decoder should commence decoding frames; and (ii) synchronize the transmitter and the receiver.

Abstract: A digital signal processing circuit having a memory for storing a digital signal obtained from a playback channel; a controller for writing the digital signal in the memory at a first rate and reading out the digital signal from the memory at a second rate lower than the first rate; and a processor for executing a desired process relative to the digital signal thus read out from the memory. The digital signal is written in the memory at a first rate by the controller and is read out therefrom at a second rate lower than the first rate. And then a desired signal process is executed relative to the digital signal read out from the memory. Therefore the required digital processing rate becomes lower than the transmission rate of the playback channel, whereby the transmission rate can be raised despite the condition that the time required for the desired signal process such as demodulation is rendered longer.

Abstract: A clock smoothing circuit generates a smoothed clock signal from a gapped clock signal having unevenly spaced pulses separated by gaps that result from the removal of data bits and from a reference clock signal having evenly spaced pulses that create a predetermined reference frequency. A smoothing element is coupled to the input elements to receive the gapped clock signal and the reference clock signal. In one embodiment, the smoothing element generates a smoothed clock signal having one pulse for each of the pulses in the gapped clock signal and having a frequency that is greater than one-half of the predetermined reference frequency. Each pulse in the smoothed clock signal is synchronized with a pulse in the reference clock signal.

Abstract: A method and apparatus are provided for transmitting and receiving a plurality of individual tributary signals in multiplex form via a common line. At the transmitting end, the tributary signals, each of which has a similar initial frequency, are converted into a compound signal having a frame structure with a common data rate. At the receiving end, each individual tributary signal is retrieved from the compound signal with its initial frequency. A phase information signal portion including a respective phase difference between each tributary signal and the compound signal is formed and inserted into the compound signal in the shape of respective coded bits. The initial frequency of each tributary signal is recovered from the phase information signal portion included in the respective coded bits belonging to the respective tributary signals.

Abstract: A radio data communication system includes a transmitter which transmits data at a predetermined transmission rate and has a table determining transmission rates in correspondence with reception levels of data, and a receiver which receives data transmitted from the transmitter. The receiver detects data error of the data transmitted from the transmitter and transmits detecting result of the data error to the transmitter. The transmitter obtains a transmission failure rate in response to the detecting result of the data error transmitted from the receiver, and changes the transmission rate with reference to the table based on the transmission failure rate.

Abstract: An arrangement for time-correct combination of a first, continuous digital data stream (V1), comprising a sync signal (S), with a second, discontinuous digital data stream (V2), the arrangement comprising, for the purpose of equalizing these discontinuities:

Abstract: An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate(S).

Abstract: A method and apparatus for multiplexing and demultiplexing multiple serial data streams provide double the data throughput on a single media channel, such as Fibre Channel (FC). A local clock provides both 0-degree phase and 180-degree phase signals of a clock signal at the same basic frequency as that of the incoming data, as well as a double-frequency clock signal. The first incoming data stream is routed to a first synchronizer unit, which receives a 0-degree phase signal of the local clock. The first synchronizer unit establishes and maintains synchronization of the first data stream with the 0-degree phase signal; it also tags the first data stream by replacing an original fill word with a special fill word. The second incoming data stream, on the other hand, is routed to a second synchronizer unit, which receives a 180-degree phase signal of the local clock. The second synchronizer unit establishes and maintains synchronization of the second data stream with the 180-degree phase signal.