Abstract: Some examples described herein provide an integrated circuit comprising an auxiliary clock and data recovery (CDR) circuitry. The CDR circuitry is configured to oversample an incoming data signal and generate a locked clock signal. The auxiliary CDR circuitry may comprise a phase-locked loop (PLL) configured to receive the incoming data signal and generate the locked clock signal. The PLL may comprise a phase detector (PD) configured to receive the incoming data signal and capture a number of samples of the incoming data signal in response to a number of adjacent clock signals and minimum data transition thresholds implemented by an intersymbol interference (ISI) filter, the minimum data transition thresholds identifying minimum data transitions in the incoming data signal.

Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

Abstract: Circuits, controllers, and techniques are provided for reducing non-linearities in a phase rotator. A circuit, according to one implementation, includes a single Phase-Locked Loop (PLL) circuit having a main path and a return path forming a feedback loop. The circuit also includes one or more phase rotators connected to an output of the single PLL circuit outside the feedback loop and one or more adaptable Look-Up Tables (LUTs) populated with operating code to be provided to the one or more phase rotators for defining operating characteristics of the one or more phase rotators. Furthermore, the circuit includes a control device configured to receive phase response characteristics from the one or more phase rotators. The control device is further configured to modify the operating code of the one or more adaptable LUTs based on the phase response characteristics to reduce non-linearities of the one or more phase rotators.

Abstract: A clock data recovery circuit includes a phase locked loop (PLL), a code signal generator, and a clock and data generator. The PLL generates a plurality of reference clock signals of which frequencies are modulated. Each of the plurality of reference clock signals has a first profile that is periodically fluctuated. The code signal generator generates a first compensation code signal. The first compensation code signal has a second profile that is periodically fluctuated and is different from the first profile. The clock and data generator generates a recovered data signal by sampling an input data signal based on a clock signal, compensates a frequency modulation on the plurality of reference clock signals based on the first compensation code signal, and includes a phase interpolator that generates the clock signal based on the plurality of reference clock signals and the first compensation code signal.

Abstract: The present disclosure relates to a data processing device, a data driving device, and a system for driving a display device, and more particularly, to a data processing device, a data driving device, and a system for speeding up data communication in a display device.

Abstract: A circuit has a driver circuit with a slew-rate controller, an output stage and a monitoring circuit. The output stage is connected to a first bus line and to a second bus line, and the driver circuit is designed to control the output stage on the basis of a first logic signal in such a manner that a corresponding bus voltage is produced between the first bus line and the second bus line. The slew-rate controller is coupled to the driver circuit and is designed to set a slew rate of the driver circuit on the basis of an input signal. The monitoring circuit is designed to generate the input signal for the slew-rate controller, wherein the input signal indicates a higher slew rate during an arbitration phase of a data frame contained in the first logic signal than during a data transmission phase of the data frame.

Abstract: A system and method for accurately determining a distance between two network devices using a Channel Sounding application is disclosed. The network devices each guarantee a fixed phase relationship between the transmit circuit and the receive circuit. In one embodiment, this is achieved by incorporating the divider within the phase locked loop. The divider may have a reset, such that it can be initialized to a predetermined state. Further, by utilizing a divider disposed within the phase locked loop with a reset, the quadrature signal generator is guaranteed to output clocks for the transmit circuit and the receive circuit that have a constant phase relationship.

Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.

Abstract: Embodiments of this application disclose example phase detection methods, phase detection circuits, and clock recovery apparatuses. One example method includes receiving a first signal and deciding a (2M?1) level of the first signal to obtain a decision result, where the first signal is a (2M?1)-level signal, and M is a positive integer. A response amplitude parameter of a transmission channel can then be obtained. Clock phase information in the first signal can then be extracted based on the first signal, the decision result, and the response amplitude parameter. Output clock phase information can then be determined based on at least three decision results and at least three pieces of clock phase information in at least three symbol periods.

Abstract: A temperature compensated, auto tunable, frequency locked loop oscillator includes, in one embodiment, an oscillator configured to generate a clock-signal with a frequency fclk based on a control voltage vc, and a frequency-to-voltage (f/v) converter coupled to the oscillator, which is configured to generate a first voltage vfb with a magnitude based on frequency fclk. A controller is also included and coupled between the oscillator and the f/v converter. The controller is configured to control the magnitude of the control voltage vc based on the first voltage vfb.

Abstract: A clock recovery circuit may include a first circuit to produce an output signal that is a logical combination of an edge detection signal and a clock signal. At least some transitions in the edge detection signal may correspond to transitions in a set of data signals. The clock recovery circuit may also include a second circuit to average the output signal to produce a voltage, and a third circuit to add a variable delay to the clock signal based on the voltage.

Abstract: In accordance with an embodiment, a method of operating a fractional-N phase locked loop (FN-PLL) includes: dividing a first clock signal using a multi-modulus divider (MMD) based on a modulus control signal to form a frequency-divided clock signal, where the first clock signal is based on an output clock of the PLL; generating the modulus control signal based on a divider control input value using a delta-sigma modulator (DSM); and when a fractional portion of the divider control input value is within a first range of values, and repeatedly removing a first number of clock cycles from the first clock signal before dividing the first clock signal using the MMD, where the first number of clock cycles is a non-integer number of clock cycles.

Abstract: A system comprises local oscillator spur suppression circuitry, local oscillator generator circuitry), and beamforming circuitry. The local oscillator spur suppression circuitry is operable to generate a phase adjustment value. The local oscillator generator circuitry is operable to generate a local oscillator signal at a determined phase equal to a reference phase offset by the phase adjustment value. The beamforming circuitry is operable to receive the phase adjustment value, and generate a beamforming coefficient to be applied to a signal that is to be upconverted by the local oscillator signal and transmitted via an antenna element of a phased array, wherein the generation of the beamforming coefficient is based on the phase adjustment value and a location of the antenna element within the phased array.

Abstract: Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

Abstract: In a wireless communication system including a plurality of wireless base stations, the wireless base stations other than the uppermost wireless base station among the plurality of wireless base stations each determine a frame timing on the basis of synchronization timing information received from the upper wireless base station, and the wireless base stations other than the lowermost wireless base station among the plurality of wireless base stations each notify the lower wireless base station of the synchronization timing information.

Abstract: A delay circuit includes a first delay line suitable for delaying a first clock by a delay value that is adjusted based on a delay control code; a delay control circuit suitable for comparing a phase of the first clock delayed through the first delay line with a phase of a second clock to generate the delay control code; and a second delay line having, based on a delay control code, a delay value corresponding to a half of the delay value of the first delay line.

Abstract: A device comprises a clock source configured to provide a spread-spectrum modulated clock signal and a control signal associated with the spread-spectrum modulated clock signal. The device also comprises a circuitry configured to receive the spread-spectrum modulated clock signal, to receive the control signal, and to sample a data signal in accordance with the spread-spectrum modulated clock signal and the control signal.

Abstract: A receiver (30) for providing an activation signal (54) to transition a device from a dormant state to an operative state. The receiver includes a sensor (32), a super regenerative oscillator, SRO, circuit (34), and a processing device (36, 38). The sensor is one of an optical sensor, an acoustic sensor, and a magnetic field sensor, and generates detector signals (40) based on wireless signals (28) received from an external source (18). The SRO circuit is electrically coupled to the sensor to receive the detector signals, and electrically oscillates with a constant SRO frequency and with a SRO amplitude (As) that changes when a carrier frequency of the detector signal substantially matches the SRO frequency. The processing device monitors the SRO amplitude in time, and generates the activation signal when a temporal characteristic (Sc) of the monitored SRO amplitude matches a predetermined reference pattern (52).

Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).

Abstract: A method determines a pin-to-pin delay between clock signals having integrally related frequencies. The method includes generating a delay code corresponding to a delay between a first signal edge of a first clock signal received by a first node of an integrated circuit and a second signal edge of a second clock signal received by a second node of the integrated circuit. The delay code is based on a first time code corresponding to the first signal edge, a second time code corresponding to the second signal edge, a first skew code, a second skew code, and a period of the first clock signal or the second clock signal. The first clock signal has a first frequency, the second clock signal has a second frequency, and the second frequency is integrally related to the first frequency.

Abstract: A physical layer transceiver for a serial data channel includes receiver circuitry having a local clock. Received signals arrive on the channel according to a remote clock. Clock-data recovery circuitry aligns the local clock with the remote clock by correcting phase and frequency error between the local and remote clocks. The clock-data recovery circuitry includes digital phase error detection circuitry operating according to a digital clock to detect phase error between the local and remote clocks, analog phase rotation circuitry to correct the detected phase error, distribution circuitry to divide the detected phase error into multiple phase error steps, and an analog clock source configured to provide the local clock to the analog phase rotation circuitry, and to provide to the distribution circuitry a distribution clock that is slower than the local clock, to correct the local clock by at least one step during one digital clock period.

Abstract: Computer readable media, methods, and apparatuses for location estimation using multi-user multiple-input multiple-output in a wireless local-area network are disclosed. An apparatus is disclosed comprising processing circuitry configure to: encode a fine timing measurement (FTM) initiate (FTI) frame, the FTI frame comprising M0 message uplink resource allocations for a plurality of responders to transmit M0 messages to the HE STA. The processing circuitry further configured to configure the HE STA to transmit the FTI frame to the plurality of responders, and decode M0 messages from the plurality of responders in accordance with the M0 message uplink resource allocations, where the M0 messages are to be received at the HE STA at times T2 in accordance with multi-user multiple-input multiple-output (MU-MIMO). The processing circuitry further configured to acknowledge the M0 messages to be transmitted at a time T3, and decode M1 messages comprising a corresponding time T1 and time T4.

Abstract: A signal is transmitted at a high speed in a direction opposite to a transmitting direction of a main large-capacity channel. A first transmitting unit transmits a first signal including a clock component to an external device through a transmission path as a differential signal. A second transmitting unit superimposes a second signal including a clock component on the transmission path as an in-phase signal to transmit to the external device. A state notifying unit communicates with the external device through a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device by a DC bias potential of at least one of the pair of differential transmission paths.

Abstract: Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.

Abstract: A locked-loop circuit includes phase synchronization circuitry to synchronize a DCO clock phase to a reference clock phase. Sampling circuitry sequentially samples the reference clock with each of N sampling clocks having offset phases, a first one of the N sampling clocks comprising a master sampling clock. Edge detection logic accumulates phase information from the multiple sampling clocks and determines, based on the accumulated phase information, whether any of the sampling clocks other than the master sampling clock correspond to edge detection signals that occurred early with respect to a rising edge of the master sampling clock. Index logic generates index values for any of the determined early edge detection signals. The index logic transfers the generated index values to a master phase transfer logic unit. Phase adjust logic adjusts the master clock phase based on a selected one of the generated index values.

Abstract: A wireless system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock. The LO signal generation circuit includes an active oscillator. The active oscillator generates the reference clock, wherein the active oscillator includes at least one active component, and does not include an electromechanical resonator. The RX circuit generates a down-converted RX signal by performing down-conversion upon an RX input signal according to the LO signal. The calibration circuit generates a frequency calibration control output according to a signal characteristic of the down-converted RX signal, and outputs the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.

Abstract: A clock recovery circuit a first phase-locked loop (PLL) circuit configured to perform a coarse phase fixing operation on a test data signal by using a first reference clock signal, the test data signal having a prescribed pattern, and a second PLL circuit configured to perform a fine phase fixing operation on the test data signal, subsequently to the coarse phase fixing operation. The second PLL circuit may be configured to perform the fine phase fixing operation on the test data signal by selectively using at least two selection reference clock signals among a plurality of second reference clock signals that are delayed from the first reference clock signal by a unit phase, in a training mode, having a phase difference of N times the unit phase, where N is an integer equal to or greater than 2.

Abstract: Described are apparatus and methods for low power clock generation in multi-channel high speed devices. In implementations, a multi-channel data processing device includes a low frequency clock generation and distribution circuit configured to generate and distribute a 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 8, and multiple data processing channels connected to the low frequency generation and distribution circuit. Each data processing channel including input ports associated with different operating frequency clocks, and a channel local clock generation circuit comprising multipliers associated with some of the input ports, each multiplier configured to multiply the FS/N frequency clock to locally generate an operating frequency clock associated with an input port of the input ports.

Abstract: In one embodiment, a phase lock loop circuit includes a control circuit, wherein the control circuit is configured to input an estimation having a second frequency and a second phase. The second frequency is selected from a range of frequencies including a first frequency from an acquired signal. A numerically controlled oscillator is coupled to the control circuit, wherein the control circuit is configured to control an output response of the numerically controlled oscillator. The numerically controlled oscillator is configured to receive the estimation from the control circuit and generate an output signal in response to the estimation. A phase detector is coupled to the control circuit and the numerically controlled oscillator, wherein the phase detector is configured to compare the first signal and the output signal and produce a comparison output, the comparison output indicative of a phase difference between the first signal and the estimation.

Abstract: According to an embodiment, a receiver is described comprising an input configured to receive a digital input signal and a digital filter configured to deliver a filtered digital output signal and to deliver stability information wherein the digital filter is configured to enter or stay in a transition state after a transition at the input signal, leave the transition state when the input signal is considered being stable, update the output signal when leaving the transition state and deliver the stability information indicating transitions at the input signal during transition state.

Abstract: A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data, packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

Abstract: A display system includes a number (M) of scan line units, a number (N) of channel line units, a number (R) of light emitting arrays connected to the scan line units and the channel line units, and a number (L) of shared driving circuits, where M?1, N?1, R?1, and L is equal to a maximum of M and N when M?N, and is equal to M otherwise. Each shared driving circuit is operable to generate or not to generate a scan driving output, and is operable to generate or not to generate a channel driving output. Each of a number (M) of the shared driving circuits is for providing the scan driving output to a respective scan line unit. Each of a number (N) of the shared driving circuits is for providing the scan driving output to a respective scan line unit.

Abstract: Techniques are described for accurate tracking of a radiofrequency (RF) carrier for amplitude-modulated signals in unstable reference clock environments. For example, some embodiments operate in context of clock circuits in devices configured for near-field communication (NFC) card emulation (CE) mode. The clock circuits seek to generate an internal clocking signal by tracking a clock reference, such as an RF carrier. In some cases, the clock reference can unpredictably become unreliable for periods of time, during which continued tracking of the unreliable clock reference can yield appreciable frequency and phase errors in the generated internal clocking signal. Embodiments implement phase delta detection with time limiting to limit the magnitude of such errors in the internal clocking signal introduced while tracking an unreliable clock reference.

Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

Abstract: A phase-locked loop (PLL) apparatus and a method for clock synchronization are disclosed. According to an embodiment, the PLL apparatus includes an adjustable oscillator, one or more first difference determiners, one or more first parameter determiners and a loop integrator. The adjustable oscillator can generate an oscillating signal based on a control signal. Each first difference determiner can receive a first clock reference signal and determine a phase difference between the received first clock reference signal and the oscillating signal. Each first parameter determiner can receive a phase difference from the one or more first difference determiners and generate a first control parameter based on a variation of the phase difference. The loop integrator can integrate the one or more first control parameters to generate the control signal for the adjustable oscillator.

Abstract: Clock and data recovery for high-speed serial data protocols is enabled using circuitry that combines the functionality of a decision feedback equalizer with that of a phase detector.

Abstract: A variable-frequency oscillator generates an oscillator clock having a frequency that corresponds to a control signal. A programmable frequency divider divides the oscillator clock, so as to generate a divided clock. A F/V converter circuit includes a capacitor and a switch that switches at a frequency that corresponds to the divided clock, and generates a detection voltage that corresponds to a reference current. A reference voltage source outputs a reference voltage that corresponds to the electric potential that occurs at the resistor due to a reference current. A feedback circuit adjusts a control signal such that the detection voltage approaches the reference voltage. A correction circuit changes the frequency-dividing ratio of the programmable frequency divider based on a modulation signal modulated according to a correction coefficient that corresponds to the temperature.

Abstract: Techniques are disclosed for performing time synchronization at a plurality of computing devices in a network. In one example, a method comprising obtaining time stamp data in accordance with a synchronization operation for a timing protocol; computing a skewness estimate and an offset estimate from the time stamp data by executing, over a number of iterations, a weighted regression analysis targeting at least one bound of the time stamp data, the skewness estimate comprising a frequency difference between a first clock at a first computing device and a second clock at a second computing device, the offset estimate comprising a clock time difference between the first clock and the second clock; and applying a clock time correction to the at least one of the first clock or the second clock based the offset estimate.

Abstract: According to one embodiment, there is provided a reception apparatus including a preamplifier and a clock recovery circuit. The preamplifier is configured to receive data through a wired transmission path. The clock recovery circuit is configured to sample a value during an edge period and a value during a data period, which are in data received from the preamplifier, by using a reference clock, to execute a phase adjustment to the reference clock with respect to a transition timing of a signal level of the data in a case sampling results is satisfied a particular condition concerning a transition of the signal level of the data, and to execute no phase adjustment to the reference clock with respect to the transition timing of the signal level of the data in a case the sampling results is not satisfied the particular condition.

Abstract: A semiconductor integrated circuit includes a first signal transmission path and a second signal transmission path in parallel with each other, a first variable delay circuit provided on the first signal transmission path and configured to cause a first signal to be delayed by a first delay amount, a duty adjustment circuit provided on the first signal transmission path in series with the first variable delay circuit, and a second variable delay circuit provided on the second signal transmission path and configured to cause a second signal to be delayed by a second delay amount. The first delay amount is smaller than the second delay amount by a third delay amount corresponding to an amount of delay applied to the first signal by the duty adjustment circuit.

Abstract: Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Abstract: Optical signal receivers and methods are provided that include multiple optical resonators, each of which receives a portion of an arriving optical signal. Various of the optical resonators are tuned or detuned from a carrier wavelength, and produce an intensity modulated output signal in response to modulation transitions in the arriving optical signal. A detector determines phase transitions in the arriving optical signal, by analyzing the intensity modulation output signals from the optical resonators, and distinguishes between differing phase transitions that result in a common final state of the arriving optical signal.

Abstract: An example apparatus (100) is for use for use with front-end circuitry (102) to transmit and receive radar wave signals, The apparatus (100) includes digital phase locked loop (PLL) circuitry (104) and a control circuit (106). The digital PLL circuitry (106) provides a chirp sequence with frequency modulated continuous wave signals (FMCW), the FMCW signals being chirps containing a start frequency and a stop frequency, representing a selected chirp bandwidth (BW). The digital PLL circuitry (104) includes the DCO circuit (108) which frequency resolution is configured and arranged to be tuned relative to the selected chirp BW, the frequency resolution configured in response to a selected level of capacitance. The control circuit (106) controls the selected level of capacitance used by the DCO circuit (108) by changing the frequency resolution of the DCO according to the selected chirp BW, wherein different frequency resolutions are used for a first selected chirp BW and for a second selected chirp BW.

Abstract: A signal processing method is described. The signal processing method comprises the following steps: An input signal is received. The input signal is processed from a start point to a preliminary stop point based on at least one first processing parameter, thereby obtaining a first processed signal. The at least one first processing parameter is adapted based on the first processed signal, thereby obtaining at least one second processing parameter. The input signal is processed from the preliminary stop point to the start point based on the at least one second processing parameter, thereby obtaining a second processed signal. At least one output parameter is generated and/or an output signal is synchronized with the input signal based on the second processed signal. Further, a signal analysis module is described.

Abstract: A multi-channel transmission device is provided. The multi-channel transmission device includes a clock generator and a plurality of transmitters. The clock generator generates input clocks. The transmitters operate based on spread spectrum clocks respectively. Each of the transmitters comprises a phase rotator. The phase rotator provides a selection signal and an interpolation signal of multiple bits. The phase rotator selects two of the input clocks as a first selected input clock and a second selected input clock according to the selection signal, and generate a spread spectrum clock according to the interpolation signal, the first selected input clock and the second selected input clock.

Abstract: A clock synthesizer has integrated voltage droop detection and clock stretching. An oscillator of the clock synthesizer receives a control current from a digital to analog converter and generates an oscillator output signal. A droop detector and clock stretching circuit responds to a voltage droop of a supply voltage supplying circuits coupled to the oscillator output signal, to cause a portion of the oscillator control current to be diverted from the oscillator to thereby cause the oscillator to reduce the first frequency. The diversion can be accomplished through shunt circuits or a current mirror circuit.

Abstract: Provided is a passive charge recovery logic circuit that includes an electromagnetic field capturing device that harvests ambient electromagnetic energy, with the device including a first end and a second end; a first phase shifter including a first end connected to the first end of the device; a second phase shifter including a first end connected to the second end of the device; a peak detector including a first end connected to the first end of the device; and at least four gates that operate by respective first to fourth power clock signals.

Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.