Abstract: Aspects of a method and system for bandwidth calibration for a phase locked loop are presented. Aspects of the method may include generating one or more carrier signals based on one or more corresponding calibration signals. A pre-distortion function may be computed based on the generated one or more carrier signals for the phase locked loop circuit. An output radio frequency (RF) synthesized signal generated by the phase locked loop circuit may be modified based on the computed pre-distortion function and a subsequent output RF synthesized signal generated based on the modified output RF synthesized signal.

Abstract: The present invention discloses a frequency synthesizer which includes: a PLL including an oscillator for generating an oscillator signal and a first frequency divider for dividing a frequency of the oscillator signal to generate a first frequency-divided signal; a switching unit for switching the PLL to either an open loop status or a closed loop status; a second frequency divider, for dividing a frequency of a reference clock to generate a second frequency-divided signal; a counter, for counting according to the first frequency-divided signal and the second frequency-divided signal to generate a counter value when the PLL is in the open loop status; a comparator, for comparing the counter value with a predetermined value to generate a comparing result; and a determining unit, for adjusting an oscillator frequency of the oscillator according to the comparing result.

Abstract: A receiving circuit which receives serial data, includes: a voltage controlled oscillator which generates a sampling clock signal having a frequency based on an input control voltage; a first frequency divider which divides the frequency of the sampling clock signal at a division rate M; a second frequency divider which divides a frequency of a clock signal based on the received serial data at a division rate N, N being a real number represented by M×q/p; a frequency comparator which generates a phase/frequency difference signal based on a phase difference between an output signal of the first frequency divider and an output signal of the second frequency divider; and a control voltage generating circuit which generates the control voltage to control a frequency of the voltage controlled oscillator based on the phase/frequency difference signal.

Abstract: In a method of recovering timing information over packet networks, raw network delays are measured using timing packets sent between a transmitter and receiver. The expected delay is predicted using a minimum statistics adaptive filter to track local minima of measured time delays over a smoothing window. Only those incoming timing packets which meet a particular criterion relative to the expected delay within a smoothing window are selected, and a local clock is adjusted based on the measured timing delays from the selected timing packets.

Abstract: Systems and methods for measuring the level of a plurality of phases of a conductive or semi-conductive mixture in a vessel. The systems and method include a vessel configured to hold the mixture, a plurality of antennas configured to transmit electromagnetic and/or eddy current signals into the mixture to impinge upon the plurality of phases and to receive corresponding signals reflected from the plurality of phases, a transmitter module configured to generate electromagnetic and/or eddy current signals in communication with the plurality of antennas, a receiver module configured to receive electromagnetic and/or eddy current signals in communication with the plurality of antennas, a control module in communication with the transmitter module and the receiver module configured to control their operation, and a signal analysis module in communication with the receiver module configured to process the reflected signals to determine the levels of the plurality of phases within the vessel.

Abstract: A television broadcast receiving apparatus can change an oscillation frequency of a local oscillation signal or a tuning frequency of an intermediate frequency signal in a reception channel, and changes the reception characteristic to an optimum reception characteristic. In this way, the television broadcast receiving apparatus effectively reduces SN ratio deterioration due to interference of the outside of a reception band such as adjacent channel interference.

Abstract: A communications subsystem for a wireless device for correcting errors in a reference frequency signal. The communications subsystem comprises a frequency generator for generating the reference frequency signal and a closed loop reference frequency correction module that generates a reference frequency adjustment signal for correcting the reference frequency signal when the communications subsystem operates in closed loop mode. The subsystem further includes an open loop frequency correction means that that samples values of the reference frequency adjustment signal during the closed loop mode and generates a frequency correction signal for correcting the reference frequency signal when the communications subsystem operates in a mode other than closed loop mode.

Abstract: One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.

Abstract: A frequency signal generator includes a controller for generating a frequency generation signal, a reference frequency signal generator for generating a first frequency signal and generate a second frequency signal by dividing a first frequency signal from the controller, an assistance frequency signal generator adapted to generate a third, fourth, and fifth frequency signals and to output a sixth frequency signal in response to an assistance frequency select signal, a mixer for selecting a sign of the sixth frequency signal in response to a sign select signal and generating a seventh frequency signal and a eighth frequency signal by mixing the sixth frequency signal of the selected sign and the first frequency signal, a switch adapted to output the seventh or eighth frequency signal in response to a dividing select signal, and a first divider outputting a ninth frequency signal by dividing the eighth frequency signal from the switch.

Abstract: A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and also used internally as feedback. Based on the clock output, the window comparator circuit collapses the thresholds while sampling input Bipolar return to zero data.

Abstract: A communication system includes master host unit, hybrid expansion unit, and remote antenna unit. Master host unit communicates analog signals with service provider interfaces. Master host unit and hybrid expansion unit communicate N-bit words of digitized spectrum over communication link. Hybrid expansion unit converts between N-bit words and analog spectrum. Hybrid expansion unit and remote antenna unit communicate analog spectrum over analog communication medium. Remote antenna unit transmits and receives wireless signals over air interfaces. Master host unit includes master clock distribution unit that generates digital master reference clock signal. Master host unit communicates digital master reference clock signal over communication link. Hybrid expansion unit receives digital master reference clock signal from master host unit over communication link and generates analog reference clock signal based on digital master reference clock signal.

Abstract: A clock and data recovery circuit injects a noise waveform into the control loop to offset the data sampling point artificially in order to induce errors. The amplitude of the injected waveform can be varied to ascertain the effect on the bit error rate (BER) so as to be able to evaluate the temporal noise margin.

Abstract: A radio apparatus includes: first and second reception units to receive first and second signals from first and second radio apparatus controllers, respectively; first and second synchronous clock generation units to generate first and second recovery clocks from clock components included in the first and second signals received by the reception units, respectively; a clock synchronization detection unit to detect whether or not the second recovery clock is synchronous with the first recovery clock; a code selection unit to select a code indicating the synchronous state according to a detection result of the synchronization detection unit; a signal processing unit of generate a third signal to which the code selected by the code selection unit is added and which is synchronous with the first recovery clock; and a transmission unit to transmit the third signal generated by the signal processing unit to the second radio apparatus controller.

Abstract: A digital linear transmitter for digital to analog conversion of a radio frequency signal. The transmitter includes a delta sigma (??) digital to analog converter (DAC) and a weighted signal digital to analog converter in the transmit path of a wireless device to reduce reliance on relatively large analog components. The ?? DAC converts the lowest significant bits of the oversampled signal while the weighted signal digital to analog converter converts the highest significant bits of the oversampled signal. The transmitter core includes components for providing an oversampled modulated digital signal which is then subjected to first order filtering of the oversampled signal prior to generating a corresponding analog signal. The apparatus and method reduces analog components and increases digital components in transmitter core architecture of wireless RF devices.

Abstract: A phase detection and decision feedback equalization circuit is provided. A first latch and a second latch are coupled to an input of the circuit. A third latch and a fourth latch are respectively coupled in series to outputs of the first latch and second latch. The first and fourth latches are enabled by a clock signal, and the second and third latches are enabled by a complement of the clock signal. A first feedback circuit is configured to provide a signal output from the first latch and a first feedback signal derived from the output of the fourth latch to an input of the third latch. A second feedback circuit is configured to provide a signal output from the second latch and a second feedback signal derived from the output of the third latch to an input of the fourth latch.

Abstract: A serializer is equipped with a plurality of input terminals into which a plurality of binary signals are input in parallel, and converts the plurality of input binary signals into serial binary signals and transmits the serial binary signals to an optical transmission module. One input terminal out of the plurality of input terminals is assigned as an input terminal for preventing bit continuation by inserting “1” signals or “0” signals into the serial binary signals so that a predetermined number of bits of the same value may not be inserted continuously. Due to this structure, bit continuation can be prevented even for a signal generating source with no coding function by a simple configuration without increasing cost and size.

Abstract: A communication system includes: a transmitter adapted to transmit a synchronizing clock and serial data synchronous with the synchronizing clock over a line at low amplitude; and a receiver adapted to receive the serial data and synchronizing clock from the transmitter. The receiver includes an amplifier adapted to amplify the received synchronizing clock of low amplitude to restore the clock to its original amplitude, a latched comparator adapted to latch the received serial data in synchronism with a reproduction clock, and a phase-locked circuit.

Abstract: A wireless apparatus includes a clock generation PLL circuit of a digital baseband section. A variable output regulator receives as an input a VCO control voltage for controlling an oscillation frequency of a VCO in the PLL circuit, varies an output voltage in accordance with the VCO control voltage, and supplies, as a supply voltage, the output voltage to a power terminal of a high frequency circuit, such as an amplifier. The VCO control voltage changes in accordance with temperature or process variations, and the supply voltage of the high frequency circuit is controlled in accordance with the VCO control voltage. For this reason, performance deterioration ascribable to the temperature or process variations can be compensated for.

Abstract: The frequency calibration device includes a logic unit for gating the clock signal according to a gating window signal to generate a gated clock signal, and a divider for dividing the gated clock signal by a divisor in frequency to generate a frequency indication signal, and output digits of the divider are set to the divisor in a calibration cycle, and the frequency indication signal is a most significant bit of the output digits.

Abstract: A digital-to-time converter for generating a first and a second output signal separated by a predetermined delay includes first and second periodic signal generators, respectively, generating a first and a second periodic signal, a periodic signal synchronizer detecting a phase difference between the first and the second periodic signals, and first and second output pulse generators, respectively, starting a count of the first and the second periodic signals when a phase of the first periodic signal coincides with a phase of the second periodic signal. When a first value is counted, the first output pulse generator outputs a pulse as the first output signal, and when a second value is counted, the second output pulse generator outputs a pulse as the second output signal.

Abstract: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

Abstract: A transmitter includes a resistor, a protection unit, and a transmission unit. The resistor control unit controls a connection of a termination resistor between first and second transmission lines. The protection unit reduces first and second voltages, respectively, from the first and second transmission lines during a power-down mode. The transmission unit receives the dropped first and second voltages during the power-down mode and transmits first and second signals through the protection unit during a power-on mode. The resistor control unit connects the termination resistor to the first and second transmission lines when a transmission rate of the first and second signals is equal to or greater than a predetermined value. The resistor control unit is disconnected from at least one of the first and second transmission lines when the transmission rate is less than the predetermined value.

Abstract: A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.

Abstract: A multi-channel regulator system includes serially connected PWM integrated circuits, each of which determines a PWM signal for a respective channel to operate therewith, and individually controls its operation mode according to whether or not an external clock is detected. Therefore, each channel will not be limited to operate under a constant mode and could become a master channel or a slave channel. Additionally, each of the PWM integrated circuits generates a phase shifted synchronous clock for its next channel during it is enabled, and thus all the channels operate in a synchronous but phase interleaving manner.

Abstract: A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.

Abstract: A system and method for processing an analog signal output by a sensor. The system and method converting, using at least one analog-to-digital converter (ADC), the analog output signal to a digital signal, the digital signal including a plurality of samples at a predetermined resolution, detecting whether a trigger condition is met by analyzing the digital signal, detecting an event based on trigger information from the detecting whether a trigger condition is met, generating event information having time information included therein when the event is detected, defining one or more time windows based on the time information included in the event information, performing decimation on the digital signal based on the defined one or more time windows to generate a decimated signal, and outputting the decimated signal.

Abstract: A source device counts a clock CLKpixel for pixel data using a transmitting counter, adds a counted value Csource(t) of the transmitting counter at a timing of transmitting a video packet Pvideo to the sink device to a header part of the video packet Pvideo as a time stamp value Csource(t), and transmits the video packet Pvideo to the sink device. The sink device receives the video packet Pvideo, extracts the time stamp value Csource(t) from the header part of the video packet Pvideo, generates a fixed reference clock CLKref based on the counted value Csource(t) of the transmitting counter using a first PLL, circuit, and generates the clock CLKpixel for the pixel data of the source device based on the reference clock CLKref using a second PLL circuit.

Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Abstract: Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include adjusting the free-running oscillator to prevent the oscillation frequency from drifting so that the spurs are eliminated. Performance data generated when the communications device engages a communications channel that is known not to generate spurs is compared to performance data generated when the communications device engages a desired communications channel. The free-running oscillator is adjusted until the two types of performance data are matched. Other methods include adjusting the dithering module of the PLL to prevent the oscillation frequency from drifting so that the spurs are eliminated.

Abstract: A method and apparatus for generating a carrier frequency signal is disclosed. The method includes generating a first frequency signal; injecting a modulation signal at a first point of the two-point modulation architecture; generating a second frequency signal from the modulation signal; introducing the second frequency signal by mixing the first frequency signal and the second frequency signal to generate a mixed frequency signal and outputting the carrier frequency signal selected from the mixed frequency signal.

Abstract: Apparatus for efficient time slicing including a phase lock loop circuit having a voltage controlled oscillator, an auto-frequency calibration circuit coupled with the phase lock loop circuit configured to output a value to select a range of the voltage controlled oscillator, and a burst mode detector connected with the auto-frequency calibration circuit. The burst mode detector having a register adapted to store the output of the auto-frequency calibration circuit.

Abstract: A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal.

Abstract: Exemplary embodiments are directed to data and clock recovery in NFC transceivers. A transceiver may include a phase-locked loop configured to recover a clock from a received input signal in a first mode and enable for oversampling of an output signal in a second, different mode.

Abstract: A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.

Abstract: A clock data recovery circuit includes a receiving circuit that takes in input data based on a sampling clock, a demultiplexer that converts serial data output from the receiving circuit into parallel data, a clock/data recovery part that detects phase information from the parallel data output from the demultiplexer and generates the sampling clock by adjusting the phase of a reference clock based on the phase information, a data pattern analyzer that carries out frequency analysis of the parallel data output from the demultiplexer, and an aliasing detector that detects a clock recovery state based on the analysis result of the frequency of the parallel data.

Abstract: A spread spectrum clock generator includes a triangular modulator, a delta sigma modulator, a frequency divider, and a phase lock loop. The triangular modulator generates a digital modulation signal, representing a decimal, according to a digital parallel signal, in which the spread amount is in proportion to the digital parallel signal. The delta sigma modulator, electrically connected to the triangular modulator, generates a divider divisor, including the decimal and an integer, according to the digital modulation signal. The frequency divider divides the frequency of the output signal clock according to the divider divisor to generate a divided clock signal, in which the frequency of the divided clock signal is substantially equal to a quotient result from dividing the frequency of the output clock signal with the divider divisor. The phase lock loop adjusts the frequency of the output clock signal according to the divided clock signal and a reference clock signal.

Abstract: In an embodiment, a circuit includes a buffer circuit including a buffer input and an output terminal and a latency locked loop (LLL) circuit. The LLL circuit includes a signal input for receiving an input signal, a feedback input coupled to the output terminal, and a signal output coupled to the buffer input. The LLL circuit is configured to control a propagation delay between the signal input and the signal output to produce a substantially constant total delay from the signal input to the output terminal.

Abstract: Systems and methods to achieve a digital audio interface having automatic rate detection and tracking of digital audio streams have been achieved. The system comprises a digital controller working in conjunction with an analog phase-locked loop (PLL). It removes the need to know or communicate in advance the rate at which the interface will be operating, so allowing asynchronous switching between different audio streams. The digital controller acts as a phase-lock loop by modifying the feedback divide ratio of the PLL in order to minimize the phase error between the device clock and an arbitrary audio interface clock.

Abstract: A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a Digitally Controlled Oscillator (DCO) output signal and a reference clock and outputs a first stream of digital values. The TDC is clocked at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate.

Abstract: A lock detection circuit and method are disclosed for phase locked loop (PLL) systems. The lock detection circuit primarily includes a delay unit and an asserting logic unit. The delay unit receives the phase error signal of the PLL and produces a present phase error signal, and then accordingly generates at least one delayed phase error signal. The asserting logic unit generates an unlock indicating signal (UNLOCK) according to the present phase error signal and the delayed phase error signal. A phase lock indicating signal will be asserted if the unlock indicating signal is not asserted within a predetermined number of counting pulses.

Abstract: Techniques for frequency synthesis using upconversion PLL processes are described herein.

Abstract: A system recovers a local media clock from a master media clock based on time-stamped packets received from a transmitter. The packets may include audio, video, or a combination of both, sampled at a rate determined by the master media clock at the transmitter. Timestamps in the packets may be based on values of a remote real-time counter at the transmitter that is synchronized with a local real-time counter at a receiver. The local media clock may be syntonized with the master media clock through the clock periods. The clocks may be synchronized by syntonizing the clocks and adjusting the phase of the local media clocks based on timestamps and a real-time counter.

Abstract: A digital waveform synthesizer (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesizer (10) which produces a synthesized output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5).

Abstract: A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

Abstract: A system and method for generating a spread spectrum clock signal with a constant ppm offset as a function of a repetition number. A phase interpolator can be configured in association with of a phase-locked loop circuit in order to provide a phase movement from a bit clock generated by the PLL circuit. A repetition number divider computes the repetition number for each time slot in a piece-wise SSC modulation profile. A noise shaping modulator can be employed for modulating a fractional part associated with the repetition number. A repetition counter and a phase accumulator receives an integer part of the repetition number and counts unit interval clock periods equal to a sum of integer and the sigma-delta modulated fractional parts of the repetition number. The phase accumulator can be incremented and/or decremented based on the sign of the spread spectrum direction.

Abstract: A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up.

Abstract: A radio communication device in which the waste of physical resources involved in the repetition transmission of a response signal can be minimized with no restriction on the scheduling of a base station imposed or with the restriction on the scheduling thereof minimized. In this device, a control unit (209) selects the ZAC sequence of the cyclic shift amount corresponding to a PUCCH number inputted from a determination section (208) from among ZAC#0 to ZAC#11 to set it to a spreading section (215) and selects the block-wise spreading code sequence corresponding to the PUCCH number inputted from the determination section (208) from BW#0 to BW#2 to set it to a spreading section (218). More specifically, the control unit (209) selects any of the resources defined by the ZAC#0 to ZAC#11 and the BW#0 to BW#2. As a result, the more the number of transmissions of the response signal, the less the number of resources the control unit (209) can select.

Abstract: Aspects of the disclosure provide a phase-locked loop (PLL). The PLL includes a voltage-controlled oscillator (VCO), a detector module, and a ramp module. The VCO has a first capacitor unit and a second capacitor unit. The VCO is configured to generate an oscillating signal having a frequency based on a first capacitance of the first capacitor unit and a second capacitance of the second capacitor unit. The detector module is configured to generate a voltage signal as a function of the oscillating signal and a reference signal. The voltage signal is used to control the first capacitor unit to stabilize the frequency of the oscillating signal. The ramp module is configured to generate a ramp signal based on the voltage signal. The ramp signal is used to control the second capacitor unit to ramp the second capacitance from a first value to a second value.

Abstract: Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.

Abstract: The spread spectrum clock generator (SSCG) includes a phase comparator detecting phase difference between input clock and feedback clock; a charge pump supplying current depending on the phase difference; a loop filter converting the current to smoothed voltage; a voltage controlled oscillator generating a spread spectrum clock signal depending on the smoothed voltage; and a modulation signal generator generating modulation signal having amplitude depending on a modulation width set value. The SSCG further includes a modulation width detector detecting modulation width of the spread spectrum clock signal while comparing the modulation width with a modulation width target value to update the modulation width set value to narrow difference between the detected modulation width and the modulation width target value, followed by feeding back the updated modulation width set value to the modulation signal generator.