Pattern Mask Patents (Class 378/35)
  • Patent number: 10895805
    Abstract: A method for producing a pellicle according to the one embodiment of the present invention produces a pellicle including a pellicle film and a pellicle frame supporting an outer peripheral portion of the pellicle film. The method includes forming the pellicle film on a substrate, and bonding a pressure-sensitive adhesive sheet, that is elastic and has a pressure-sensitive adhesive force thereof decreased upon receipt of external stimulation, to each of two surfaces of the substrate; making a notch inside a part of the substrate, the part having the pressure-sensitive adhesive sheets bonded thereto; separating a substrate outer peripheral portion outer to the notch of the substrate, in a state where the pressure-sensitive adhesive sheets are bonded to the substrate, to form a pellicle frame; and stimulating the pressure-sensitive adhesive sheets to peel off the pressure-sensitive adhesive sheets.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: January 19, 2021
    Assignees: MITSUI CHEMICALS, INC., TAZMO CO., LTD.
    Inventors: Kazuo Kohmura, Daiki Taneichi, Yosuke Ono, Hisako Ishikawa, Tsuneaki Biyajima, Yasuyuki Sato, Toshiaki Hirota
  • Patent number: 10866197
    Abstract: Methods and systems for photomask defect dispositioning are provided. One method includes directing energy to a photomask and detecting energy from the photomask. The photomask is configured for use at one or more extreme ultraviolet wavelengths of light. The method also includes detecting defects on the photomask based on the detected energy. In addition, the method includes generating charged particle beam images of the photomask at locations of the detected defects. The method further includes dispositioning the detected defects based on the charged particle beam images generated for the detected defects.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 15, 2020
    Assignee: KLA Corp.
    Inventors: Vikram Tolani, Masaki Satake, Weston L. Sousa
  • Patent number: 10662526
    Abstract: A method is provided, including the following operations: simultaneously applying an organosilyl chloride inhibitor and a Lewis base to a surface of a substrate, the organosilyl chloride inhibitor being configured to adsorb onto dielectric regions of the surface of the substrate; performing a plurality of cycles of an ALD process to deposit a metal oxide onto the surface of the substrate; wherein the applying of the organosilyl chloride inhibitor and the Lewis base prevents the ALD process from depositing the metal oxide onto the dielectric regions of the surface of the substrate.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: May 26, 2020
    Assignee: Lam Research Corporation
    Inventors: Dennis Hausmann, Alexander R. Fox, Paul C. Lemaire, David Charles Smith
  • Patent number: 10494713
    Abstract: In a method of forming a diamond film, diamond substrate, or diamond window, a silicon substrate is provided and the diamond film, diamond substrate, or diamond window is CVD grown on a surface of the silicon substrate. The grown diamond film, diamond substrate, or diamond window has an aspect ratio ?100, wherein the aspect ratio is a ratio of a largest dimension of the diamond film, diamond substrate, or diamond window divided by a thickness of the diamond film, diamond substrate, or diamond window. The silicon substrate has a thickness greater than or equal to 2 mm. The silicon substrate can optionally be removed or separated from the grown diamond film, diamond substrate, or diamond window.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: December 3, 2019
    Assignee: II-VI Incorporated
    Inventors: Wen-Qing Xu, Thomas E. Anderson, Giovanni Barbarossa, Elgin E. Eissler, Chao Liu, Charles D. Tanner
  • Patent number: 10483079
    Abstract: For manufacturing a radiation window for an X-ray measurement apparatus, an etch stop layer is first produced on a polished surface of a carrier. A thin film deposition technique is used to produce a boron carbide layer on an opposite side of the etch stop layer than the carrier. The combined structure including the carrier, the etch stop layer, and the boron carbide layer is attached to a region around an opening in a support structure with the boron carbide layer facing the support structure. The middle area of carrier is etched away, leaving an additional support structure.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: November 19, 2019
    Assignee: HS FOILS OY
    Inventors: Pekka Torma, Heikki Johannes Sipila
  • Patent number: 10387602
    Abstract: A method for generating masks for manufacturing of a semiconductor structure comprises the following steps. A design pattern for features to be formed on a substrate is divided into a first set of patterns and a second set of patterns. The first set of patterns comprises a first pattern corresponding to a first feature, the second set of patterns comprises two second patterns corresponding to two second features, and the first feature will be arranged between the two second features when the features are formed on a substrate. Two assist feature patterns are added into the first set of patterns. The two assist feature patterns are arranged in locations corresponding to the two second features, respectively. A first mask is generated based on the first set of patterns with the assist feature patterns. A second mask is generated based on the second set of patterns.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: August 20, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yeh Wu, Chia-Wei Huang, Yung-Feng Cheng
  • Patent number: 10350843
    Abstract: The present invention relates to an element comprising a surface area with a specific, optically effective surface relief microstructure (12). The surface relief microstructure has a surface modulation of top regions (13) and bottom regions (14), wherein in a first lateral direction of the surface area there is in average at least one transition from a top to a bottom region or vice versa within every 20 micrometer, and in a second lateral direction of the mask, which is perpendicular to the first direction, there is in average at least one transition from a first to a second zone or vice versa within every 200 micrometer. In the microstructure, (i) in the first direction the lateral arrangement of the transitions is non-periodic, and (ii) the top regions substantially lie in the same top relief plateau (15) and the bottom regions substantially lie in the same bottom relief plateau (16).
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: July 16, 2019
    Assignee: ROLIC AG
    Inventor: Martin Stalder
  • Patent number: 10061301
    Abstract: A method of generating a tool path for an additive manufacturing process, the tool path having an input polygon for a thick region, and an input path for a wire region. The method includes offsetting the input polygon by a minimum step over distance, creating a set of contour parallel offset lines, computing path segments from a medial axis transform of the input polygon, computing a dilation of the medial axis path by a radius approximately half the step over distance, producing a dilated medial axis, clipping the contour parallel offset paths by the medial axis path, producing, and recursively connect the medial axis paths with the clipped contour parallel paths.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 28, 2018
    Assignee: Palo Alto Research Center Incorporated
    Inventor: Gregory Burton
  • Patent number: 10025198
    Abstract: The present invention generally relates to simulating a lithographic process, and more particularly to methods for smart selection and smart weighting when selecting parameters and/or kernels used in aerial image computation. According to one aspect, advantages in simulation throughput and/or accuracy can be achieved by selecting TCC kernels more intelligently, allowing highly accurate aerial images to be simulated using a relatively fewer number of TCC kernels than in the state of the art. In other words, the present invention allows for aerial images to be simulated with the same or better accuracy using much less simulation throughput than required in the prior art, all else being equal.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: July 17, 2018
    Assignee: ASML Netherlands B.V.
    Inventors: Yu Cao, Wenjin Shao, Hanying Feng, Fei Du, Martin Snajdr
  • Patent number: 9979648
    Abstract: Entropy in routing tables may be increase to perform packet forwarding. Hash tables that store forwarding routes may be divided into multiple hash table segments. Forwarding routes may be stored across the hash table segments in different route segments. When looking up route segments to identify a forwarding route for a destination address of a network packet, digest values generated for previous route segments may be used to determine hash key values to identify hash table entries in a different hash table segment. The forwarding route may be identified according to the hash table entries located based on the digest values for previous route segments.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 22, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Bijendra Singh, Kari Ann O'Brien
  • Patent number: 9910348
    Abstract: A method of mask correction where two independent process models are analyzed and co-optimized simultaneously. In the method, a first lithographic process model simulation is run on a computer system that results in generating a first mask size in a first process window. Simultaneously, a second hard mask open etch process model simulation is run resulting in generating a second mask size in a second process window. Each first lithographic process model and second hard mask open etch process model simulations are analyzed in a single iterative loop and a common process window (PW) optimized between lithography and etch is obtained such that said first mask size and second mask size are centered between said common PW. Further, an etch model form is generated that accounts for differences in an etched pattern due to variation in three-dimensional photoresist profile, the model form including both optical and density terms that directly relate to an optical image.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: March 6, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Geng Han, Scott M. Mansfield, Dominique Nguyen-Ngoc, Donald J. Samuels, Ramya Viswanathan
  • Patent number: 9815139
    Abstract: A method for processing a part (10) with an energy beam A mask (70, 80) is arranged between a source of the energy beam and the part. The mask is configured with a beam-transmissive portion (71) in correspondence with mutually opposed portions (12, 14) of the part. Simultaneously heating the mutually opposed portions of the part is performed with energy beamlets passing through the beam-transmissive portions of the mask This simultaneous heating is configured to keep a thermally-induced distortion of the part within a predefined tolerance. Scanning of the mask with the energy beam may be performed without precisely tracking the mutually opposed portions of the part, thereby avoiding a need for complicated numerical programming for tracking a relatively complex geometry defined by the mutually opposed portions of the part.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: November 14, 2017
    Assignee: Siemens Energy, Inc.
    Inventors: Gerald J. Bruck, Ahmed Kamel
  • Patent number: 9799495
    Abstract: A plasma processing apparatus that performs plasma processing on a substrate held on a transport carrier including an annular frame and a holding sheet. The apparatus includes a process chamber; a process gas supply unit that supplies process gas to the process chamber; a decompressing mechanism that decompresses the process chamber; a plasma excitation device that generates plasma in the process chamber; a stage in the chamber, on which the transport carrier is loaded; a cooling mechanism for cooling the stage; a cover that partly covers the holding sheet and the frame and that has a window section through which the substrate is partly exposed to plasma; a correction member that presses the frame onto the stage and corrects warpage of the frame; and a movement device that moves the correction member. The correction member is provided separately from the cover to be covered by the cover.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: October 24, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Bunji Miizuno, Tomohiro Okumura
  • Patent number: 9791771
    Abstract: Disclosed are a repairable photomask structure and extreme ultraviolet (EUV) photolithography methods. The structure includes a multilayer stack, a protective layer above the stack and a light absorber layer above the protective layer. The stack includes alternating layers of high and low atomic number materials and a selected one of the high atomic number material layers is different from the others such that it functions as an etch stop layer. This configuration allows the photomask structure to be repaired if/when defects are detected near exposed surfaces of the multilayer stack following light absorber layer patterning. For example, when a defect is detected near an exposed surface of the stack in a specific opening in the light absorber layer, the opening can be selectively extended down to the etch stop layer or all the openings can be extended down to the etch stop layer in order to remove that defect.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Zhengqing John Qi, Jed H. Rankin
  • Patent number: 9778577
    Abstract: A testing structure of a strip width of a scribing slot is provided, the structure includes a first isolated line (232) and a second isolated line (234) which are perpendicular to each other, the testing structure further includes a first field region pattern (220), the first field region pattern (220) includes two graphics, the two graphics are each located on one side of the first isolated line (232) and opposite to each other. A testing method of a strip width of a scribing slot is also disclosed.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: October 3, 2017
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Wei Huang
  • Patent number: 9589794
    Abstract: A hot wire device and method for depositing semiconductor material onto a substrate in a deposition chamber in which the ends of at least two filaments are clamped into a filament holder and heated by supplying current, wherein a voltage for generating an electrical current is applied in temporal succession to filaments made of differing materials so that a number of differing semiconductors corresponding to the number of consecutively heated filament materials can be consecutively deposited onto the substrate without opening the chamber.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: March 7, 2017
    Assignee: Forschungszentrum Juelich GmbH
    Inventors: Friedhelm Finger, Andreas Schmalen, Johannes Wolff
  • Patent number: 9523926
    Abstract: The exposure apparatus of the present invention has an original holding unit including a holding frame that holds an original M by attracting the outer peripheral portion thereof and a drive unit that is capable of moving the holding frame while changing an irradiation area of the light to be irradiated on a pattern. Here, the holding frame has a penetrating portion, which is capable of flowing gas which is present in a space defined by the original and the holding frame into and out from the space, provided at both front and back lateral sides of the holding frame in the direction of movement thereof, and the penetrating portion has a shape or a configuration such that the pressure loss in the flow of the gas in a first direction is less than the pressure loss in the flow of the gas in a second direction.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: December 20, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Atsushi Umemura, Noriyasu Hasegawa
  • Patent number: 9437481
    Abstract: One method includes forming a mandrel element above a hard mask layer, forming first and second spacers on the mandrel element, removing the mandrel element, a first opening being defined between the first and second spacers and exposing a portion of the hard mask layer and having a longitudinal axis extending in a first direction, forming a block mask covering a middle portion of the first opening, the block mask having a longitudinal axis extending in a second direction different than the first direction, etching the hard mask layer in the presence of the block mask and the first and second spacers to define aligned first and second line segment openings in the hard mask layer extending in the first direction, etching recesses in a dielectric layer disposed beneath the hard mask layer based on the first and second line segment openings, and filling the recesses with a conductive material.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Jia Zeng, Youngtag Woo, Jongwook Kye
  • Patent number: 9323881
    Abstract: An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: April 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Jen Tseng, Ting-Wei Chiang, Wei-Yu Chen, Ruei-Wun Sun, Hung-Jung Tseng, Shun Li Chen, Li-Chun Tien
  • Patent number: 9316622
    Abstract: A vibration sensor includes a probe body with a vibration isolator operatively connected to the probe body for isolation of the probe body from vibrations of a structure to be monitored for vibration. A waveguide is operatively connected to the probe body to convey microwaves to and from a surface for sensing vibration of the structure to be monitored for vibration.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: April 19, 2016
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Peter L. Jalbert, Gary M. McBrien
  • Patent number: 9311442
    Abstract: Various embodiments include computer-implemented methods, computer program products and systems for verifying an integrated circuit (IC) layout. In some cases, approaches include a computer-implemented method of verifying an IC layout, the method including: obtaining data about a process variation band for at least one physical feature in the IC layout; determining voltage-based process variation band thresholds for the at least one physical feature in the IC layout; determining whether the process variation band for the at least one physical feature in the IC layout meets design specifications for the IC layout based upon the voltage-based process variation band thresholds for the at least one physical feature in the IC layout; and modifying the IC layout in response to a determination that the process variation band for the at least one physical feature does not meet the design specifications.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: April 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shayak Banerjee, James A. Culp, Ian P. Stobert
  • Patent number: 9152036
    Abstract: An X-ray mask structure includes a unibody support substrate having at least one thinned portion surrounded by a wall portion, a top layer disposed on the at least one thinned portion of the support substrate, and a plurality of X-ray absorber patterns disposed on the top layer over the at least one thinned portion. The top layer and the at least one thinned portion form a laminated membrane, wherein the at least one thinned portion and the wall portion provide mechanical support for the top layer, and the laminated membrane provides mechanical support for the plurality of X-ray absorber patterns.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 6, 2015
    Assignee: NATIONAL SYNCHROTRON RADIATION RESEARCH CENTER
    Inventor: Bor Yuan Shew
  • Patent number: 9128383
    Abstract: Photolithographic apparatus, systems, and methods that make use of sub-resolution assist devices are disclosed. In the various embodiments, an imaging mask includes an optically transmissive substrate having a sub-resolution assist device that further includes a first optical attenuation region and a spaced-apart second optical attenuation region, and an optically transmissive phase adjustment region interposed between the first optical attenuation region and the second optical attenuation region, the phase adjustment region being configured to change a phase of incident illumination radiation by altering an optical property of the substrate.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: September 8, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Anton P. Eppich, Fei Wang
  • Patent number: 9003338
    Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
  • Patent number: 9001967
    Abstract: Embodiments of methods and apparatus are disclosed for obtaining a phase-contrast digital radiographic imaging system and methods for same that can include an x-ray source for radiographic imaging; a beam shaping assembly including a collimator and a source grating, an x-ray grating interferometer including a phase grating, and an analyzer grating; and an x-ray detector, where a single arrangement of the beam shaping assembly, the x-ray grating interferometer and a position of the detector is configured to provide spectral information (e.g. at least two images obtained at different relative beam energies).
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: April 7, 2015
    Assignee: Carestream Health, Inc.
    Inventors: Pavlo Baturin, Mark E. Shafer
  • Publication number: 20150085974
    Abstract: An X-ray mask structure includes a unibody support substrate having at least one thinned portion surrounded by a wall portion, a top layer disposed on the at least one thinned portion of the support substrate, and a plurality of X-ray absorber patterns disposed on the top layer over the at least one thinned portion. The top layer and the at least one thinned portion form a laminated membrane, wherein the at least one thinned portion and the wall portion provide mechanical support for the top layer, and the laminated membrane provides mechanical support for the plurality of X-ray absorber patterns.
    Type: Application
    Filed: November 15, 2013
    Publication date: March 26, 2015
    Applicant: NATIONAL SYNCHROTRON RADIATION RESEARCH CENTER
    Inventor: Bor Yuan SHEW
  • Patent number: 8972909
    Abstract: The present disclosure relates to a method of performing an optical proximity correction (OPC) procedure that provides for a high degree of freedom by using an approximation design layer. In some embodiments, the method is performed by forming an integrated chip (IC) design having an original design layer with one or more original design shapes. An approximation design layer, which is different from the original design layer, is generated from the original design layer. The approximation design layer is a design layer that has been adjusted to remove features that may cause optical proximity correction (OPC) problems. An optical proximity correction (OPC) procedure is then performed on the approximation design layer. By performing the OPC procedure on the approximation design layer rather than on the original design layer, characteristics of the OPC procedure can be improved.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chang, Jau-Shian Liang, Wen-Chen Lu, Chin-Min Huang, Ming-Hui Chih, Cherng-Shyan Tsay, Chien-Wen Lai, Hua-Tai Lin
  • Patent number: 8966410
    Abstract: A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Wei Huang, Ming-Jui Chen, Chun-Hsien Huang
  • Patent number: 8956789
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes patterning a first photoresist layer overlying a mask blank that is mounted on a first chuck to form a first patterned photoresist layer. The mask blank is selectively etched using the first patterned photoresist layer to form a first patterned mask. The first patterned mask is mounted on a second chuck and a non-flatness compensation is determined. The first patterned mask is mounted on the first chuck and a second photoresist layer is patterned overlying the first patterned mask to form a second patterned photoresist layer. The second patterned photoresist layer includes a device pattern that has been adjusted using the non-flatness compensation. The first patterned mask is selectively etched using the second patterned photoresist layer to form a second patterned mask.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 17, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventor: Sudharshanan Raghunathan
  • Patent number: 8921812
    Abstract: A position measurement device measures the position of a position measurement mark formed on the lower surface of a reticle, thereby measuring the position of the reticle. A position measurement device measures the position of the position measurement mark formed on the lower surface of a lower lid, thereby measuring the position of the lower lid. The relative displacement of the reticle and lower lid is known when the position of the reticle and the position of the lower lid are known. Therefore, when the lower lid having the reticle loaded thereon is carried with a carrying device and set in an exposure device, the stop position of the lower lid is determined by taking this displacement into account. As a result, the reticle can be correctly set in the exposure device.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: December 30, 2014
    Assignee: Nikon Corporation
    Inventors: Motoko Suzuki, Yukiharu Okubo
  • Patent number: 8918746
    Abstract: Methodologies and an apparatus enabling a selection of design rules to improve a density of features of an IC design are disclosed. Embodiments include: determining a feature overlapping a grating pattern of an IC design, the grating pattern including a plurality of grating structures; determining a shape of a cut pattern overlapping the grating pattern; and selecting one of a plurality of rules for the feature based on the determined shape.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Jongwook Kye, Harry J. Levinson
  • Patent number: 8841625
    Abstract: An extreme ultraviolet light source device, comprising a collector mirror focusing extreme ultraviolet radiation at a focal point, wherein a porous plate having a plurality of through holes arranged such that only radiation focusing at said focal point passes is provided insertably between said collector mirror and said focal point on an optical axis of said collector mirror, and a detection means is provided to receive radiation having passed through said porous plate and to detect an intensity of said received radiation, and a method for detecting an irradiance distribution in an extreme ultraviolet light source device.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: September 23, 2014
    Assignee: Ushio Denki Kabushiki Kaisha
    Inventor: Daiki Yamatani
  • Patent number: 8843859
    Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: September 23, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Juan Andres Torres Robles, Oberdan Otto, Yuri Granik
  • Patent number: 8806394
    Abstract: Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs).
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: August 12, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Hanying Feng, Yu Cao, Jun Ye
  • Patent number: 8772737
    Abstract: A coupling module may include an upper portion that defines an aperture, mask contact elements, chuck contact elements and an intermediate element that is connected between the mask contact elements and the upper portion. A shape and a size of the aperture may correspond to a shape and size of a pattern transfer area of an extreme ultra violet (EUVL) mask. The coupling module may be shaped and sized so that once the mask contact elements contact the upper portion of the EUVL mask, the chuck contact elements contact a chuck that supports the mask. The coupling module may further provide at least one conductive path between the upper portion of the EUVL mask and the chuck when the EUVL mask is positioned on the chuck.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: July 8, 2014
    Assignee: Applied Materials Israel, Ltd.
    Inventors: Igor Krivts (Krayvitz), Israel Avneri, Yoram Uziel, Nir Ben-David Dodzin, Ido Holcman, Itzak Yair, Yosi Basson
  • Publication number: 20140177789
    Abstract: Embodiments of methods and apparatus are disclosed for obtaining a phase-contrast digital radiographic imaging system and methods for same that can include an x-ray source for radiographic imaging; a beam shaping assembly including a collimator and a source grating, an x-ray grating interferometer including a phase grating, and an analyzer grating; and an x-ray detector, where the phase-contrast digital radiographic imaging system and methods are adjustable for different mean energies of the x-ray source.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Pavlo Baturin, Mark E. Shafer
  • Patent number: 8762897
    Abstract: A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh
  • Patent number: 8756536
    Abstract: The present invention provides a generation method of generating data for a mask pattern to be used for an exposure apparatus including a projection optical system for projecting a mask pattern including a main pattern and auxiliary pattern onto a substrate, including a step of setting a generation condition under which the auxiliary pattern is generated, and a step of determining whether a value of an evaluation function describing an index which indicates a quality of an image of the mask pattern calculated, wherein if it is determined that the value of the evaluation function falls outside a tolerance range, the generation condition is changed to set a new generation condition.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: June 17, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tadashi Arai
  • Patent number: 8707222
    Abstract: In an electronic design automation technique for optical proximity correction, a mask is represented by a function with an exact analytical form over a mask region. Using the physics of optical projection, a solution based on a spatial frequency analysis is determined. Spatial frequencies above a cutoff are determined by the optical system do not contribute to the projected image. Spatial frequencies below this cutoff affect the print (and the mask), while those above the cutoff only affect the mask. Frequency components in the function below this cutoff frequency may be removed, which will help to reduce computational complexity.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: April 22, 2014
    Assignee: Gauda, Inc.
    Inventors: P. Jeffrey Ungar, Ilhami H. Torunoglu
  • Patent number: 8707231
    Abstract: A system and method are provided for enabling a systematic detection of issues arising during the course of mask generation for a semiconductor device. IC mask layer descriptions are analyzed and information is generated that identifies devices formed by active layers in the masks, along with a description of all layers in proximity to the found devices. The IC mask information is compared to a netlist file generated from the initial as-designed schematic. Determinations can then made, for example, as to whether all intended devices are present, any conflicting layers are in proximity to or interacting with the intended devices, and any unintended devices are present in the mask layers. Steps can then be taken to resolve the issues presented by the problematic devices.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: April 22, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Douglas M. Reber, Mehul D. Shroff, Edward O. Travis
  • Patent number: 8694929
    Abstract: A method and an apparatus for determining the position of a structure on a mask for microlithography, in which the position is determined by comparing an aerial image, measured by a recording device, of a portion of the mask with an aerial image determined by simulation. The position determination includes carrying out a plurality of such comparisons which differ from one another with regard to the input parameters of the simulation.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: April 8, 2014
    Assignees: Carl Zeiss SMT GmbH, Carl Zeiss SMS GmbH
    Inventors: Dirk Seidel, Michael Arnz
  • Patent number: 8694927
    Abstract: A method of designing a pattern layout includes defining one shot area including a plurality of chip areas, generating an initial common layout in the plurality of chip areas, primarily correcting the initial layout to form a primary corrected layout, and secondarily correcting the primary corrected layout independently to form a plurality of secondary corrected layouts.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: April 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Moon-Gyu Jeong
  • Patent number: 8667430
    Abstract: A method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. Designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern. Generating the second, updated DSA directing pattern includes linearizing a self-consistent field theory equation.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventor: Azat Latypov
  • Patent number: 8667428
    Abstract: In an exemplary embodiment, a method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. The step of designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventor: Azat Latypov
  • Patent number: 8656320
    Abstract: A method for creating a photolithography mask from a set of initial mask cells arranged to form an initial mask. The set includes first and second initial mask cells having a mask element in common within an initial region of the initial mask. The method includes a creation of a first modified mask cell and of a second modified mask cell including OPC processing operations, a comparison of the position of the mask element in common between the first modified mask cell and the second modified mask cell, and if the result of the comparison is greater than a threshold, a creation of a new mask region including an optical proximity correction processing operation on the initial region, and a creation of the photolithography mask from the new mask region.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: February 18, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Christian Gardin
  • Patent number: 8595657
    Abstract: Methods of fabricating a photo mask are provided. The method includes collecting sample data, setting a preliminary mask layout, performing an optical proximity correction using the sample data and a preliminary mask layout to obtain an optimized preliminary mask layout, verifying the optimized preliminary mask layout to obtain a final mask layout, and fabricating the photo mask using the final mask layout. Verification of the optimized preliminary mask layout includes operating a verification simulator using the sample data and the optimized preliminary mask layout as input data to obtain verification image data. The verification image data includes a plurality of contours of a pattern at different vertical positions.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: November 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hosun Cha, Eunmi Lee, Sungwoo Lee
  • Patent number: 8589830
    Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving an IC design layout having a feature with an outer boundary, performing a dissection on the feature to divide the outer boundary into a plurality of segments, and performing, using the segments, an optical proximity correction (OPC) on the feature to generate a modified outer boundary. The method also includes simulating a photolithography exposure of the feature with the modified outer boundary to create a contour and performing an OPC evaluation to determine if the contour is within a threshold. Additionally, the method includes repeating the performing a dissection, the performing an optical proximity correction, and the simulating if the contour does not meet the threshold, wherein each repeated dissection and each repeated optical proximity correction is performed on the modified outer boundary generated by the previously performed optical proximity correction.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chang, Chin-Min Huang, Wei-Kuan Yu, Cherng-Shyan Tsay, Lai Chien Wen, Hua-Tai Lin
  • Patent number: 8589828
    Abstract: A method for reducing layer overlay errors by synchronizing the density of mask material in the frame area across the masks in a set is disclosed. An exemplary method includes creating a mask design database corresponding to a mask and containing a die area with one or more dies and a frame area outside the die area. Fiducial features within the frame area are identified, and from the fiducial features, an idle frame area is identified. A reference mask design, which corresponds to a reference mask configured to be aligned with the mask, is used to determine a reference density for the idle frame area. The idle frame area of the mask design database is modified to correspond to the reference density. The modified mask design database is then available for further use including manufacturing the mask.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chang Lee, Chia-Jen Chen, Lee-Chih Yeh, Anthony Yen
  • Patent number: 8584057
    Abstract: A method of data preparation in lithography processes is described. The method includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, converting the IC layout design GDS grid to a first exposure grid, applying a non-directional dither technique to the first exposure, coincident with applying dithering to the first expose grid, applying a grid shift to the first exposure grid to generate a grid-shifted exposure grid and applying a dither to the grid-shifted exposure grid, and adding the first exposure grid (after receiving dithering) to the grid-shifted exposure grid (after receiving dithering) to generate a second exposure grid.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Copmany, Ltd.
    Inventors: Pei-Yi Liu, Shy-Jay Lin, Wen-Chuan Wang, Jaw-Jung Shin, Burn Jeng Lin
  • Patent number: 8560978
    Abstract: Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs).
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: October 15, 2013
    Assignee: ASML Netherlands B.V.
    Inventors: Hanying Feng, Yu Cao, Jun Ye