Mask Inspection (e.g., Semiconductor Photomask) Patents (Class 382/144)
  • Patent number: 10262229
    Abstract: Described is a system for detecting multiple salient objects in an image using low power hardware. From consecutive pair of image frames of a set of input image frames, image channels are generated. The image channels are resized into multiple image scales that specify a relative size of a salient object in the image frames. A patch-based spectral transform is applied to overlapping image patches in the resized image channel, generating salient patches. Saliency patches are combined into a saliency map for each resized image channel, resulting in multiple saliency maps. The saliency maps are combined into an aggregate saliency map. An adaptive threshold is applied to the aggregate saliency map to determine which pixels in the aggregate saliency map correspond to a detected salient object region including a salient object. An object bounding box is generated for each salient object and output to a display.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 16, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: Shankar R. Rao, Narayan Srinivasa
  • Patent number: 10254753
    Abstract: The present disclosure relates to a system for predicting abnormality occurrence using a PLC log data, the system including a controller configured to receive a data from a lower-level device connected to a PLC data log module and determine the data, and to store the data in an event storage when the data is a data related to abnormality occurrence, an analyzer configured to generate an abnormality analysis result by analyzing the data related to abnormality occurrence, and an analysis result storage configured to store the abnormality analysis result, wherein the controller compares the data transmitted from the lower-level device with the abnormality analysis result stored in the analysis result storage, and generates an abnormality occurrence prediction signal, when it is determined that the data transmitted from the lower-level device is similar to the abnormality analysis result.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: April 9, 2019
    Assignee: LSIS CO., LTD.
    Inventor: Seung Jong Kim
  • Patent number: 10254816
    Abstract: A control unit of a substrate processing apparatus has a storage medium that stores operation commands as a single macro. The operation commands include an operation command for shutdown of the substrate processing apparatus by which the substrate processing apparatus is automatically transferred from a normally-operating condition to a condition suitable for man power maintenance, and an operation command for startup of the substrate processing apparatus by which the substrate processing apparatus is automatically transferred to a condition suitable for normal operation after completion of the man power maintenance. The control unit makes a display unit display both the operation commands for shutdown and startup together on a single ejection screen of the display unit, and allows editing of the macro on the single edit screen by using the input unit.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: April 9, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Seiichiro Yuasa, Kunihiko Fujimoto
  • Patent number: 10241395
    Abstract: A pattern correction amount calculating apparatus includes: an accepting unit that accepts pattern information; a micro side group acquiring unit that acquires a micro side group, which is a group of continuous sides forming a contour of a pattern figure indicated by the pattern information, and is a group of micro sides that are each small enough to satisfy a predetermined condition; a virtual side acquiring unit that acquires a virtual side, which is a side that approximates micro sides contained in the micro side group; a virtual side correction amount calculating unit that calculates a virtual side correction amount, which is a correction amount for the virtual side; and a micro side correction amount calculating unit that calculates micro side correction amounts, which are correction amounts respectively for the micro sides contained in the micro side group corresponding to the virtual side, using the virtual side correction amount.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: March 26, 2019
    Assignee: Nippon Control System Corporation
    Inventor: Hiroyuki Tsunoe
  • Patent number: 10204416
    Abstract: Deskew for image review, such as SEM review, aligns inspection and review coordinate systems. Deskew can be automated using design files or inspection images. A controller that communicates with a review tool can align a file of the wafer, such as a design file or an inspection image, to an image of the wafer from the review tool; compare alignment sites of the file to alignment sites of the image from the review tool; and generate a deskew transform of coordinates of the alignment sites of the file and coordinates of alignment sites of the image from the review tool. The image of the wafer may not contain defects.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: February 12, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Arpit Jain, Arpit Yati, Thirupurasundari Jayaraman, Raghavan Konuru, Raj Kuppa, Hema Prasad, Saiyashwanth Momula, Arun Lobo
  • Patent number: 10169522
    Abstract: The present invention relates to a method for tuning lithography systems so as to allow different lithography systems to image different patterns utilizing a known process that does not require a trial and error process to be performed to optimize the process and lithography system settings for each individual lithography system. According to some aspects, the present invention relates to a method for a generic model-based matching and tuning which works for any pattern. Thus it eliminates the requirements for CD measurements or gauge selection. According to further aspects, the invention is also versatile in that it can be combined with certain conventional techniques to deliver excellent performance for certain important patterns while achieving universal pattern coverage at the same time.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: January 1, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Yu Cao, Hanying Feng, Jun Ye
  • Patent number: 10127648
    Abstract: A pattern inspection apparatus includes a stage to mount thereon a substrate with patterns formed thereon and be able to move two-dimensionally, plural detectors of a two-dimensional scale, whose height positions are mutually different and arranged at positions on the stage different from the substrate position, to perform measurement, the body of the two-dimensional scale arranged fixed to a position facing the plural detectors, a sensor to acquire an optical image of the pattern on the substrate, in a state where the stage with the substrate is moving in one direction on a surface for the two-dimensional movement, a calculation circuitry to calculate an image acquiring position of the optical image by using position information measured by the two-dimensional scale, and a comparison circuitry to compare, using a reference image corresponding to the image acquiring position of the optical image, the optical image with the reference image for each pixel.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: November 13, 2018
    Assignee: NuFlare Technology, Inc.
    Inventors: Hideki Nukada, Nobutaka Kikuiri
  • Patent number: 10113975
    Abstract: An appearance inspection device and an appearance inspection method, capable of teaching a line pattern having an arbitrary shape as a portion to be inspected, in relation to a captured image of an inspection object, by a simple teaching operation. The device has an image storing part, a teaching part, an inspecting part and an inspection factor storing part. The teaching part obtains an image of the inspection object in the teaching process, and teaches the position of an inspection point, the position and the angle of an inspection region relative to the inspection point, the inspection factor and a judgment condition. The teaching factor storing part stores a setting parameter and a teaching factor. The inspecting part executes inspection based on the teaching factor in the inspecting process.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: October 30, 2018
    Assignee: FANUC CORPORATION
    Inventor: Rui Kanou
  • Patent number: 10095941
    Abstract: Some of pixels in a general image sensor for image capturing are designated as vision pixels used for vision recognition. Optical information obtained only from the vision pixels is used to perform vision recognition in the vision recognition mode. Capturing image data is generated based on optical information obtained from all the pixels in the image data in the image-shooting mode. A digital signal converter that converts optical information obtained only from vision pixels into a digital signal is separately provided in addition to a digital signal converter that converts optical information of all pixels in the image sensor into a digital signal.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hwa-Yong Kang, Young-Kwon Yoon, Young-Sam Yu, Eun-Soo Chang
  • Patent number: 10062155
    Abstract: Disclosed is a defect detection apparatus. The defect detection apparatus includes an angle extractor configured to extract a slope angle of a pattern from an original image in which a plurality of the patterns are formed at periodic intervals, a pattern period extractor configured to extract a pattern period at which the patterns are separated from each other, by using the slope angle, and an image shifter configured to shift the original image by the pattern period in a direction perpendicular to the slope angle to form the shifted image. The present invention shifts an image by using the slope angle and pattern period of the periodic pattern, thus easily extracting a defect of the original image.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: August 28, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Philippe Lavole
  • Patent number: 10043261
    Abstract: Methods and systems for generating simulated output for a specimen are provided. One method includes acquiring information for a specimen with one or more computer systems. The information includes at least one of an actual optical image of the specimen, an actual electron beam image of the specimen, and design data for the specimen. The method also includes inputting the information for the specimen into a learning based model. The learning based model is included in one or more components executed by the one or more computer systems. The learning based model is configured for mapping a triangular relationship between optical images, electron beam images, and design data, and the learning based model applies the triangular relationship to the input to thereby generate simulated images for the specimen.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: August 7, 2018
    Assignee: KLA-Tencor Corp.
    Inventors: Kris Bhaskar, Jing Zhang, Grace Hsiu-Ling Chen, Ashok Kulkarni, Laurent Karsenti
  • Patent number: 10036961
    Abstract: An optical proximity correction method includes loading a target layout for a mask, generating a correction density map based on manipulation of flare to correct global errors caused by exposing equipment, generating a flare map via convolution integration of the correction density map and a point spread function (PSF) regarding the flare, and correcting the target layout using the flare map and an OPC model.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: July 31, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hoon Jang, Sang-hwa Lee
  • Patent number: 9984109
    Abstract: A system to manage clustering vertices of a streaming graph includes a memory storing a computer program, a vertex structure storing vertices of the graph, and a cluster structure storing clusters of the graph, and a processor. Each cluster structure comprises a plurality of edge structures represent edges of the graph and each edge structure comprises two of the vertices. The processor is configured to execute the program to cluster the vertices using the structures and a maximum cluster size that is constant.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gabriela Jacques da Silva, Kun-Lung Wu, Mindi Yuan
  • Patent number: 9984920
    Abstract: A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Hsueh-Chung Chen, Cheng Chi, Lin Hu, Kafai Lai, Chi-Chun Liu, Jed W. Pitera
  • Patent number: 9970873
    Abstract: A luminescent tag based defect detection system comprises a luminescent tag attachment assembly, an illumination source, one or more detectors, and a set of optical elements. The luminescent tag attachment assembly exposes a sample to one or more luminescent tag materials selectively attached to one or more defects on the sample. The illumination source generates illumination including one or more wavelengths corresponding to the one or more absorption spectra associated with the one or more luminescent tags. At least a portion of the set of optical elements directs illumination from the illumination source to the sample, and at least a portion of the set of optical elements directs illumination emitted from the one or more luminescent tag materials to the one or more detectors. A luminescent tag based defect detection system may also include a luminescent tag removal assembly to remove the luminescent tags after detection.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: May 15, 2018
    Assignee: KLA-Tencor Corporation
    Inventors: Donald Pettibone, Chuanyong Huang, Kurt Haller
  • Patent number: 9940704
    Abstract: A system and method to image a layer of a wafer based on a coordinate of a defect in a pre-layer of the wafer are disclosed. A design file for the current layer can be aligned to the wafer using an image of the current layer. A design file for a previous layer can be aligned to the design file for the current layer.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: April 10, 2018
    Assignee: KLA—Tencor Corporation
    Inventor: Arpit Yati
  • Patent number: 9916965
    Abstract: Hybrid inspectors are provided. One system includes computer subsystem(s) configured for receiving optical based output and electron beam based output generated for a specimen. The computer subsystem(s) include one or more virtual systems configured for performing one or more functions using at least some of the optical based output and the electron beam based output generated for the specimen. The system also includes one or more components executed by the computer subsystem(s), which include one or more models configured for performing one or more simulations for the specimen. The computer subsystem(s) are configured for detecting defects on the specimen based on at least two of the optical based output, the electron beam based output, results of the one or more functions, and results of the one or more simulations.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 13, 2018
    Assignee: KLA-Tencor Corp.
    Inventors: Kris Bhaskar, Grace Hsiu-Ling Chen, Keith Wells, Wayne McMillan, Jing Zhang, Scott Young, Brian Duffy
  • Patent number: 9886753
    Abstract: A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: February 6, 2018
    Assignee: Synopsys, Inc.
    Inventors: Mahantesh Narwade, Namit Gupta, Kaushik De, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal
  • Patent number: 9869712
    Abstract: A method for detecting defects of wafer by wafer sort is introduced. In the method, a wafer sort testing apparatus is used to obtain a DTL or ADART result, wherein a plurality of repaired sites in a wafer is highlighted according to the DTL or ADART result. A plurality of physical locations of the repaired sites is then output. An analysis equipment is used to match the physical locations with a graphic data system (GDS) design layout coordinate of the wafer so as to generate a data correlating with defects at the repaired sites.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: January 16, 2018
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Tuung Luoh, I-Jen Huang, Ling-Wuu Yang, Ta-Hone Yang, Kuang-Chao Chen
  • Patent number: 9846761
    Abstract: A layout of an integrated circuit design is provided and a plurality of multiple patterning decompositions is determined from the layout. Each decomposition of the plurality of multiple patterning decompositions includes patterns separated into masks. One or more files are generated that include sensitivities of pattern capacitances to changes in spacing between patterns due to mask shifts. Using the sensitivities and changes in spacing, respective worst-case performance values are determined for each decomposition. A mask set is selected based on the worst-case performance values.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: December 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Chou, Te-Yu Liu, Ke-Ying Su, Hsien-Hsin Sean Lee
  • Patent number: 9842186
    Abstract: Disclosed herein is a computer-implemented method for determining an overlapping process window (OPW) of an area of interest on a portion of a design layout for a device manufacturing process for imaging the portion onto a substrate, the method comprising: obtaining a plurality of features in the area of interest; obtaining a plurality of values of one or more processing parameters of the device manufacturing process; determining existence of defects, probability of the existence of defects, or both in imaging the plurality of features by the device manufacturing process under each of the plurality of values; and determining the OPW of the area of interest from the existence of defects, the probability of the existence of defects, or both.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: December 12, 2017
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Frank Gang Chen, Joseph Werner De Vocht, Yuelin Du, Wanyu Li, Yen-Wen Lu
  • Patent number: 9823886
    Abstract: To provide an electronic device that can restrict a delayed execution of a process whose existence is impossible to confirm for an overwrite erasure thread. An MFP includes a job execution part that executes a job and an overwrite erasure thread that performs overwrite erasures of obsolete files. The overwrite erasure thread performs the overwrite erasures intermittently even while the job is in execution if the obsolete files have a size more than a threshold value size. The job execution part performs the overwrite erasures while the job is in execution if the obsolete files have a size less than the threshold value size.
    Type: Grant
    Filed: December 17, 2016
    Date of Patent: November 21, 2017
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Yuya Maesono
  • Patent number: 9811623
    Abstract: A method for generating a pattern includes defining a footprint of a main pattern in each cell, arranging a first cell and a second cell which has an auxiliary pattern outside the footprint of the main pattern, side by side in such a manner that the auxiliary pattern outside the footprint of the second cell is present in the footprint of the main pattern of the first cell, and generating the pattern of the mask by removing a pattern element of the auxiliary pattern outside the footprint of the second cell in a portion where the pattern element of the auxiliary pattern outside the footprint of the second cell is close to or overlaps with the main pattern in the first cell of the first cell and the second cell arranged side by side.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: November 7, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroyuki Ishii, Ryo Nakayama, Tadashi Arai
  • Patent number: 9753363
    Abstract: A modeling technique is provided. The modeling technique includes inputting tool parameters into a model and inputting basic model parameters into the model. The technique further includes generating a simulated, corrected reticle design using the tool parameters and the basic model parameters. An image of test patterns is compared against the simulated, corrected reticle design. A determination is made as to whether ?1<?1, wherein ?1 represents model vs. exposure difference and ?1 represents predetermined criteria. The technique further includes completing the model when ?1<?1.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: September 5, 2017
    Assignees: NIKON CORPORATION, NIKON PRECISION INC
    Inventors: Jacek Tyminski, Raluca Popescu, Tomoyuki Matsuyama
  • Patent number: 9747518
    Abstract: A method for selecting samples of reticle design data patterns in order to calibrate the parameters based on which the reference image used in a die-to-database reticle inspection method is rendered, the method comprising the steps of applying local binary pattern (LBP) analysis to a plurality of samples to obtain a p-dimensional vector output for each of the plurality of samples, clustering the q-D data points to M groups, selecting one sample from each clustered group, calculating evaluation scores for the samples selected, and, selecting a portion of the M samples on the representativeness score and the diversity score.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: August 29, 2017
    Assignee: KLA-Tencor Corporation
    Inventors: Feng Zhao, Gang Pan
  • Patent number: 9733577
    Abstract: In some embodiments, the present application is directed to a method and system for process control of a lithography tool. The method transfers a reference pattern to exposure fields of a reference workpiece to form pairs of overlapping reference layers. Misalignment between the overlapping reference layers is measured to form first and second baseline maps, and a ? baseline map is formed from the first and second baseline maps. A production pattern is transferred to exposure fields of a production workpiece to form second production layers arranged over and aligned to first production layers. Misalignment between the first and second production layers is measured to form a production map. The ? baseline map is transformed and subsequently added to the production map, to form a final production map. Parameters of a process tool are updated based on the final production map.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ai-Jen Hung, Chen-Yen Huang, Shin-Rung Lu, Yen-Di Tsen
  • Patent number: 9728373
    Abstract: A pattern inspection apparatus includes a data processing circuitry to input detection data based on a secondary electron from a substrate for each irradiation unit region, where n1×m1 irradiation unit regions in irradiation unit regions configure one of n2×m2 image reference regions configuring an inspection measurement image, to calculate, for each of the n2×m2 image reference regions, a statistic value acquired from the detection data of all the n1×m1 irradiation unit regions in one of the n2×m2 image reference regions, and to define the statistic value as image reference data for the image reference region, and a comparison processing circuitry to receive transmission of the image reference data for each image reference region, and to compare, using a reference image corresponding to the inspection measurement image composed of the n2×m2 image reference regions, the measurement image with the reference image for each image reference region.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: August 8, 2017
    Assignee: NuFlare Technology, Inc.
    Inventors: Nobutaka Kikuiri, Ikunao Isomura
  • Patent number: 9612541
    Abstract: Disclosed are methods and apparatus for qualifying a photolithographic reticle. A reticle inspection tool is used to acquire at least two images at different imaging configurations from each pattern area of the reticle. A reticle pattern is reconstructed based on each at least two images from each pattern area of the reticle. For each reconstructed reticle pattern, a lithographic process with two or more different process conditions is modeled on such reconstructed reticle pattern to generate two or more corresponding modeled test wafer patterns. Each two or more modelled test wafer patterns is analyzed to identify hot spot patterns of the reticle patterns that are susceptible to the different process conditions altering wafer patterns formed with such hot spot patterns.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: April 4, 2017
    Assignee: KLA-Tencor Corporation
    Inventors: Rui-fang Shi, Mark Wagner
  • Patent number: 9613411
    Abstract: Methods and systems for setting up a classifier for defects detected on a wafer are provided. One method includes generating a template for a defect classifier for defects detected on a wafer and applying the template to a training data set. The training data set includes information for defects detected on the wafer or another wafer. The method also includes determining one or more parameters for the defect classifier based on results of the applying step.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: April 4, 2017
    Assignee: KLA-Tencor Corp.
    Inventors: Raghavan Konuru, Naema Bhatti, Michael Lennek, Martin Plihal
  • Patent number: 9582875
    Abstract: Conventionally, there was no method for automatically selecting the layers to be overlaid, so when the number of layers to be overlaid was large, there was a problem that much time was required for selecting the layers. It is an object of the present invention to provide a defect image analysis method capable of specifying patterns and layers in which a defect occurs by overlaying defect images to be analysis targets and design layout data, and a defect image analysis system capable of improving the efficiency to select the layers from the design layout data. The present invention is characterized in dividing analysis target images for each hierarchy corresponding to a manufacturing process and generating a plurality of layers; calculating a degree of matching between each of the layer division images and each design layer of the design layout data; and specifying a design layer with a highest degree of matching of the each design layer as a design layer corresponding to the layer division image.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: February 28, 2017
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takehiro Hirai, Ryo Nakagaki, Kenji Obara
  • Patent number: 9569836
    Abstract: Cases in which defects are analyzed in a manufacturing process stage in which a pattern is not formed or in a manufacturing process in which a pattern formed on a lower layer does not appear in the captured image are increasing. However, in these cases, there is a problem of not being able to synthesize a favorable reference image and failing to detect a defect when a periodic pattern cannot be recognized in the pattern. In the present invention, a defect occupation rate, which is the percentage of an image being inspected occupied by a defect region, is found, it is determined whether the defect occupation rate is higher or lower than a threshold, and, in accordance with the determination results, it is determined whether to create, as the reference image, an image comprising pixels having the average luminance value of the luminance values of a plurality of pixels contained in the image being inspected.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: February 14, 2017
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takehiro Hirai, Ryo Nakagaki, Minoru Harada
  • Patent number: 9541824
    Abstract: A method and system for inspecting defects saves scanned raw data as an original image so as to save time for repeated scanning and achieve faster defect inspection and lower false rate by reviewing suspicious defects and other regions of interest in the original image by using the same or different image-processing algorithm with the same or different parameters.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: January 10, 2017
    Assignee: HERMES MICROVISION, INC.
    Inventors: Wei Fang, Jack Jau
  • Patent number: 9535319
    Abstract: A method includes providing a pre-optical proximity correction (OPC) layout of at least a portion of at least one reticle. The pre-OPC layout defines a test cell including a first test cell area having a plurality of first target features having a first pitch and a second test cell area having a plurality of second target features having a second pitch. A post-OPC layout of the portion of the reticle is formed on the basis of the pre-OPC layout. The formation of the post-OPC layout includes performing a rule-based OPC process, wherein a plurality of first reticle features for the first test cell area are provided on the basis of the plurality of first target features, and performing a model-based OPC process, wherein a plurality of second reticle features for the second test cell area are provided on the basis of the plurality of second target features.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 3, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guido Ueberreiter, Guoxiang Ning, Jui-Hsuan Feng, Paul Ackmann, Chin Teong Lim
  • Patent number: 9530200
    Abstract: A method and a system for inspection of a patterned structure are provided. In various embodiments, the method for inspection of a patterned structure includes transferring the patterned structure into a microscope. The method further includes acquiring a top-view image of the patterned structure by the microscope. The method further includes transferring the patterned structure out of the microscope and exporting the top-view image to an image analysis processor. The method further includes measuring a difference between a contour of the top-view image and a predetermined layout of the patterned structure by the image analysis processor.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: December 27, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chang Hsueh, Chia-Jen Chen, Hsin-Chang Lee
  • Patent number: 9494856
    Abstract: A method and system for inspecting defects saves scanned raw data as an original image so as to save time for repeated scanning and achieve faster defect inspection and lower false rate by reviewing suspicious defects and other regions of interest in the original image by using the same or different image-processing algorithm with the same or different parameters.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: November 15, 2016
    Assignee: HERMES MICROVISION, INC.
    Inventors: Wei Fang, Jack Jau
  • Patent number: 9490181
    Abstract: A misalignment/alignment compensation method for a lithography process includes the steps of: obtaining misalignment data associated with an alignment mark disposed on a substrate; and obtaining a compensation parameter by performing asymmetry compensation calculation on at least one of a first directional component of the misalignment data, which is associated with a first direction, and a second directional component of the misalignment data, which is associated with a second direction.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: November 8, 2016
    Inventor: Tian-Xing Huang
  • Patent number: 9483547
    Abstract: Recipes are hierarchically clustered into groups based on features of the recipes. Candidate clusters with a threshold number of clustered recipes having at least one feature in common are found by traversing the hierarchy. A plurality of clusters is selected for display to a user from among the candidates based on an objective function that considers the relevancy of the cluster as well as diversity of the clusters. A plurality of recipes within each selected cluster is selected for display to a user from among the recipes within the cluster based on an objective function that considers the quality of the recipe as well as the diversity of the recipes within the cluster. At least one feature that all of the recipes in a respective cluster have in common is used to generate a name for the cluster.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: November 1, 2016
    Assignee: Yummly, Inc.
    Inventors: David B. Feller, Vadim Geshel, Gregory Allen Druck, Jr., Iurii Volodimirovich Korolov
  • Patent number: 9442894
    Abstract: The present invention assigns, in order to form a word representation for a flow pattern in a multiply connected exterior domain having N holes topologically, any one of words that define two types of flow patterns that can be topologically applied to a simply connected exterior domain having a hole, and repeatedly assigns, to the assigned word, any one of words that define five types of operations that can be topologically applied to add a hole to the flow pattern, so that a word representation corresponding to the multiply connected exterior domain having N holes is formed.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: September 13, 2016
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Takashi Sakajo, Tomoo Yokoyama
  • Patent number: 9418400
    Abstract: Systems and methods for rendering depth-of-field visual effect on images with high computing efficiency and performance. A diffusion blurring process and a Fast Fourier Transform (FFT)-based convolution are combined to achieve high-fidelity depth-of-field visual effect with Bokeh spots in real-time applications. The brightest regions in the background of an original image are enhanced with Bokeh effect by virtue of FFT convolution with a convolution kernel. A diffusion solver can be used to blur the background of the original image. By blending the Bokeh spots with the image with gradually blurred background, a resultant image can present an enhanced depth-of-field visual effect. The FFT-based convolution can be computed with multi-threaded parallelism.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: August 16, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Nikolay Sakharnykh, Holger Gruen
  • Patent number: 9401013
    Abstract: There is provided an inspection method capable of classifying defects detected on a production layer of a specimen. The method comprises: obtaining input data related to the detected defects; processing the input data using a decision algorithm associated with the production layer and specifying two or more classification operations and a sequence thereof; and sorting the processed defects in accordance with predefined bins, wherein each bin is associated with at least one classification operation, wherein at least one classification operation sorts at least part of the processed defects to one or more classification bins to yield finally classified defects, and wherein each classification operation, excluding the last one, sorts at least part of the processed defects to be processed by one or more of the following classification operations.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: July 26, 2016
    Assignee: Applied Materials Israel, Ltd.
    Inventors: Mark Geshel, Zvi Goren, Efrat Rozenman
  • Patent number: 9390486
    Abstract: A method and system for aligning a DUT image for testing. The alignment is performed by obtaining an optical image of the DUT from an optical system; obtaining a computer aided design (CAD) data having CAD layers of the DUT; constructing a CAD image of the DUT by overlaying the CAD layers; operating on the CAD image to generate a synthetic image simulating an optical image of the DUT; generating a difference image by comparing the optical image to the synthetic image; and, varying parameters of the synthetic image so as to minimize the difference image.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 12, 2016
    Inventor: Neeraj Khurana
  • Patent number: 9386243
    Abstract: A lens shading correction method includes providing lens shading correction profile data; calculating an intensity values of light passing through each of one or more visible light pass filters and each of one or more infrared light pass filters; calculating an average of the intensity values of the light passing through the one or more visible light pass filters; calculating an average of the intensity values of the light passing through the one or more infrared light pass filters; calculating a normalized intensity value of the light passing through the one or more infrared light pass filters, based on the calculated averages; adjusting one or more lens shading correction coefficients included in the lens shading correction profile data and each having a value varying depending on a frequency element of light, based on the calculated normalized intensity value; and correcting lens shading by using the adjusted lens shading correction coefficient.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongpan Lim, Taechan Kim
  • Patent number: 9372399
    Abstract: An imprint lithography method is disclosed for reducing a difference between an intended topography and an actual topography arising from a part of a patterned layer of fixed imprintable medium. The method involves imprinting an imprint lithography template into a layer of flowable imprintable medium to form a patterned layer in the imprintable medium, and fixing the imprintable medium to form a patterned layer of fixed imprintable medium. Local excitation is applied to the part of the patterned layer to adjust a chemical reaction in the part of the patterned layer to reduce the difference between the intended topography and the actual topography arising from the part of the fixed patterned layer of imprintable medium when this is subsequently used as a resist for patterning the substrate. An imprint medium suitable for imprint lithography with the method is also disclosed.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: June 21, 2016
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Martinus Bernardus Van Der Mark, Vadim Yevgenyevich Banine, Andre Bernardus Jeunink, Johan Frederik Dijksman, Sander Frederik Wuister, Emiel Andreas Godefridus Peeters, Johan Hendrik Klootwijk, Roelof Koole, Christianus Martinus Van Heesch, Ruediger Guenter Mauczok, Jacobus Bernardus Giesbers
  • Patent number: 9367910
    Abstract: A method and system to analyze various dimensional parameters of a structure, such as a self-assembled block copolymer structure whether formed by graphoepitaxy or chemical epitaxy. The method involves image processing including median filtering and feature detection to determine critical dimension information, and optionally the use of a Hough transform to find periodicity values and to determine placement errors.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: June 14, 2016
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Christianus Martinus Van Heesch, Hieronymus Johannus Christiaan Meessen
  • Patent number: 9360436
    Abstract: The disclosure provides an inspection device including a light source module, an image receiving module and a processing unit. The light source module emits a first incident light and a second incident light to a device under test (DUT). The image receiving module receives a first image corresponding to the DUT irradiated by the first incident light, and receives a second image corresponding to the DUT irradiated by the second incident light. The processing unit calculates the contrast ratio of the first image and the second image to obtain a high-contrast image for inspection.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: June 7, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Yi-Chen Hsieh, Chih-Jung Chiang, Fu-Cheng Yang
  • Patent number: 9360863
    Abstract: Various embodiments for determining parameters for wafer inspection and/or metrology are provided.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: June 7, 2016
    Assignee: KLA-Tencor Corp.
    Inventors: Govind Thattaisundaram, Mohan Mahadevan, Ajay Gupta, Chien-Huei Adam Chen, Ashok Kulkarni, Jason Kirkwood, Kenong Wu, Songnian Rong
  • Patent number: 9311698
    Abstract: Various embodiments for detecting defects on a wafer are provided. Some embodiments include matching a template image, in which at least some pixels are associated with regions in the device having different characteristics, to output of an electron beam inspection system and applying defect detection parameters to pixels in the output based on the regions that the pixels in the output are located within to thereby detect defects on the wafer.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: April 12, 2016
    Assignee: KLA-Tencor Corp.
    Inventors: Xing Chu, Jan A. Lauber, J. Rex Runyon
  • Patent number: 9311047
    Abstract: A matching circuit includes pattern circuits, and a signal path in which the pattern circuits are series-connected, wherein each of the pattern circuits connected to a preceding-stage pattern circuit through the signal path is settable in a first operation mode and in a second operation mode, wherein each of the pattern circuits in the first operation mode generates a result of matching in response to both a result of matching supplied from a preceding-stage pattern circuit and a result obtained by matching data supplied from the preceding-stage pattern circuit against part of a regular expression pattern, and wherein each of the pattern circuits in the second operation mode generates a result of matching in response to a result obtained by matching the data supplied from the preceding-stage pattern circuit against part of a regular expression pattern, without relying on a result of matching supplied from the preceding-stage pattern circuit.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: April 12, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Shinichiro Tago, Hiroya Inakoshi
  • Patent number: 9297739
    Abstract: A method and device for estimating a porosity ratio of a sample of material from at least one gray-scale coded image. The method includes: evaluating an intermediate ratio of a sample for each value of a plurality of gray-scale threshold values lying between two determined limit values, the intermediate ratio being equal to a ratio of a number of pixels of the at least one image having a gray-scale value bounded by the threshold value to a total number of pixels of the at least one image; and estimating the porosity ratio of the sample by analyzing variations in the intermediate ratio as a function of the threshold value.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: March 29, 2016
    Assignee: SNECMA
    Inventors: Julien Schneider, Benedicte Marie Le Borgne
  • Patent number: 9299150
    Abstract: A method of recording the location of a point of interest on an object, the method comprising capturing a digital image of an object having a point of interest, accessing a three-dimensional virtual model of the object, aligning the image with the model, calculating the location of the point of interest with respect to the model, and recording the calculated point of interest location. Also, a system for performing the method.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: March 29, 2016
    Assignee: Airbus Operations Limited
    Inventors: Lee Dann, Joerg Reitmann