Integrated Optical Circuit Patents (Class 385/14)
  • Patent number: 12374630
    Abstract: A stress-reduced silicon photonics semiconductor wafer includes a silicon nitride layer on a backside of the wafer. At least one silicon nitride stress-reduction configuration is on a topside of the wafer. At least one silicon nitride photonics device is also on the topside of the wafer. A silicon photonics device can be situated in the wafer.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: July 29, 2025
    Assignee: Newport Fab, LLC
    Inventors: Oleg Martynov, Edward Preisler, William Krieger
  • Patent number: 12369251
    Abstract: An optical communication module substrate includes a wiring board and an opto-electronic hybrid substrate, the wiring board and the opto-electronic hybrid substrate being connected to each other, in which a connection terminal of the wiring board and a connection terminal of the opto-electronic hybrid substrate are electrical connection points, and a frame-shaped removal portion is formed by removing a portion of the metal reinforcing layer of the opto-electronic hybrid substrate that faces the connection terminal with the insulating layer interposed between the metal reinforcing layer and the connection terminal, so as to surround each terminal. According to this configuration, the connection strength at the connection point between the wiring board and the opto-electronic hybrid substrate is sufficiently ensured, and the optical communication module substrate has excellent electrical properties that are compatible with high-speed signal transmission.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: July 22, 2025
    Assignee: NITTO DENKO CORPORATION
    Inventors: Tadao Okawa, Takashi Oda, Masataka Yamaji, Kazushi Ichikawa
  • Patent number: 12360431
    Abstract: A photonic integrated circuit (PIC) includes a first microresonator that generates a two-mode squeezed vacuum using spontaneous four-wave mixing. Specifically, the first microresonator uses a nonlinear optical medium to convert two pump photons into a pair of entangled signal and idler photons. Due to imperfect conversion efficiency, some of the pump light may co-propagate with the signal light and idler light. To remove this “unconverted” pump light, the PIC includes a second microresonator that is tuned to resonate with only the pump light. The second microresonator is located after the first microresonator and couples the unconverted pump light into a waveguide that guide the light off the PIC. Thus, the second microresonator acts as a notch filter. Integrating this pump filter onto the PIC adds negligibly to the path length of the squeezed light, and therefore saves the propagation losses incurred when using a much larger off-chip filter.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: July 15, 2025
    Inventors: Zheshen Zhang, Shuai Liu, Bo-Han Wu
  • Patent number: 12363464
    Abstract: An optical link system for computation, preferably including a photonics substrate and a plurality of electronics modules, such as processors, memory controllers, and/or switches, which are preferably bonded to the photonics substrate. A photonics substrate, preferably including a plurality of optical links including waveguides and optical transducers. A method for optical link system operation, preferably including operating electronics modules and using optical links, optionally in cooperation with electronics modules such as switches, to transfer information between the electronics modules.
    Type: Grant
    Filed: March 18, 2024
    Date of Patent: July 15, 2025
    Assignee: Luminous Computing, Inc.
    Inventors: Patrick Gallagher, Thomas W. Baehr-Jones, Michael Gao, Mitchell A. Nahmias
  • Patent number: 12360313
    Abstract: The present disclosure generally pertains to systems and methods for processing optical signals. In some embodiments, an optical system has an optical device for receiving a plurality of optical signals and processing such signals in a desired way. The optical device has one or more functional layers that are separated by buffer layers. The index of refraction of at various points in each functional layer is controlled during manufacturing so that the functional layer performs one or more optical functions or, in other words, manipulates one or more incoming optical signals in a desired way, such as switching, filtering, splitting, focusing, collimating, etc. As an example, the index of refraction profile within a region of a functional layer may be controlled so that an incoming signal from a first optical fiber is redirected for reception by a second optical fiber that is not aligned with the first optical fiber.
    Type: Grant
    Filed: May 30, 2024
    Date of Patent: July 15, 2025
    Assignee: Board of Trustees of the University of Alabama, for and on behalf of the University of Alabama in Huntsville
    Inventors: Robert Lindquist, Patrick Reardon
  • Patent number: 12354935
    Abstract: Integrated circuit (IC) package substrate with an embedded trace substrate (ETS) layer on a substrate, and related fabrication methods. The package substrate of the IC package includes an ETS layer provided on the substrate to facilitate providing higher density substrate interconnects to provide bump/solder joints for coupling a semiconductor die to the package substrate. ETS interconnects in the ETS layer in the package substrate facilitates die connections having a reduced line-spacing ratio (L/S) (e.g., 5.0 micrometers (?m)/5.0 ?m or less) over substrate interconnects in a substrate. In additional exemplary aspects, raised metal pillar interconnects are formed in contact with respective ETS interconnects of the ETS layer of the package substrate to avoid or reduce metal consumption by die solder disposed on metal pillar interconnects of the ETS layer providing bump/solder joints.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: July 8, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kuiwon Kang, Chin-Kwan Kim, Joonsuk Park
  • Patent number: 12332479
    Abstract: Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.
    Type: Grant
    Filed: March 15, 2024
    Date of Patent: June 17, 2025
    Assignee: Lightmatter, Inc.
    Inventors: Nicholas C. Harris, Carl Ramey, Michael Gould, Thomas Graham, Darius Bunandar, Ryan Braid, Mykhailo Tymchenko
  • Patent number: 12322928
    Abstract: An optical device may include a substrate and vertical-cavity surface-emitting lasers (VCSELs) on the substrate. The optical device may also include a coupling layer over the substrate and that includes optical guides aligned with the VCSELs to guide outputs thereof from a vertical path direction to a lateral path direction. The optical device also includes controllable delay elements, each controllable delay element associated with a respective optical guide, and a controller coupled to the controllable delay elements.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: June 3, 2025
    Assignee: EAGLE TECHNOLOGY, LLC
    Inventors: Stephen J. Bauman, Fraser R. Dalgleish
  • Patent number: 12316744
    Abstract: A programmable data storage device includes: a non-volatile memory; a storage controller configured to control the non-volatile memory; a network interface; and a field programmable gate array configured to: implement a blockchain algorithm; and store at least one block of a blockchain corresponding to the blockchain algorithm in the non-volatile memory via the storage controller; and a processor having memory coupled thereto, the memory having instructions stored thereon that, when executed by the processor, cause the processor to: send and receive one or more blocks of the blockchain via the network interface; and control the field programmable gate array to execute the blockchain algorithm on the one or more blocks of the blockchain.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: May 27, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rajinikanth Pandurangan, Vijay Balakrishnan
  • Patent number: 12313880
    Abstract: An optical integrated device includes a substrate and a waveguide that has a hollow structure. The waveguide includes a first waveguide and a second waveguide that is optically coupled to the first waveguide and that has a smaller relative refractive index difference than that of the first waveguide and converts a mode diameter to a mode diameter of an optical fiber in accordance with travelling of light. The optical integrated device includes a dent portion that is formed in the vicinity of the dicing line on the substrate such that the width of the output end surface is smaller than the core width of the optical fiber that is optically coupled to the output end surface in the state in which the dicing end surface of the substrate protrudes farther than the output end surface of the second waveguide in the axial direction of the optical waveguide.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 27, 2025
    Assignee: FUJITSU OPTICAL COMPONENTS LIMITED
    Inventors: Tatsuya Ito, Takeshi Matsumoto
  • Patent number: 12313886
    Abstract: An apparatus includes: at least one of a circuit board or a substrate; and a first structure attached to the at least one of a circuit board or a substrate. The first structure is configured to enable an optical module with connector to be removably coupled to the first structure, and the optical module with connector is configured to enable an optical fiber connector to be removably coupled to the optical module with connector.
    Type: Grant
    Filed: March 26, 2024
    Date of Patent: May 27, 2025
    Assignee: Nubis Communications, Inc.
    Inventors: Peter Johannes Winzer, Clinton Randy Giles, Guilhem de Valicourt, Peter James Pupalaikis
  • Patent number: 12313884
    Abstract: A polarization-independent, optical circulator is formed in silicon photonics. The polarization-independent, optical circulator uses an optical splitter having two couplers and two waveguides joining the two couplers. One of the two waveguides is thinner than the other to create a large effective index difference between TE and TM modes transmitted through the one waveguide. Polarization rotators, including reciprocal and/or non-reciprocal rotators, are further used to create the optical circulator.
    Type: Grant
    Filed: May 1, 2024
    Date of Patent: May 27, 2025
    Assignee: Skorpios Technologies, Inc.
    Inventors: Majid Sodagar, Wenyi Wang, Changyi Li, Guoliang Li, Murtaza Askari, Yi Wang, John Dallesasse, Stephen B. Krasulick
  • Patent number: 12292607
    Abstract: An optical package includes a substrate made of a first material having an upper surface and a lower surface. The substrate further includes at least one cavity opening onto an upper surface of the substrate. Electrical connection vias extend through the substrate. An electronic integrated circuit chip is mounted on the upper surface of the substrate in a position so as to cover the at least one cavity. The electronic integrated circuit chip includes an integrated optical sensor. Each cavity is filled with a second material having a thermal conductivity greater than the thermal conductivity of the first material. The electrical connection vias are arranged on either side of each cavity and between two cavities.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: May 6, 2025
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Deborah Cogoni, Raphael Goubot, Younes Boutaleb
  • Patent number: 12271045
    Abstract: The present disclosure provides a reverse clamping compression device for CPO or NPO. The device includes a mechanical bolster placed on a main board, a compression cover covering optical modules, and a fastening connecting and fixing the compression cover to the mechanical bolster and protruding below the mechanical bolster. In the present disclosure, the compression cover above the optical modules is used to apply a compression force to the optical modules, and the spring element is placed in space below the main board, therefore, the space above the compression cover is not occupied, which can maximize the use of the space above the optical modules, greatly shorten the heat conduct path of the heat sink module, and ensure that the entire device is still assembled from top to bottom.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: April 8, 2025
    Assignee: Celestica Technology Consultancy (Shanghai) Co. Ltd
    Inventors: Chao Sun, Peng Xiao
  • Patent number: 12272921
    Abstract: Data rate that can be supported by a photodetector can be limited by the aperture size of the photodetector. In some embodiments, the minimum aperture diameter can be about 30 um. This limitation is due, for example, to an inability of the optics to focus the beam to a smaller spot, and the mechanical tolerances of the assembly process. The techniques described in the present disclosure can reduce the optical spot size and improve on the mechanical tolerances that are achievable, thereby improving the photodetector and VCSEL manufacturing processes and systems. A photodetector or VCSEL system design with higher data rate and lower production cost can be achieved using the techniques described herein.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: April 8, 2025
    Assignee: Broadcom International Pte. Ltd.
    Inventors: Tak Kui Wang, Rashit Nabiev, Ramana M. V. Murty, Laura M. Giovane
  • Patent number: 12266673
    Abstract: A semiconductor package includes electric integrated circuit dies, photoelectric integrated circuit dies, and an inter-chip waveguide. The electric integrated circuit dies are laterally encapsulated by a first insulating encapsulant. The photoelectric integrated circuit dies are laterally encapsulated by a second insulating encapsulant. Each one of photoelectric integrated circuit dies includes an optical input/output terminal. The inter-chip waveguide is disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lun Chang, Ching-Hua Hsieh, Chung-Hao Tsai, Chung-Shi Liu, Chuei-Tang Wang, Hsiu-Jen Lin
  • Patent number: 12264242
    Abstract: A resin composition for an optical communication component includes a base resin and silica. The base resin contains a polyether ether ketone resin as a main component. The content of the silica in the resin composition is 55 to 75 mass %.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: April 1, 2025
    Assignee: Fujikura Ltd.
    Inventor: Takahito Otomitsu
  • Patent number: 12259580
    Abstract: Some embodiments of the disclosure provides a substrate for optical fiber array and the disclosed substrate fixes the fiber by epoxy. In some embodiments, the substrate includes a main body, a first holding groove, and a second holding groove. The first holding groove is notched along a width direction of the main body for holding a stripped optical fiber by epoxy. The second holding groove is an arc-shaped groove and connected with the first holding groove. The second holding groove extends along a notching direction of the first holding groove for holding an unstripped optical fiber. In other embodiments, a groove is notched along a length direction of the main body to prevent epoxy overflow.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: March 25, 2025
    Assignee: Suzhou TFC Optical Communication Co., Ltd.
    Inventor: Zhiguo Luo
  • Patent number: 12253725
    Abstract: This present disclosure seals the light propagation path in an optical interconnection element from external contaminants. The optical interconnection element includes a reflective surface, which can also be sealed from external contaminants Additional novel concepts include all enclosed sealed regions of the optical interconnection element being fluidly connected and making the final seal of the optical interconnection element with a thin plate, which can bend reducing the pressure differential between the ambient environment and the sealed internal volume of the optical interconnection element.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: March 18, 2025
    Assignee: SAMTEC, INC.
    Inventors: Matthew Brian Puffer, Raymond Lee, R. Brad Bettman, Edwin Loy, Dyan Seville-Jones, Arlon Martin, Stephen Michael Girlando, Christopher Alan Bandfield
  • Patent number: 12253716
    Abstract: In one aspect, the disclosure relates to an apparatus including a photonic integrated circuit (PIC) including an optical network including V optical output channels and U optical input ports, wherein a selectable subset of the U optical input ports can be connected to L lasers, wherein L is less than or equal to U, and wherein the PIC is operable to output light on some or all of the V optical output channels in response to different number of active lasers connected to the U optical input ports.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: March 18, 2025
    Inventor: Long Chen
  • Patent number: 12253714
    Abstract: An exemplary multi quantum well structure may include a silicon platform having a pit formed in the silicon platform, a chip positioned inside the pit, a first waveguide formed in the chip, and a second waveguide formed in the silicon platform. The pit may be defined at least in part by a sidewall and a base. The chip may include a first side and a first recess in the first side. The first side may be defined in part by a first cleaved or diced facet. The first recess may be defined in part by a first etched facet. The first waveguide may be configured to guide an optical beam to pass through the first etched facet. The second waveguide may be configured to guide the optical beam to pass through the sidewall. The second waveguide may be optically aligned with the first waveguide.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: March 18, 2025
    Assignee: Skorpios Technologies, Inc.
    Inventors: Paveen Apiratikul, Damien Lambert
  • Patent number: 12248175
    Abstract: The disclosed structures and methods are directed to a chip for an optical gyroscope and methods of manufacturing the chip for the optical gyroscope. The chip comprises a substrate, a waveguide having a first waveguide cladding layer and a waveguide core; and a ring resonator having a first ring cladding layer and a ring resonator core attached to the first ring cladding layer. A side wall of the ring resonator core forms an obtuse angle with an upper surface of the substrate. The method comprises etching a ring groove and a waveguide groove; placing the optical fiber ring into the ring groove and the optical fiber waveguide into the waveguide groove. The method further comprising splicing two ends of an optical fiber; annealing the ring junction of the optical fiber ring; and attaching the optical fiber waveguide to the waveguide groove and the optical fiber ring into the ring groove.
    Type: Grant
    Filed: October 27, 2023
    Date of Patent: March 11, 2025
    Assignee: OSCPS MOTION SENSING INC.
    Inventor: Kazem Zandi
  • Patent number: 12248206
    Abstract: A method of integrating an optoelectronic device comprising a Pockels material, such as lithium niobate (LiNbO3), includes forming an optoelectronic device layer over a semiconductor layer. The optoelectronic device layer includes a patterned optoelectronic device segment in an interlayer dielectric. A window is etched in the interlayer dielectric using the patterned optoelectronic device segment as a sacrificial etch stop. The patterned optoelectronic device segment is removed in the window. The optoelectronic device comprising the Pockels material is formed in place of the removed patterned optoelectronic device segment. The optoelectronic device comprising the Pockels material may be formed from an optoelectronic chiplet.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: March 11, 2025
    Assignee: Newport Fab, LLC
    Inventors: Edward Preisler, Oleg Martynov
  • Patent number: 12248178
    Abstract: A packaged device includes an optical IC having an optical feature therein. An interconnect structure including layers of conductive features embedded within respective layers of dielectric materials overlie the optical feature. The interconnect structure is patterned to remove the interconnect structure from over the optical feature and a dielectric material having optically neutral properties, relative to a desired light wavelength(s) is formed over the optical feature. One or more electronic ICs may be bonded to the optical IC to form an integrated package.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: March 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 12242103
    Abstract: A batch-molding multi optical transmission sheet assembly includes a batch-molding multi optical transmission sheet, a housing member, and a fixing element. The batch-molding multi optical transmission sheet includes a sheet-like covering part made of plastic, and a plurality of optical transmission regions, inside the covering part, including a core region made of plastic that is disposed to extend along an extending direction of the covering part and a clad region made of plastic that surrounds an outer circumference of the core region, the optical transmission regions being arranged in a line in substantially parallel with each other along a principal surface of the covering part. The housing member includes a disposition hole in which at least one end part of the batch-molding multi optical transmission sheet is housed. The fixing element fixes the batch-molding multi optical transmission sheet and the housing member.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: March 4, 2025
    Inventors: Yasuhiro Koike, Hiroshi Takizuka
  • Patent number: 12235492
    Abstract: A large-scale silicon-photonics-based optical switching system that occupies an area larger than the maximum area of a standard step-and-repeat lithography reticle is disclosed. The system includes a plurality of identical switch blocks, each of is formed in a different reticle field that no larger than the maximum reticle size. Bus waveguides of laterally adjacent switch blocks are stitched together at lateral interfaces that include a second arrangement of waveguide ports that is common to all lateral interfaces. Bus waveguides of vertically adjacent switch blocks are stitched together at vertical interfaces that include a first arrangement of waveguide ports that is common to all vertical interfaces. In some embodiments, the lateral and vertical interfaces include waveguide ports having waveguide coupling regions that are configured to mitigate optical loss due to stitching error.
    Type: Grant
    Filed: May 16, 2024
    Date of Patent: February 25, 2025
    Assignee: The Regents of the University of California
    Inventors: Tae Joon Seok, Ming Chiang A Wu
  • Patent number: 12222566
    Abstract: Alignment aid structures and the method of formation of these structures on an interposer comprised of a planar waveguide layer and a base structure, facilitate the alignment of the optical axes of optical and optoelectrical devices formed from and mounted to the interposer. Alignment aids formed from a common hard mask on the planar waveguide layer of the interposer structure include vertical and lateral alignment structures and fiducials. Optical losses for signals propagating in interposer-based photonic integrated circuits are reduced with effective alignment structures and methods.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: February 11, 2025
    Assignee: POET Technologies, Inc.
    Inventor: Suresh Venkatesan
  • Patent number: 12222552
    Abstract: The present disclosure is directed to photonic wavelength division multiplexing (WDM) receivers with polarization diversity and/or low reflectance. In embodiments, a WDM receiver is provided with a splitter, a plurality of waveguides and a plurality of photodetectors in series. The waveguides having particular equal path lengths relationship from the splitter to respective ones of the photodetectors. In other embodiments, the WDM receiver is provided with a splitter, a looped waveguide, a plurality of photodetectors, and a plurality of variable optical attenuators (VOAs). The VOAs are configured to suppress reflection of signal beams back to the transmitter. In various embodiments, the WDM receiver is a receiver sub-assembly of a silicon photonic transceiver disposed in a silicon package. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: February 11, 2025
    Assignee: Intel Corporation
    Inventors: Duanni Huang, Saeed Fathololoumi, Meer Nazmus Sakib, Mohammad Montazeri Najafabadi, Chaoxuan Ma, David Hui, Taehwan Kim, Ling Liao, Hao Li, Ganesh Balamurugan, Haisheng Rong, Aliasghar Eftekhar
  • Patent number: 12216314
    Abstract: Provided is an optical module having high efficiency in optical coupling to a functional element on a substrate. An optical module includes: a first optical waveguide disposed parallel to a substrate; a condensing mirror configured to reflect and condense light propagated in the first optical waveguide toward the substrate; a second optical waveguide formed in a tapered shape narrowed toward the substrate, the second optical waveguide guiding the light reflected by the condensing mirror to the vicinity of the surface of the substrate; and an optical function unit disposed on the substrate such that the light emitted from the second optical waveguide is incident on the optical function unit.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: February 4, 2025
    Assignee: AIO CORE CO., LTD.
    Inventors: Shigeru Kobayashi, Kazuhiro Shiba, Mitsuru Kurihara, Kazuhiko Kurata
  • Patent number: 12219304
    Abstract: A network element receives a classical header for a quantum payload, and processes the classical header to determine a destination endpoint for the quantum payload. The network element generates a new classical header for the quantum payload based on the destination endpoint. The network element sends the new classical header to a next hop ahead of the quantum payload at a time based on a number of hops between the network element and the destination endpoint.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: February 4, 2025
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Alireza Shabani, Bing Qi, Stephen Magno DiAdamo, Glen W. Miller, Ramana Rao Venkata Renuka Kompella
  • Patent number: 12211755
    Abstract: A system may include a wafer that includes ICs and defines cavities. Each cavity may be formed in a BEOL layer of the wafer and proximate a different IC. The system may also include an interposer that includes a transparent layer configured to permit optical signals to pass through. The interposer may also include at least one waveguide located proximate the transparent layer. The at least one waveguide may be configured to adiabatically couple at least one optical signal out of the multiple ICs. Further, the interposer may include a redirecting element optically coupled to the at least one the waveguide. The redirecting element may be located proximate the transparent layer and may be configured to receive the at least one optical signal from the at least one waveguide. The redirecting element may also be configured to vertically redirect the at least one optical signal towards the transparent layer.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: January 28, 2025
    Assignee: II-VI DELAWARE, INC.
    Inventors: Shiyun Lin, Daniel Mahgerefteh, Bryan Park, Jin-Hyoung Lee
  • Patent number: 12210197
    Abstract: A method and system for forming a photonic device. A photonic device may include a substrate, a cladding layer disposed on the substrate, an electrical device region formed within the cladding layer, the electrical device region having a plurality of electrical device component layers that include at least one metal layer, and a grating region formed within the cladding layer, the grating region including a grating coupler and the at least one metal layer. The at least one metal layer is deposited simultaneously in the electrical device and grating regions and is used in the grating region to reflect light emitted from the grating coupler.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 28, 2025
    Assignee: Lumentum Operations LLC
    Inventors: Guilhem De Valicourt, Michael Kossey
  • Patent number: 12204150
    Abstract: An assembly of two fiber optic ferrules allows for the mating of a CWDM fiber optic ferrule with a non-CWDM fiber optic ferrule. The CWDM fiber optic ferrule has optical fibers that carry optical beams with at least two different wavelengths, which the non-CWDM ferrule has optical fibers that carry only one wavelength. The CWDM fiber optic ferrule and the non-CWDM fiber optic ferrule have optical fibers that are inserted along parallel axes. The non-CWDM fiber optic ferrule has a lens pitch that matches the CWDM ferrule.
    Type: Grant
    Filed: December 26, 2023
    Date of Patent: January 21, 2025
    Assignee: US Conec Ltd.
    Inventors: Mitchell Cloud, Darrell R. Childers, D J Hastings
  • Patent number: 12197002
    Abstract: Disclosed are a heterogeneously integrated optical modulator and a manufacturing method thereof. The modulator includes a substrate having a trench, an input waveguide disposed at one side of the trench, an output waveguide disposed at the other side of the trench, a first Mach-Zehnder interferometer including first branch waveguides disposed between the input waveguide and the output waveguide and a heater disposed on one of the first branch waveguides, and second Mach-Zehnder interferometers connected to each of the first branch waveguides.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: January 14, 2025
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young-Tak Han, Seoktae Kim, Sang Ho Park, Yongsoon Baek, Jang Uk Shin, Seok Jun Yun, Seo Young Lee
  • Patent number: 12189183
    Abstract: A structure includes a polarization device such as a polarization splitter, a polarization combiner or a polarization splitter rotator including a waveguide having a light absorber at an end section with an at least hook shape, e.g., it can be hooked or spiral shape. The structure also includes another waveguide adjacent the stated waveguide. The hook or spiral shape acts as a light absorber that reduces undesired optical noise such as excessive light insertion loss and/or light scattering. The hook or spiral shape may also be used on supplemental waveguides used to further filter and/or refine an optical signal in one of the waveguides of the polarization device, e.g., downstream of an output section of the polarization splitter and/or rotator.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: January 7, 2025
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Yusheng Bian, Won Suk Lee, Andreas D. Stricker
  • Patent number: 12191257
    Abstract: A circuit package is described that includes a photonic interposer, a second interposer, and a die partially overlapping and connected to both the photonic interposer and the second interposer.
    Type: Grant
    Filed: January 8, 2024
    Date of Patent: January 7, 2025
    Assignee: CELESTIAL AI INC.
    Inventor: Ankur Aggarwal
  • Patent number: 12181724
    Abstract: Disclosed are apparatus and methods for optical interconnections that include the integration of a photonics die (pDie) and an electronic die (eDie) with a socket layer, waveguides and fiber connectors to enable high bandwidth communications. In one embodiment, an exemplary optical interconnect device includes an electronic die coupled to a photonics die and integrated with a substrate, a socket, a board, a pair of micro-lenses and a mirror coupled to a waveguide, which can be embedded in the board. In another embodiment, the waveguide is embedded in a socket layer and coupled to a fiber connector. In these embodiments, the exemplary optical interface device can be coupled one more other optical interconnect devices via a waveguide array and/or a fiber array.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Stefan Rusu, Wei-Wei Song, Mohammed Rabiul Islam, Chih-Tsung Shih
  • Patent number: 12174421
    Abstract: A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: December 24, 2024
    Assignee: POET Technologies, Inc.
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Patent number: 12174422
    Abstract: A second core includes a first portion, a second portion, and a bending portion. In the first portion, a wave-guiding direction is a first direction parallel to a plane of a first substrate. In the second portion, a wave-guiding direction is a second direction that is at a predetermined angle with respect to the plane of the first substrate. For example, in the second portion, the wave-guiding direction is the second direction that is at substantially 90 degrees with respect to the plane of the first substrate. The bending portion connects the first portion and the second portion. A relative refractive index difference between the second core and a cladding of the second optical waveguide preferably has a value such that the propagation loss in the bending portion is equal to or smaller than 0.1 dB.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 24, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Abe, Atsushi Aratake
  • Patent number: 12176958
    Abstract: Provided is a device which includes a method for the coherent detection of an optical signal, including the following steps of providing a vertically illuminable photodiode; producing an optical reference signal; radiating the optical signal and the reference signal into the photodiode in such a way that the two signals at least partially interfere with each other. Radiating the optical signal into the photodiode is effected via a first side of the photodiode, and radiating the reference signal into the photodiode is effected via a second side of the photodiode, or, vice versa, the reference signal is radiated into the photodiode via the first side of the photodiode and the optical signal is radiated into the photodiode via the second side.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: December 24, 2024
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Patrick Runge, Francsico Soares, Pascal Rustige, Jan Krause
  • Patent number: 12174440
    Abstract: An interconnect package integrates a photonic die, an electronic die, and a switch ASIC into one package. At least some of the components in the electronic die, such as, for example, the serializer/deserializer circuits, transceivers, clocking circuitry, and/or control circuitry are integrated into the switch ASIC to produce an integrated switch ASIC. The photonic die is attached and electrically connected to the integrated switch ASIC.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rabiul Islam, Stefan Rusu, Nick Samra
  • Patent number: 12171089
    Abstract: A light-source apparatus includes a light-source chip, a case, first and second electrically-conductive parts, a substrate, an electromagnetic shield plate, an electrically-conductive layer and an electrically-conductive unit. The light-source chip is received in the case. Each of the first and second electrically-conductive parts is a part of the case. The case is mounted to the substrate. The electromagnetic shield plate covers at least part of the substrate. The electrically-conductive layer is formed on the substrate and electrically connected with both the second electrically-conductive part and the electromagnetic shield plate. The electrically-conductive unit is provided to electrically connect the first electrically-conductive part and the electromagnetic shield plate.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: December 17, 2024
    Assignee: DENSO CORPORATION
    Inventor: Kosuke Niimura
  • Patent number: 12164150
    Abstract: In part, in one aspect, the disclosure relates to a method for passivating a waveguide of an optical circuit. The method includes etching a suspended waveguide in the optical circuit; the suspended waveguide having a top surface, a bottom surface, and side surfaces; and covering the top surface and side surfaces of the suspended waveguide with a passivation coating having a thickness that ranges from between about 10 nm to about 20 nm. In one embodiment, the method further includes removing one or more coatings from a portion of the optical circuit. The disclosure also relates to various passivated optical silicon circuit embodiments.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: December 10, 2024
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Li Chen, Long Chen, Christopher Doerr
  • Patent number: 12164148
    Abstract: A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: December 10, 2024
    Assignee: POET Technologies, Inc.
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Patent number: 12153253
    Abstract: An optical device includes a waveguide configured to guide light, a taper integrated with the waveguide on a substrate configured for optical coupling, and an attenuator to degrade unwanted optical signal from the taper. The attenuator extends along one side of the taper, and includes one of a conductive structure, a doped structure and a refractive structure.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, Feng Wei Kuo
  • Patent number: 12149051
    Abstract: In an example embodiment, a system includes a first grating-coupled laser (GCL) that includes a first laser cavity optically coupled to a first transmit grating coupler configured to redirect horizontally-propagating first light, received from the first laser cavity, vertically downward and out of the first GCL. The system also includes a second GCL that includes a second laser cavity optically coupled to a second transmit grating coupler configured to transmit second light vertically downward and out of the second GCL. The system also includes a photonic integrated circuit (PIC) that includes a first receive grating coupler optically coupled to a first waveguide and configured to receive the first light and couple the first light into the first waveguide. The PIC also includes a second receive grating coupler optically coupled to a second waveguide and configured to receive the second light and couple the second light into the second waveguide.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: November 19, 2024
    Assignee: II-VI DELAWARE, INC.
    Inventors: Shiyun Lin, Daniel Mahgerefteh
  • Patent number: 12140825
    Abstract: An optical communication device is configured to include: a laser diode that outputs light; an EA modulator including a cathode and an anode, to modulate the light output from the laser diode on the basis of a high-frequency signal applied between the cathode and the anode; a resistor connected between the cathode and the anode; and a pattern line connected in series with the resistor and having an inductance component, in which each of the laser diode and the EA modulator is formed on a front surface of the high-frequency line substrate or a back surface of the high-frequency line substrate, and the pattern line is formed on a side face of the high-frequency line substrate.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: November 12, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Nobuo Ohata
  • Patent number: 12136797
    Abstract: The upper surface of the semiconductor substrate has a slope descending from the projection in the second direction at an angle of 0-12° to a horizontal plane. The mesa stripe structure has an inclined surface with a slope ascending from the upper surface of the semiconductor substrate at an angle of 45-55° to the horizontal plane, the mesa stripe structure having an upright surface rising from the inclined surface at an angle of 85-95° to the horizontal plane. The buried layer is made from semiconductor with ruthenium doped therein and is in contact with the inclined surface and the upright surface. The inclined surface is as high as 80% or less of height from the upper surface of the semiconductor substrate to a lower surface of the quantum well layer and is as high as 0.3 ?m or more.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: November 5, 2024
    Assignee: Lumentum Operations LLC
    Inventors: Takafumi Taniguchi, Shigenori Hayakawa, Yasushi Sakuma
  • Patent number: 12128729
    Abstract: An optical transceiver includes a silicon photonics substrate and multiple devices. The devices are configured to process optical signals propagating to and from the optical transceiver, and to perform at least one of an optical-to-electrical conversion of received optical signals to incoming electric signals and an electrical-to-optical conversion of outgoing electric signals to transmitted optical signals. The devices are each fabricated to include respectively a package substrate configured according to one of multiple different package substrate mounting technologies. Each package substrate among the multiple devices is mounted on the silicon photonics substrate according to mounting requirements of the respective package substrate mounting technology of that package substrate. At least two of the package substrates are mounted according to the mounting requirements of different package substrate mounting technologies.
    Type: Grant
    Filed: October 13, 2023
    Date of Patent: October 29, 2024
    Assignee: Marvell Asia Pte Ltd
    Inventors: Ding Liang, Mark Patterson, Roberto Coccioli, Radhakrishnan L. Nagarajan
  • Patent number: RE50370
    Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: April 8, 2025
    Assignee: XILINX, INC.
    Inventors: Alireza Kaviani, Pongstorn Maidee, Ivo Bolsens