Integrated Optical Circuit Patents (Class 385/14)
  • Patent number: 12044857
    Abstract: A hybrid reflective/refractive HMD includes a structural frame, refractive optical lens elements, and optics housings coupled to the structural frame and positioned in front of a user's first and second eyes. Light-emitting visual sources and reflective optical surfaces are contained in the optics housings. Visual content is transmitted from light-emitting visual sources to the reflective optical surfaces. The visual content is reflected within the reflective optical surfaces at least four times without passing through a refractive optical lens element. The visual content is transmitted to the user's first eye or the user's second eye. Simultaneous with the transmission of the visual content to the user's first eye or the user's second eye, a real-world view of the outside surrounding environment is transmitted to the user's first eye or the user's second eye. The visual content is overlaid onto the real-world view of the outside surrounding environment.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: July 23, 2024
    Inventor: Douglas Peter Magyari
  • Patent number: 12044892
    Abstract: A semiconductor package includes a first interposer having a first substrate, a first redistribution structure over a first side of the first substrate, and a first waveguide over the first redistribution structure and proximate to a first side of the first interposer, where the first redistribution structure is between the first substrate and the first waveguide. The semiconductor package further includes a photonic package attached to the first side of the first interposer, where the photonic package includes: an electronic die, and a photonic die having a plurality of dielectric layers and a second waveguide in one of the plurality of dielectric layers, where a first side of the photonic die is attached to the electronic die, and an opposing second side of the photonic die is attached to the first side of the first interposer, where the second waveguide is proximate to the second side of the photonic die.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia
  • Patent number: 12038616
    Abstract: A photonic system includes a light source and a photonic structure. The photonic structure includes an optical transmission structure and an optical absorption structure. The optical transmission structure is configured to transmit light associated with a first wavelength range. The optical absorption structure is configured to absorb light associated with a second wavelength range. The light source is configured to provide a light beam with a wavelength that is within the second wavelength range to the optical absorption structure. The optical absorption structure is configured to generate and provide heat to the optical transmission structure when the light beam falls incident on the optical absorption structure.
    Type: Grant
    Filed: July 14, 2023
    Date of Patent: July 16, 2024
    Assignee: VIAVI Solutions Inc.
    Inventor: William D. Houck
  • Patent number: 12040321
    Abstract: An optical device includes an optical component and an electrical component. The optical component has a sensing surface and a backside surface opposite to the sensing surface. The electrical component is disposed adjacent to the backside surface of the optical component and configured to support the optical component. A portion of the backside surface of the optical component is exposed from the electrical component.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: July 16, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsiang-Cheng Tsai, Ying-Chung Chen
  • Patent number: 12032268
    Abstract: An optical modulator in which an optical signal is input from one side of a package, includes in the package, a chip that optically modulates the optical signal and in which an input waveguide and an output waveguide of the optical signal are led to mutually different destinations each being one end of the chip facing the one side of the package and a side surface of the chip orthogonal to the one end of the chip; an input optical system coupled to the input waveguide of the chip; and an output optical system coupled to the output waveguide of the chip.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: July 9, 2024
    Assignee: FUJITSU OPTICAL COMPONENTS LIMITED
    Inventors: Shinji Maruyama, Shuntaro Makino, Yoshimitsu Sakai, Yoshinobu Kubota
  • Patent number: 12025833
    Abstract: Provided is an optical waveguide element that prevents leaked light generated at a forking section from entering a downstream optical waveguide such as another forking section, thereby affording minimal degradation of optical characteristics. The optical waveguide is characterized in that: at least one of two fork waveguides (20a, 20b) forking from a first forking section (20) comprises a second forking section (21, 22); slab waveguides (3c-1 to 3c-3) are formed between the two fork waveguides; and between the first forking section and the second forking section, slits (41, 42) are formed that partition the slab waveguides into a first slab waveguide area (3c-1) close to the first forking section and second slab waveguide areas (3c-2, 3c-3) close to the second forking section(s).
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: July 2, 2024
    Assignee: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Yu Kataoka, Norikazu Miyazaki
  • Patent number: 12007602
    Abstract: In an integrated optical device, squeezed light is used internally to effectively increase an optical modulation effect. One exemplary device operates by squeezing the light at the input, then sending it through an electro-optic stage where its phase picks up the signal of interest, and finally anti-squeezing it to obtain a displaced coherent state. Thus the displacement is amplified by the level of squeezing that is achieved inside the device and it is thereby less sensitive to loss. Since this device behaves simply as an electro-optic modulator, albeit one with an exponentially enhanced sensitivity, no extra considerations are needed to integrate the modulator into a system. Such devices can be operated as modulators or as sensors, and can make use of optical phase shift effects other than the electro-optic effect.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: June 11, 2024
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Amir H. Safavi-Naeini, Timothy Patrick McKenna, Hubert S. Stokowski
  • Patent number: 12001120
    Abstract: An optical device including a plurality of electrodes, an electro-optic component, an optical grating, and a buried back reflector is described. The electro-optic component includes at least one optical material exhibiting an electro-optic effect. The optical grating is optically coupled with the electro-optic component. In some embodiments, the optical grating includes a vertical optical grating coupler. The buried back reflector is optically coupled with the optical grating. The buried back reflector is configured to increase a coupling efficiency of the optical grating to an out-of-plane optical mode and configured to reduce a performance perturbation to the plurality of electrodes. The buried back reflector may include a metal layer having a thickness of at least thirty nanometers and not more than five hundred nanometers.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: June 4, 2024
    Assignee: HyperLight Corporation
    Inventors: Mian Zhang, Kevin Luke, Prashanta Kharel, Christian Reimer, Lingyan He
  • Patent number: 11994426
    Abstract: A photon counting device includes unit cells, a bias current source coupled to the unit cells, and a waveguide coupled to the unit cells. Each unit cell includes photodetector(s). Each photodetector includes superconducting component(s) and a transistor. The transistor includes a superconducting gate that is coupled in parallel with the photodetector(s), and a channel that is electrically isolated from the superconducting gate. For each unit cell, a photodetector is optically coupled to the waveguide. A superconducting component is configured to transition from the superconducting state to the non-superconducting state in response to a photon being incident upon the superconducting component while the superconducting component receives at least a portion of bias current output from the bias current source.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: May 28, 2024
    Assignee: PSIQUANTUM CORP.
    Inventors: Faraz Najafi, Eric Dudley
  • Patent number: 11977256
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor package comprising optically coupled integrated circuit (IC) chips. A first IC chip and a second IC chip overlie a substrate at a center of the substrate. A photonic chip overlies the first and second IC chips and is electrically coupled to the second IC chip. A laser device chip overlies the substrate, adjacent to the photonic chip and the second IC chip, at a periphery of the substrate. The photonic chip is configured to modulate a laser beam from the laser device chip in accordance with an electrical signal from the second IC chip and to provide the modulated laser beam to the first IC chip. This facilitates optical communication between the first IC chip to the second IC chip. Various embodiments of the present disclosure are further directed towards simultaneously aligning and bonding constituents of the semiconductor package.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tsung Shih, Hau-Yan Lu, Wei-Kang Liu, Yingkit Felix Tsui
  • Patent number: 11971592
    Abstract: The present disclosure provides a method for stacking a plurality of optical fibre ribbons in an optical fibre cable. The method includes a step of arranging a plurality of optical fibre ribbon stacks in a hexagonal arrangement in the optical fibre cable. The method may further include stacking the plurality of optical fibre ribbons to form an optical fibre ribbon stack such that the optical fibre ribbon stack may have a parallelogram shape. Each optical fibre ribbon is placed at an offset from adjacent optical fibre ribbon. The optical fibre ribbon stack may have a stack height. In addition, each optical fibre ribbon of the plurality of optical fibre ribbons may have a ribbon height. The hexagonal arrangement may have the packaging density greater than 80%.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: April 30, 2024
    Inventors: Badri Gomatam, Manish Sinha
  • Patent number: 11971757
    Abstract: In embodiments, an electronic device may include a housing, a display panel, and an optical sensor module. The display panel is disposed in an inner space of the housing and is at least partially visible from an outside through the housing, the display including a display area, a first non-display area disposed adjacent to at least a peripheral portion of the display area, and a second non-display area disposed adjacent to at least a peripheral portion of the first non-display area. The optical sensor module is disposed in the inner space at least partially overlapping the display panel, and includes a flexible printed circuit board (FPCB), a light emitting structure disposed on the FPCB at least partially overlapping the first non-display area when the display panel is viewed from above, and a light receiving structure disposed on the FPCB at least partially overlapping the display area when the display panel is viewed from above.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: April 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongah Kim, Jeongho Cho, Heewoong Yoon, Donghan Lee
  • Patent number: 11963291
    Abstract: A packaging assembly and methodology provide a PCB substrate with one or more waveguide apertures and a conductive pattern which includes a plurality of landing pads that are disposed around peripheral edges of each waveguide aperture and that are connected to one another by trace lines so that, upon attachment and reflow of solder balls to the plurality of landing pads, the solder balls reflow along the trace lines to form a fully closed solder waveguide shielding wall disposed around peripheral edges of the first waveguide aperture.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: April 16, 2024
    Assignee: NXP B.V.
    Inventors: Leo van Gemert, Michael B. Vincent
  • Patent number: 11960152
    Abstract: A method for adjusting a transmission wavelength of signal light transmitted through an optical waveguide device provided with one or more optical waveguides through which the signal light having a wavelength of 1520 nm to 1560 nm and blue light having a wavelength of 375 nm to 455 nm pass, a groove through which the waveguide passes, and resin filled in the groove, including a step of passing the signal light and the blue light through the same or mutually different one or more optical waveguides and of passing the signal light and the blue light through the same or mutually different resin, the latter step changing a refractive index of the resin by irradiating the resin with the blue light so as to change the transmission wavelength of the signal light transmitted through the resin in accordance with a change in the refractive index of the resin.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: April 16, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Katsuhiko Hirabayashi, Nobutatsu Koshobu, Satomi Katayose, Ryoichi Kasahara
  • Patent number: 11960131
    Abstract: Described herein is an integrated photonics device including a light emitter, integrated edge outcoupler(s), optics, and a detector array. The device can include a hermetically sealed enclosure. The hermetic seal can reduce the amount of moisture and/or contamination that may affect the measurement, analysis, and/or the function of the individual components within the sealed enclosure. Additionally or alternatively, the hermetic seal can be used to protect the components within the enclosure from environmental contamination induced during the manufacturing, packaging, and/or shipping process. The outcoupler(s) can be formed by creating one or more pockets in the layers of a die. Outcoupler material can be formed in the pocket and, optionally, subsequent layers can be deposited on top. The edge of the die can be polished until a targeted polish plane is achieved. Once the outcoupler is formed, the die can be flipped over and other components can be formed.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: April 16, 2024
    Inventors: Michael J. Bishop, Vijay M. Iyer, Jason S. Pelc, Mario J. Costello
  • Patent number: 11953725
    Abstract: A device includes a dielectric layer, a plurality of grating structures, and a dielectric material between the plurality of grating structures and on top of the plurality of grating structures. The grating structures are arranged on the dielectric layer and separated from each other, the plurality of grating structures each having a bottom portion and top portion, the top portion having a first width and the bottom portion having a second width, the second width being larger than the first width.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Wei Kuo, Chewn-Pu Jou, Hsing-Kuo Hsia
  • Patent number: 11953727
    Abstract: A device coupon for use in a hybrid integration process with a silicon platform. The device coupon comprises: an input waveguide, including an input facet; an active waveguide, coupled to the input waveguide, the active waveguide including a III-V semiconductor based electro-optical device; and an output waveguide, configured to couple light between the active waveguide and an output facet. The input waveguide and output waveguide are passive waveguides.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Rockley Photonics Limited
    Inventors: Guomin Yu, Aaron John Zilkie
  • Patent number: 11947200
    Abstract: The present disclosure relates to optical phase modulation devices. The optical phase modulation devices may include a heater resistance which induces a phase change and control systems and methods of controlling the induced phase change.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 2, 2024
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Quazi Ikram, Ronald Scott Karfelt, Steven Nguyen, Nicholas Karfelt, Saman Jafarlou, Swetha Babu
  • Patent number: 11947172
    Abstract: An optical probe package structure is provided, used in a test environment for testing a plurality of optical chips on a wafer, including: a main body, an optical fiber, an optical fiber positioning area, a mode field conversion waveguide structure, and an optical waveguide. Wherein, the mode field conversion waveguide structure is used to convert the propagation field of the optical signal, and the optical signal transmitted by the mode field conversion waveguide structure enters the optical waveguide. The optical waveguide has an emitting end, and the emitting end is provided with a facet, the facet has a facet angle, and the facet angle makes the optical signal after field conversion mode field conversion to produce total reflection and output along a second direction. The optical signal after total reflection enters the optical chips. Thereby, an optical probe package structure that can test before wafer cutting and polishing is provided.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: April 2, 2024
    Assignee: FOCI FIBER OPTIC COMMUNICATIONS, INC.
    Inventors: Ting-Ta Hu, Hsu-Liang Hsiao, Po-Yi Wu
  • Patent number: 11934022
    Abstract: A photoelectric fiber includes a fiber including a core through which light is guided; an electrical unit formed continuously with the fiber, the electrical unit being configured to house a photoelectric conversion chip including a photoelectric conversion element; and an external electrode formed on a front surface of at least one of the fiber or the electrical unit, wherein the photoelectric conversion chip is optically connected to the core and electrically connected to the external electrode.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: March 19, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Norio Sato, Atsushi Aratake, Makoto Abe, Takuya Tanaka, Kota Shikama, Takao Fukumitsu, Hiroshi Ishikawa
  • Patent number: 11934007
    Abstract: An assembly of an active semiconductor component and of a silicon-based passive optical component includes a carrier; and the active semiconductor component and the passive optical component both arranged on the carrier. The active semiconductor component includes a first set of semiconductor layers comprising at least one first waveguide configured to guide, in a first section of the assembly, at least one first optical mode; a second set of semiconductor layers, the set being superposed and making contact with the first set of layers, and including at least one second waveguide configured to guide at least one second optical mode. At least some of the layers of the first set of layers and of the second set of layers are doped to form, in a first region of the component, a PIN diode. The at least one first waveguide and the at least one second waveguide are configured to allow evanescent coupling therebetween, in a second section of the assembly.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: March 19, 2024
    Assignee: ALMAE TECHNOLOGIES
    Inventors: Hélène Debregeas, François Lelarge, David Carrara
  • Patent number: 11929357
    Abstract: An optoelectronic package structure is provided. The optoelectronic package includes a carrier, an electronic component, a photonic component and a first power supply path in the carrier. The carrier includes a first region and the electronic component is disposed over the first region of the carrier. A first power supply path is electrically connects the electronic component.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: March 12, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jr-Wei Lin, Mei-Ju Lu
  • Patent number: 11914264
    Abstract: Photonic ring modulators with high tuning efficiency and small footprint can be formed in a hybrid material platform from a silicon bus waveguide vertically coupled to an optically active compound semiconductor (e.g., III-V) ring resonator. The performance of the modulator, e.g., in terms of the tuning efficiency and the maximum insertion loss, may be optimized by suitable levels of an applied bias voltage and a heater power of a heater optionally included in the ring modulator. The disclosed hybrid photonic ring modulators may be used, e.g., in photonic transceiver circuits with high lane count.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: February 27, 2024
    Assignee: OpenLight Photonics, Inc.
    Inventors: John Parker, Jonathan Edgar Roth, Gregory Alan Fish
  • Patent number: 11914201
    Abstract: A multi-chip photonic assembly includes first and second photonic integrated circuits having first and second waveguides vertically stacked such that first vertical dimensions of the first and second waveguides occupy different horizontal planes in the stack. At least one of the first and second waveguides has a region that has a second vertical dimension that is larger than the first vertical dimension and either horizontally overlaps the other waveguide and/or vertically contacts the other waveguide. Light moving through one of the waveguides from the first vertical dimension to the other vertical dimension changes modes vertically so that the light moves from one waveguide to the other.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: February 27, 2024
    Assignee: Apple Inc.
    Inventors: Jeremy D. Witmer, Alfredo Bismuto
  • Patent number: 11906802
    Abstract: An apparatus includes a substrate that includes one or more routing layers, and an optical module coupled to the substrate. The optical module includes a photonic integrated circuit (PIC) and electronic integrated circuit (EIC), wherein the photonic integrated circuit is at least partially embedded within the substrate. The apparatus further includes a fiber optic coupler coupled to at least one of the substrate or PIC, wherein the PIC is configured to transmit or receive an optical signal via the fiber optic coupler.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: February 20, 2024
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Mayank Mayukh, Sam Zhao, Sam Karikalan, Reza Sharifi, Liming Tsau, Arun Ramakrishnan, Dharmendra Saraswat
  • Patent number: 11899254
    Abstract: A photonic integrated circuit including an InP-based substrate that is provided with a first InP-based optical waveguide and a neighboring second InP-based optical waveguide, a dielectric planarization layer that is arranged at least between the first optical waveguide and the second optical waveguide. At least between the first optical waveguide and the neighboring second optical waveguide, the dielectric planarization layer is provided with a recess that is arranged to reduce or prevent optical interaction between the first optical waveguide and the second optical waveguide via the dielectric planarization layer. At the location of the recess, the dielectric planarization layer has a first sidewall that is arranged sloped towards the first optical waveguide, and a second sidewall that is arranged sloped towards the second optical waveguide. An opto-electronic system including said PIC.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: February 13, 2024
    Assignee: EFFECT PHOTONICS B.V.
    Inventor: Tsjerk Hans Hoekstra
  • Patent number: 11892678
    Abstract: A photonic device includes a silicon layer, wherein the silicon layer extends from a waveguide region of the photonic device to a device region of the photonic device, and the silicon layer includes a waveguide portion in the waveguide region. The photonic device further includes a cladding layer over the waveguide portion, wherein the device region is free of the cladding layer. The photonic device further includes a low refractive index layer in direct contact with the cladding layer, wherein the low refractive index layer comprises silicon oxide, silicon carbide, silicon oxynitride, silicon carbon oxynitride, aluminum oxide or hafnium oxide. The photonic device further includes an interconnect structure over the low refractive index layer.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Ying Wu, Yuehying Lee, Sui-Ying Hsu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
  • Patent number: 11894312
    Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
  • Patent number: 11886004
    Abstract: Provided is a planar lightwave circuit in which stress on a substrate is reduced to decrease the curve of the substrate. The planar lightwave circuit is formed by layering a glass film on the substrate. When the optical axis direction from an input waveguide toward an output waveguide is in the longitudinal direction of the substrate, a plurality of grooves are formed in a line in the transverse direction of the substrate.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: January 30, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Junji Sakamoto, Toshikazu Hashimoto
  • Patent number: 11874497
    Abstract: A photonic chip and a preparation method thereof are provided. The chip includes a lithium niobate film modulator array, a first optical coupling array, and a silica waveguide wavelength-division multiplexer, and the lithium niobate film modulator array includes one or more lithium niobate film modulators and is used to modulate an optical signal; the first optical coupling array includes one or more first optical coupling structures, and the first optical coupling structure has one end connected to a corresponding lithium niobate thin film modulator and the other end connected to the silica waveguide wavelength-division multiplexer so as to transmit the modulated optical signal to the silica waveguide wavelength-division multiplexer; and the silica waveguide wavelength-division multiplexer is used to perform wavelength-division multiplexing on the modulated optical signal.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: January 16, 2024
    Assignee: INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES
    Inventors: Lin Yang, Shanglin Yang, Lei Zhang
  • Patent number: 11874495
    Abstract: A monolithic InP-based PIC having a first photonic assembly that has a first optical splitter-combiner unit having a first end part that is optically connected with a first optical waveguide and a second end part that is optically connected with a first main photonic circuit and a first auxiliary photonic circuit. The first auxiliary photonic circuit has a first laser unit, and a first SOA. The first SOA is configurable to be in a first operational state in which the first SOA allows optical communication between the first laser unit and the first optical splitter-combiner unit, or a second operational state in which the first SOA prevents optical communication between the first laser unit and the first optical splitter-combiner unit. An opto-electronic system including the PIC.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: January 16, 2024
    Assignee: EFFECT PHOTONICS B.V.
    Inventors: Tim Koene, Niall Patrick Kelly
  • Patent number: 11860412
    Abstract: Embodiments include a photonic device with a compensation structure. The photonic device includes a waveguide with a refractive index which changes according to the thermo-optic effect as a temperature of the photonic device fluctuates. The compensation structure is positioned on the photonic device to counteract or otherwise alter the thermo-optic effect on the refractive index of the waveguide in order to prevent malfunctions of the photonic device.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: January 2, 2024
    Assignee: Cisco Technology, Inc.
    Inventors: Subal Sahni, Kamal V. Karimanal, Gianlorenzo Masini, Attila Mekis, Roman Bruck
  • Patent number: 11841598
    Abstract: A optical modulator with reduced with a reduced amount of ripple is provided. A Mach-Zehnder optical modulator includes a phase modulation unit including optical waveguides having a PN junction structure and traveling wave electrodes, and a dummy phase modulation unit including portions of the traveling wave electrodes, the portions being obtained by forming the respective traveling wave electrodes longer than the phase modulation unit in the light propagation direction of the phase modulation unit, and optical waveguides having the same PN junction structure as that of the optical waveguides of the phase modulation unit and not connected to the optical waveguides of the phase modulation unit.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: December 12, 2023
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Masayuki Takahashi, Ken Tsuzuki, Toshihiro Ito, Kiyofumi Kikuchi
  • Patent number: 11841562
    Abstract: Electro-optic modulation of multiple phase modulator waveguides with a single electrode is made possible by determining places of equal electric field strength. Substrate extensions support edges of a wide hot electrode and ground electrodes equally spaced from the wide hot electrodes. Waveguides are positioned in the extensions separated from the electrodes by buffer layers. A wide microstrip hot electrode on a buffer layer, wider substrate and ground has multiple waveguides in the substrate below the buffer layer. A thinned substrate has a microstrip hot electrode and spaced coplanar grounds with multiple waveguides located on both sides. Decreasing substrate thickness flattens the electric field strength between the electrodes and allows multiple waveguides located between the central hot and outer ground electrodes. Adjacent waveguides with different asymmetric waveguide index portion staged along their length eliminate cross talk.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 12, 2023
    Assignee: EOSPACE INC.
    Inventors: David Emil Moilanen, Suwat Thaniyavarn, Walter Charczenko
  • Patent number: 11841533
    Abstract: Disclosed is a structure including a first waveguide core with a first end portion and a second waveguide core with a second end portion, which overlays and is physically separated from the first end portion. The structure includes a coupler configured for interlayer waveguide coupling. Specifically, the coupler includes an additional waveguide core stacked vertically between and physically separated from the first end portion and the second end portion. Optionally, the coupler includes multiple additional waveguide cores. The shapes of the various waveguide cores are configured in order to achieve mode matching so that optical signals pass between the first end portion of the first waveguide core and the second end portion of the second waveguide core through each additional waveguide core in sequence. Also disclosed is a structure including a crossing array implemented using couplers.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: December 12, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventor: Yusheng Bian
  • Patent number: 11841563
    Abstract: The present disclosure relates to electro-optic modulators that include caps for optical confinement. One example embodiment includes an electro-optic modulator. The electro-optic modulator includes a first cladding layer. The electro-optic modulator also includes a second cladding layer. In addition, the electro-optic modulator includes a first waveguide. The first waveguide is at least partially encapsulated between the first cladding layer and the second cladding layer. Further, the electro-optic modulator includes a thin-film lithium niobate layer adjacent to the second cladding layer. The thin-film lithium niobate layer is on an opposite side of the second cladding layer from the first waveguide. Additionally, the electro-optic modulator includes a first cap positioned on an opposite side of the thin-film lithium niobate layer from the second cladding layer. The first cap enhances optical confinement within the thin-film lithium niobate layer.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: December 12, 2023
    Assignee: IMEC USA NANOELECTRONICS DESIGN CENTER, Inc.
    Inventors: Swapnajit Chakravarty, Reza Safian
  • Patent number: 11836102
    Abstract: Matrix multiplication process is segregated between two separate dies—a memory die and a compute die to achieve low latency and high bandwidth artificial intelligence (AI) processor. The blocked matrix-multiplication scheme maps computations across multiple processor elements (PE) or matrix-multiplication units. The AI architecture for inference and training includes one or more PEs, where each PE includes memory (e.g., ferroelectric (FE) memory, FE-RAM, SRAM, DRAM, MRAM, etc.) to store weights and input/output I/O data. Each PE also includes a ring or mesh interconnect network to couple the PEs for fast access of information.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: December 5, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Amrita Mathuriya, Rajeev Kumar Dokania, Ananda Samajdar, Sasikanth Manipatruni
  • Patent number: 11835781
    Abstract: A cable assembly may include a first end and a second end. The first end may include a first breakout including a plurality of transmissive conduits implementing a plurality of communications channels and a second breakout including a plurality of conduits implementing a plurality of communications channels. The second end may include a third breakout including a plurality of conduits implementing a plurality of communications channels and a fourth breakout including a plurality of conduits implementing a plurality of communications channels. Communication channels of the first breakout, second breakout, third breakout, and fourth breakout may be arranged such that the first breakout shares a first communications channel with the third breakout, the first breakout shares a second communications channel with the fourth breakout, the second breakout shares a third communications channel with the third breakout, and the second breakout shares a fourth communications channel with the fourth breakout.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: December 5, 2023
    Assignee: Dell Products L.P.
    Inventors: David Piehler, Per Fremrot
  • Patent number: 11837620
    Abstract: A photo receiver includes a photo detector including a semiconductor substrate having a first main surface and a second main surface and a metal pattern layer provided on the second main surface; and a carrier including a supporting substrate having a third main surface facing the second main surface and a solder pattern layer provided on the third main surface. The solder pattern layer is bonded to the metal pattern layer. The first main surface is provided with a variable optical attenuator, an optical 90-degree hybrid device, and a plurality of photodiodes optically coupled to the variable optical attenuator via the optical 90-degree hybrid device. The solder pattern layer and the metal pattern layer are located in a peripheral area surrounding a central area where the variable optical attenuator and the optical 90-degree hybrid device are located when viewed in the normal direction of the first main surface.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: December 5, 2023
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hideki Yagi, Takuya Okimoto, Munetaka Kurokawa
  • Patent number: 11835765
    Abstract: A structure of a silicon photonics device for LIDAR includes a first insulating structure and a second insulating structure disposed above one or more etched silicon structures overlying a substrate member. A metal layer is disposed above the first insulating structure without a prior deposition of a diffusion barrier and adhesion layer. A thin insulating structure is disposed above the second insulating structure. A first configuration of the metal layer, the first insulating structure and the one or more etched silicon structures forms a free-space coupler. A second configuration of the thin insulating structure above the second insulating structure forms an edge coupler.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: December 5, 2023
    Assignee: Aurora Operations, Inc.
    Inventors: Sen Lin, Andrew Steil Michaels
  • Patent number: 11828983
    Abstract: Structures for a cavity included in a photonics chip and methods of fabricating a structure for a cavity included in a photonics chip. The structure includes a substrate, a back-end-of-line stack having interlayer dielectric layers on the substrate, and a cavity penetrating through the back-end-of-line stack and into the substrate. The cavity includes first sidewalls and second sidewalls, and the second sidewalls have an alternating arrangement with the first sidewalls to define non-right-angle corners.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: November 28, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Ian Melville, Nicholas Polomoff, Thomas Houghton, Koushik Ramachandran, Pallabi Das
  • Patent number: 11831124
    Abstract: The disclosure belongs to the technical field of photoelectric emission in semiconductors, and discloses an electro-absorption modulated laser chip and a fabrication method thereof, which can solve the problems of signal distortion caused by optical crosstalk between components in an existing electro-absorption modulated laser (EML) integrated with a semiconductor optical amplifier (SOA), and failure in longer-distance transmission.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: November 28, 2023
    Assignee: Yuanjie Semiconductor Technology Co., Ltd.
    Inventors: Mahui Li, Yenting Pan, Yao Mu, Yuchen Shi, Haichao Zhang
  • Patent number: 11822122
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to waveguide structures with metamaterial structures and methods of manufacture. The structure includes: at least one waveguide structure; and metamaterial structures separated from the at least one waveguide structure by an insulator material, the metamaterial structures being structured to decouple the at least one waveguide structure to simultaneously reduce insertion loss and crosstalk of the at least one waveguide structure.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: November 21, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob, Steven M. Shank
  • Patent number: 11824327
    Abstract: A photonic integrated circuit (PIC) assembly comprising a semiconductor optical amplifier (SOA) array and a U-turn chip. The SOA array includes an input SOA and a plurality of SOAs. The input SOA and the plurality of SOAs are arranged parallel to one another. The U-turn chip includes an optical splitter and a waveguide assembly. The optical splitter is configured to receive amplified input light propagating in a first direction from the input SOA, and divide the amplified light into beams. The waveguide assembly guides the beams to a corresponding SOA of the plurality of SOAs, and adjusts a direction of prorogation of each of the guided beams to be substantially parallel to a second direction that is substantially opposite the first direction.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: November 21, 2023
    Assignee: OURS TECHNOLOGY, LLC
    Inventors: Andrew Steil Michaels, Lei Wang, Sen Lin
  • Patent number: 11822120
    Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes a waveguide core and a back-end-of-line stack including a first metallization level, a second metallization level, and a heat sink having a metal feature in the second metallization level. The heat sink is positioned adjacent to a section of the waveguide core. The first metallization level including a dielectric layer positioned between the metal feature and the section of the waveguide core.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: November 21, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Hemant Dixit, Yusheng Bian, Theodore Letavic
  • Patent number: 11824029
    Abstract: A semiconductor package structure includes a first semiconductor die having an active surface and a passive surface opposite to the active surface, a conductive element leveled with the first semiconductor die, a first redistribution layer (RDL) being closer to the passive surface than to the active surface, a second RDL being closer to the active surface than to the passive surface, and a second semiconductor die over the second RDL and electrically coupled to the first semiconductor die through the second RDL. A first conductive path is established among the first RDL, the conductive element, the second RDL, and the active surface of the first semiconductor die.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: November 21, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi-Han Chen, Hung-Yi Lin
  • Patent number: 11815725
    Abstract: An example photonic integrated circuit includes a transmitter circuit with a optical communication path to an optical coupler configured to couple with an optical fiber. The optical communication path has a propagation direction away from the transmitter circuit and towards the optical coupler. A counter-propagating tap diverts light sent by a light source backward against the propagation direction of the optical communication path. A photodiode receives the diverted light and measures its power level. The photodiode generates a feedback signal for the optical coupler and provides the feedback signal to the optical coupler. The optical coupler receives the feedback signal and adjusts a coupling alignment of the optical communication path to the optical fiber based on the feedback signal, which indicates the measured power level of the diverted counter-propagating light.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: November 14, 2023
    Assignee: OpenLight Photonics, Inc.
    Inventors: Brandon W. Buckley, Brian Robert Koch, John Garcia, Jared Bauters, Sudharsanan Srinivasan, Anand Ramaswamy
  • Patent number: 11808979
    Abstract: A method of fabricating a device coupon including a waveguide which is suitable for use in a micro-transfer printing process. The method comprises the steps, on a wafer, of: depositing a lower cladding layer on an uppermost surface of the wafer; providing a silicon nitride guiding layer on an uppermost surface of the lower cladding; depositing an upper cladding over at least an uppermost surface of the silicon nitride guiding layer; providing a tether over the coupon, and etching away a region of the uppermost layer of the wafer located between the lower cladding layer and a substrate of the wafer, thereby leaving the lower cladding layer, silicon nitride guiding layer, and upper cladding layer suspended above the wafer via the tether.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 7, 2023
    Assignee: Rockley Photonics Limited
    Inventors: Guomin Yu, Aaron John Zilkie
  • Patent number: 11803016
    Abstract: Structures for an edge coupler and methods of fabricating such structures. The structure includes a substrate, a waveguide core, and a metamaterial layer positioned in a vertical direction between the substrate and the waveguide core. The metamaterial layer includes a plurality of elements separated by a plurality of gaps and a dielectric material in the plurality of gaps.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: October 31, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventor: Yusheng Bian
  • Patent number: 11796351
    Abstract: Some embodiments of the disclosure provide a demodulation system for obtaining phase change parameters by a fiber-optic Fabry Perot sensor. In an embodiment, the demodulation system includes a transmitting module, a fiber-optic Fabry Perot sensor, a light splitting module, a filter module, a receiving module, and a processing module. The transmitting module transmits a beam with a predetermined wavelength range. The fiber-optic Fabry Perot sensor receives the beam and forms a reflected light beam. The light splitting module is arranged between the transmitting module and the fiber-optic Fabry Perot sensor. The filter module obtains the first light beam, the second light beam, and the third light beam. The filter module has a broadband filter. The receiving module receives the first light beam, the second light beam, and the third light beam and converts them into the first signal, the second signal, and the third signal.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: October 24, 2023
    Assignee: North University of China
    Inventors: Pinggang Jia, Jijun Xiong, Qianyu Ren, Jia Liu, Guowen An, Wenyi Liu