Including Wafer Orienting Means Patents (Class 414/936)
  • Patent number: 5404894
    Abstract: A thermal processing station is provided with a first conveyor that conveys a wafer from a first conveyor access portion and a second conveyor that conveys another wafer from a second conveyor access opening portion. The wafer conveyed from the first conveyor is conveyed along a route consisting of the second conveyor, a washing portion, the second conveyor again, the first conveyor, and a thermal processing portion. On the other hand, the wafer conveyed from the second conveyor is conveyed along a route consisting of the washing portion, the second conveyor again, the first conveyor, and the thermal processing portion. An intermediate transfer portion that is free to rotate and rise and lower is provided between the first and second conveyor. A control section does not rotate the intermediate transfer portion while the wafer is being transferred along the former route, but it does rotate the intermediate transfer portion through 180.degree.
    Type: Grant
    Filed: May 18, 1993
    Date of Patent: April 11, 1995
    Assignees: Tokyo Electron Kabushiki Kaisha, Tokyo Electron Tohoku Kabushiki Kaisha
    Inventor: Hirotsugu Shiraiwa
  • Patent number: 5405230
    Abstract: A load-lock unit is disposed between first and second atmospheres, stores a wafer transferred from the first atmosphere, is blocked off from the first atmosphere, is thereafter set in the same atmosphere as or a similar atmosphere to the second atmosphere, and is opened to communicate with the second atmosphere in order to transfer the wafer to the second atmosphere. The load-lock unit includes a load-lock chamber, a storing device, disposed in the load-lock chamber, for storing a plurality of wafers vertically at a gap, a holding mechanism for holding one of the plurality of wafers stored in the storing device, a rotating mechanism for rotating the wafer held by the holding mechanism, and an error detecting device for detecting the positional error of the center of the wafer and an orientation error of the wafer on the basis of data obtained by radiating light on the wafer which is rotating.
    Type: Grant
    Filed: March 26, 1992
    Date of Patent: April 11, 1995
    Assignee: Tokyo Electron Limited
    Inventors: Hiroo Ono, Tetsu Oosawa, Teruo Asakawa, Kenji Nebuka
  • Patent number: 5399531
    Abstract: A manufacturing system and method for processing semiconductor wafers through a plurality of processing stations that perform manufacturing operations on wafers includes a plurality of processing stations, each of which are capable of performing at least one processing operation on a wafer, each of the processing stations having a controlled environment for processing the wafers, and a branched tunnel joined and communicating with the controlled environment. A means is provided for maintaining a clean environment in the tunnel. Within the tunnel there are provided a plurality of guided transport vehicles adapted to travel between the process stations. A plurality of wafer carriers, each adapted to support a single wafer and be carried by the transport vehicles, are part of the system.
    Type: Grant
    Filed: December 17, 1990
    Date of Patent: March 21, 1995
    Assignee: United Micrpelectronics Corporation
    Inventor: H. J. Wu
  • Patent number: 5383759
    Abstract: Disclosed is an apparatus and method for aligning the flat edges of semiconductor wafers in a wafer cassette. The apparatus includes a roller and alignment blade mounted in a frame on which the wafer cassette is mounted. A motor mechanism rotates the roller and alignment blade to align the wafer flat edges.
    Type: Grant
    Filed: August 20, 1993
    Date of Patent: January 24, 1995
    Inventor: Gaille Lin
  • Patent number: 5374147
    Abstract: A device for transferring a LCD substrate under a reduced pressure atmosphere comprises a first stage on which the LCD substrate is mounted such that the surface of the LCD substrate is substantially horizontal, a multi-joint arm mechanism for mounting the LCD substrate on a second stage of a delivery position after moving the first stage in substantially horizontal plane, a mechanism for pushing the LCD substrate on the first and second stages, and for positioning the LCD substrate at a home position.
    Type: Grant
    Filed: September 10, 1992
    Date of Patent: December 20, 1994
    Assignees: Tokyo Electron Limited, Tokyo Electron Yamanashi Limited
    Inventors: Tsutomu Hiroki, Teruo Asakawa
  • Patent number: 5340261
    Abstract: A load-lock unit is disposed between first and second atmospheres, for storing a wafer transferred from the first atmosphere, and which is blocked off from the first atmosphere, thereafter being set in an atmosphere at least substantially similar to the second atmosphere, and opened so as to communicate with the second atmosphere in order to transfer the wafer to the second atmosphere. The load-lock unit includes a load-lock chamber, a holding mechanism, disposed in the load-lock chamber for holding the wafer, a rotating mechanism for rotating the wafer held by the holding mechanism, and an error detecting mechanism for detecting a positional error of the center of the wafer and an orientation error of the wafer on the basis of data obtained by radiating light on the wafer which is rotating.
    Type: Grant
    Filed: March 26, 1992
    Date of Patent: August 23, 1994
    Assignee: Tokyo Electron Limited
    Inventors: Tetsu Oosawa, Teruo Asakawa, Kenji Nebuka, Hiroo Ono
  • Patent number: 5308993
    Abstract: A wafer cassette mapper detects the presence or absence of a wafer in a particular corresponding pair of slots in a wafer cassette, as well as a cross slotted condition in which a wafer is not aligned in a corresponding pair of slots. The wafer cassette mapper includes a base member for receiving a standard slotted wafer cassette, the base member supporting a transmitter/receiver module adjacent the rear of the wafer cassette. The transmitter/receiver module includes two vertical columns of light emitting apertures, coupled to an infrared transmitter array, and a single vertical column, between the two columns of light emitting apertures, of light receiving apertures coupled to an infrared receiver array. Corresponding light emitting apertures in each of the two columns are positioned to illuminate the rear edge of each of the wafers in the wafer cassette at an angle that will cause the diffused reflected light to enter an associated one of the light receiving apertures.
    Type: Grant
    Filed: March 28, 1993
    Date of Patent: May 3, 1994
    Assignee: Avalon Engineering, Inc.
    Inventors: George T. Holman, Ronald E. Logan
  • Patent number: 5308222
    Abstract: A prealigner (10) employs an X-Y stage (20) and a rotary stage (26) to position and orient a specimen (12) without centering it on the prealigner. In a preferred embodiment, the rotary stage is mounted on the X-Y stage and receives a semiconductor (12) in a substantially arbitrary position and orientation. The prealigner employs the rotary stage and translation in only an X-axis direction to scan the peripheral edge (76) of the wafer across an optical scanning assembly (36) to form a polar coordinate map of the wafer. A microprocessor (162) determines the location and orientation of the wafer from the map and cooperates with a motor drive controller (122) to generate control signals for positioning and orienting the wafer in the preselected alignment without changing the location at which the wafer is held.
    Type: Grant
    Filed: May 17, 1991
    Date of Patent: May 3, 1994
    Assignee: Kensington Laboratories, Inc.
    Inventors: Paul E. Bacchi, Paul S. Filipski
  • Patent number: 5295777
    Abstract: A wafer transport module interconnects a horizontal wafer handler with a vertical wafer processor and includes an evacuatable housing with a first port in communication with the horizontal wafer handler and sized to permit passage of a wafer therethrough in horizontal orientation and a second port in communication with a load/unload station of the vertical wafer processor and sized to permit passage of wafers therethrough in vertical orientation. The transport module includes a wafer holder which supports a wafer on a pedestal and rotates the pedestal and wafer about an inclined axis between horizontal orientation adjacent the first port and vertical orientation adjacent and in alignment with the second port. The wafer holder horizontally extends the vertically oriented platen and wafer from the second position through the second port to the load/unload station of the vertical processor. After wafer processing, the sequence is reversed to return the wafer to the horizontal wafer handler.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: March 22, 1994
    Assignee: Materials Research Corporation
    Inventor: Julian Hodos