Including A Masking Coating Patents (Class 427/259)
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Patent number: 4717639Abstract: Process for formation of a hardened, insoluble or crosslinked stencil or resist image on a substrate, e.g., having a metal surface such as copper, and modifying the substrate or image surface comprising:A. forming an image on the substrate by applying a solvent-soluble thermoplastic copolymer of ethylene and .alpha.,.beta.-ethylenically unsaturated acid having an acid number of at least about 30, the copolymer reacting thermochemically with the substrate;B. fusing at a temperature and for a duration to induce the thermochemical reaction at a rate sufficient to partially insolubilize, harden or crosslink the polymeric image and adhere the polymeric image to the substrate surface to facilitate subsequent removal therefrom;C. modifying the uncovered substrate surface or the polymeric image surface, e.g., etching, plating, depositing, soldering; andD. removing the polymeric image.The image can be formed on the substrate by printing, electrostatic means, etc.Type: GrantFiled: December 6, 1985Date of Patent: January 5, 1988Assignee: E. I. Du Pont De Nemours and CompanyInventors: Alan S. Dubin, Robert A. McMillen, R. David Mitchell
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Patent number: 4716049Abstract: Apparatus is disclosed for providing microelectronic, intra-chip and chip-to-chip interconnections in an ultra-dense integrated circuit configuration. Compressive pedestals 20 are used to form spring-loaded electrical and mechanical interconnections to conductive terminals on a chip interface mesa and chip assembly 28 in order to form a large multi-chip array 23 on an interconnection substrate 24. Methods are also disclosed for fabricating the compressive pedestals 20.Type: GrantFiled: June 30, 1986Date of Patent: December 29, 1987Assignee: Hughes Aircraft CompanyInventor: Nils E. Patraw
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Patent number: 4714518Abstract: A method for providing a dual layer diffusion mask or encapsulation coating for use with III-V compound semiconductors, the dual layer coating comprising an inner layer of silicon which closely matches the coefficient of thermal expansion of the III-V compound semiconductor and an outer layer of silicon nitride which is relatively impermeable to subsequent metallization and for thereafter applying metallized contacts to the III-V compound semiconductor through selectively etched openings in the diffusion mask or encapsulation coating.Type: GrantFiled: January 14, 1987Date of Patent: December 22, 1987Assignee: Polaroid CorporationInventors: Arumugam Satyanarayan, Aland K. Chin
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Patent number: 4702942Abstract: A process for the preparation of works of art comprises removing portions of a protective cover paper from a first surface of a clear plexiglass panel, spray painting the thus exposed surface areas of the panel while the remaining protective paper functions as a mask, repeating the steps of partial removal of the protective paper and paintaing until a completed design has been formed on the rear surface of the panel and then peeling the protective cover paper from the front surface of the plexiglass panel to permit viewing of the work of art.Type: GrantFiled: March 3, 1986Date of Patent: October 27, 1987Inventor: Timothy J. Wood
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Patent number: 4699811Abstract: Chromium is employed as the mask in selective electroless plating of nickel or copper on a substrate. The chromium is applied conveniently by electroplating in the case of conductive substrates or by sputtering in the case of non-conductive substrates.Type: GrantFiled: September 16, 1986Date of Patent: October 13, 1987Assignee: MacDermid, IncorporatedInventor: David J. Kunces
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Patent number: 4678738Abstract: A process for manufacturing a member having a wear resistant sliding surface. The process includes the steps of providing a metallic substrate having a surface covered by a photo-resist coating, forming the photo-resist coating with a pattern of hard and soft portions, removing the photo-resist coating at the soft portions to expose surface portions of the metallic substrate beneath the soft portions of the photo-resist coating, etching the metallic substrate with the hard portion of the photo-resist coating retained thereon to form pits in the surface portions of the metallic substrate, spraying molten filler material on the surface of the metallic substrate with the hard portion of the photo-resist coating thereon, to fill the pits with the filler material of a porous structure having an oil-retaining capability, and removing the hard portion of the photo-resist coating from the metallic substrate.Type: GrantFiled: January 17, 1986Date of Patent: July 7, 1987Assignee: Mazda Motor CorporationInventors: Tsutomu Shimizu, Kouji Tarumoto, Satoshi Nanba
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Patent number: 4663186Abstract: Disclosed is a screening paste for covering a selected portion of a metallurgical pattern on a substrate while leaving other metallurgy uncovered. The paste is free of polymers and consists, in one example, of 75-80% of a ceramic particulate (such as alumina), 2-8% amorphous fumed silica and 15-20% of linear alcohol. The linear alcohol serves as a vehicle to deliver the solid particles in the paste. In use, after covering the selected portion of the metallurgical pattern with the paste, the alcohol content therein is expelled by subjecting to vacuum treatment at room temperature or heating to a low temperature below about 275.degree. C. thereby obtaining an inert, dry and crack-free protective coating. Upon evaporation of a new metal layer onto the substrate and removal of the protective coating and new metal layer from everywhere except the uncovered metallurgy, the metallurgical pattern is selectively coated with the new metal.Type: GrantFiled: April 24, 1986Date of Patent: May 5, 1987Assignee: International Business Machines CorporationInventors: Richard F. Indyk, Francisco J. Lamelas, Mark O. Neisser
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Patent number: 4663192Abstract: A process for preparing a transparent electrode substrate comprising forming, on an insulated transparent substrate film (A), a polymer compound layer (B) formed from at least one class consisting of polyurethane resin, a polyester resin and an epoxy resin, forming partly thereon a water-soluble coating layer (C), further forming conductive layer (D) having a surface electric resistance of 10 to 10.sup.4 ohm/.quadrature., and dissolving and removing the water-soluble coating layer (C) and the transparent conductive layer (D) thereon by the aid of washing.Type: GrantFiled: October 22, 1985Date of Patent: May 5, 1987Assignee: Nissha Printing Co., Ltd.Inventors: Hiroshi Hatakeyama, Masayuki Ogawa, Kozo Matsumura, Eiji Nakagawa
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Patent number: 4643912Abstract: A method for forming a metal layer with a positive pattern on a plastic sheet or plate substrate which comprises printing an oil-soluble, water-insoluble ink on the substrate to provide a negative pattern, forming a metal layer on said substrate by dry metal plating, immersing the substrate in a hydrocarbon having 6-17 carbon atoms, preferably kerosene, and removing the ink layer and metal layer thereon by applying supersonic vibration to the substrate in the kerosene.Type: GrantFiled: September 27, 1984Date of Patent: February 17, 1987Assignee: Marui Industry Co., Ltd.Inventors: Shigeru Nakagawa, Kiyotaka Uchikawa
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Patent number: 4634039Abstract: A solder resist paste having the feature that it is relatively easily removed is disclosed. The paste is comprised of a liquid polyglycol (e.g. Pluronic 25R2 by BASF) and either Kaoline or talc powder. In operation, the paste is selectively applied to holes in the PCB which it is desired to keep open during a soldering process. The paste is then washed out of the holes, additional components mounted via those holes, and soldered into place.Type: GrantFiled: October 19, 1984Date of Patent: January 6, 1987Assignee: Northern Telecom LimitedInventor: Hari N. Banerjee
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Patent number: 4628409Abstract: A printed circuit board which facilitates the removal and replacement of components. The circuit board (1) has unplated holes (8) extending therethrough for receiving connection pins (3) of components (2) mounted on one face of the circuit board (1). The pins (3) protrude from the opposite face of the circuit board (1) and are soldered to conductive pads (9) on this face which are connected by surface conductors (10) to plated through-holes (4) linking conductive tracks (6,7) at different layers of the circuit board (1).Type: GrantFiled: February 14, 1986Date of Patent: December 9, 1986Assignee: International Computers LimitedInventors: Gordon L. Thompson, Brian Gudgeon, Kenneth J. Wombwell
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Patent number: 4619504Abstract: The invention is directed to an ophthalmic lens having a marking and a method of producing the same. The lens is suitable for spectacles and the like. The method includes applying a removable adhering substance to a region of the surface of the lens body so that the peripheral outline of the substance corresponds to the marking to be formed. Then, an anti-reflection coating is applied to the lens body and, at a time thereafter, the adhering substance and the portion of the coating covering the substance is removed thereby causing a recess to be formed in the coating having a peripheral outline defining the marking. The marking formed in this way is practically invisible to a person wearing spectacles equipped with the lens of the invention. On the other hand, the marking is clearly visible when viewed in reflected light.Type: GrantFiled: September 2, 1983Date of Patent: October 28, 1986Assignee: Carl-Zeiss-StiftungInventors: Erwin J. Daniels, Bernd Kratzer, Hermann Schurle
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Patent number: 4617193Abstract: An integrated circuit having a plurality of devices on a substrate is disclosed, wherein a plurality of metallization layers, separated by a plurality of insulating layers, are used to interconnect the devices. Each metallization layer is recessed in an upper portion of a corresponding dielectric layer. A metallization layer is connected to a lower one, or, in the case of the first metallization layer, to the devices, by solid contacts extending through via windows in the lower portion of the corresponding dielectric layer. A method of manufacturing such an integrated circuit is also disclosed, whereby each layer is formed in two steps. First, the lower portion of the insulating layer is deposited, the contact pattern opened and the vias windows filled with metal to provide contacts even with the top surface of the lower portion of the insulating layer.Type: GrantFiled: June 16, 1983Date of Patent: October 14, 1986Assignee: Digital Equipment CorporationInventor: Andrew L. Wu
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Patent number: 4610910Abstract: A printed circuit board comprising an insulating board deposited with a catalyst having reactivity against electroless plating deposition, a resist for electroless plating provided on the insulating board excepting the part where a circuit is to be formed and a circuit formed by electroless plating, wherein the resist for electroless plating contains a coupling agent having a function of preventing the catalyst from ionizing. A process for producing the printed circuit board in which the insulating board surface excepting the part where a circuit is to be formed is covered with a resist for electroless plating containing a coupling agent having a function of preventing the catalyst from ionizing. Use of said resist for electroless plating can prevent drop of insulation resistance of the insulating board after moisture absorption.Type: GrantFiled: September 28, 1984Date of Patent: September 9, 1986Assignee: Hitachi, Ltd.Inventors: Mineo Kawamoto, Kanji Murakami, Haruo Akahoshi, Yoichi Matsuda, Motoyo Wajima, Makoto Matsunaga, Shoji Kawakubo, Toyofusa Yoshimura, Haruo Suzuki, Tomio Yoshida
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Patent number: 4606931Abstract: A lift-off process for depositing a metallurgy layer on a substrate wherein the improvement is the use of a sacrificial masking layer that is substantially unaffected by exposure to high intensity radiation. The process includes the steps of (1) preparing a resin mixture of a polyaryl sulfone polymer, and a compound of the following: ##STR1## wherein R.sub.1 is a methyl ethyl or an .alpha. branched alkyl group from 3 to 10 atoms, R.sub.2 is a hydrogen, methyl, ethyl or a branched alkyl group of from 3 to 10 carbon atoms, and X has a value of 1 to 6, and Z is an aliphatic hydrocarbon of the formula C.sub.5 H.sub.8 the compound being present in the amount of from 0.5 to 3.Type: GrantFiled: June 27, 1983Date of Patent: August 19, 1986Assignee: International Business Machines CorporationInventors: Beverly L. Olsen, Augustus C. Ouano
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Patent number: 4600629Abstract: The present printing process provides a unique color tone print of muted contrast in two, sequentially operated, flexographic print stations. A suitable paper substrate base for the process is uncoated white paper of stationery or envelope grade. As the paper supply web is drawn through the first print station, the desired image or design is printed on the paper with a colorless solution of a polyol, such as glycerine, in a glycol ether solvent. The second print station simply lays a uniform color coating of compatible pigment or solvent dye based ink over the entire web surface. Shade or tone differences resulting from differences in ink absorption with respect to the glycerine solution image areas provide a distinctive printed product.Type: GrantFiled: September 16, 1985Date of Patent: July 15, 1986Assignee: Westvaco CorporationInventors: David H. Knapp, Robert E. Lafler
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Patent number: 4595608Abstract: A metal is selectively chemically vapor deposited on a substrate through openings in a moisture adsorbing mask layer by maintaining moisture in the mask layer. Thick metal layers are formed by precharging the mask with moisture. Also a cleaned tube is prepared for selective deposition by operating the process with a bare substrate until the tube is coated. The selective deposition is then performed.Type: GrantFiled: November 9, 1984Date of Patent: June 17, 1986Assignee: Harris CorporationInventors: Edward M. King, Kurt E. Gsteiger, Joseph S. Raby
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Patent number: 4594265Abstract: Single crystal dielectrically isolated islands are formed providing a substantially non-reflective or indentured silicon surface before the application of the dielectric isolation layer and the polycrystalline support. Thin film resistor material is formed and delineated on an insulative layer over the single crystal island juxtaposed to the substantially non-reflective bottom dielectric isolation. The thin film resistive layer is trimmed using a laser.Type: GrantFiled: May 15, 1984Date of Patent: June 10, 1986Assignee: Harris CorporationInventors: Nicolaas W. Van Vonno, Richard Hull, Paul S. Reinecke
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Patent number: 4592808Abstract: A method for plating conductive plastics. The area to be plated is abrasively blasted as necessary to produce suitable mechanical bonding sites. The area is cleaned with a hot alkaline cleaning solution that will not appreciably attack the plastic. The area is sensitized to provide a base for firm adhesion of the metal onto the plastic. Sensitizing a graphite-reinforced epoxy composite preferably includes flowing a dilute solution of hydrochloric acid over the area, flowing a palladium chloride catalyst, rinsing the area, flowing a stannous accelerator, and rinsing the area again. Striking is then carried out by flowing an electroless plating solution over the area to provide a preliminary deposit of metal. The electroless solution may be either copper or nickel. The flowing of each solution is done at a very low velocity to ensure effective and even action on the entire area. Following striking, a plating buildup is provided as required.Type: GrantFiled: July 24, 1984Date of Patent: June 3, 1986Assignee: The Boeing CompanyInventor: Roark M. Doubt
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Patent number: 4578281Abstract: A partial painting method suitable for partially painting a workpiece or article of a complex surface shape. A surface of the workpiece is coated with strippable paint. The coated strippable paint is dried into a strippable film on the workpiece surface. A laser beam is applied to the strippable film along a prescribed cutting line so as to cut the strippable film. A portion of the strippable film corresponding to a first area of the workpiece surface to be painted is peeled off, while the remaining portion of the strippable film is left adhering on a second area of the workpiece surface to remain unpainted, and thereby masking of the workpiece is completed. The first area is then painted with a paint to form a final paint coating.Type: GrantFiled: April 25, 1985Date of Patent: March 25, 1986Assignee: Honda Giken Kogyo Kabushiki KaishaInventors: Hiroo Ebisawa, Iwao Maruyama, Masao Fukuda, Shigeo Miyamoto
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Patent number: 4576834Abstract: A streamlined process for forming a fully recessed, self-planarized dielectric isolation structure involves selectively depositing organosilicon material such as orthosilicate esters or siloxane resins in substrate trenches without build-up on adjacent substrate steps, which steps are coated with a non-wetting polymer material such as fluorocarbon compounds, then converting the organosilicon material to silicon oxide by heating at about 200.degree. C.-900.degree. C.Type: GrantFiled: May 20, 1985Date of Patent: March 18, 1986Assignee: NCR CorporationInventor: Zbigniew P. Sobczak
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Patent number: 4571286Abstract: A process for selectively depositing a tungsten or tantalum refractory metal on a graphite piece, particularly for X-ray tube anodes, wherein the graphite piece is masked on selected surfaces, an intermediate layer of a coating material is deposited on unmasked surfaces to promote adhesion of the refractory metal followed by removal of the masking and deposition of the refractory metal on all surfaces, and finally removing from the formerly masked surfaces refractory metal poorly adhered thereto.Type: GrantFiled: October 11, 1983Date of Patent: February 18, 1986Assignee: Thomson-CSFInventor: Jean-Marie Penato
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Patent number: 4560642Abstract: A method of manufacturing a semiconductor device which comprises the step of applying a silicon carbide film having a prescribed perforated pattern as a masking film selectively to etch a silicon dioxide film or diffuse an impurity into a substrate.Type: GrantFiled: July 19, 1984Date of Patent: December 24, 1985Assignee: Toyko Shibaura Electric Co., Ltd.Inventors: Toshio Yonezawa, Takashi Ajima, Shunichi Hiraki, Yutaka Koshino, Yoshitami Oka
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Patent number: 4560584Abstract: In accordance with one embodiment of the invention, solder masking material is pressurized by means of a fluid pump to approximately 250 psi and a high speed valve is used to turn the flow on and off rapidly in order that small "shots" of fluid are propelled from a tip, through the air, to selected portions of a circuit board. The selected areas of the circuit board to be masked are situated oppositely from the tip, as by a XY positioning system for the tip and/or the circuit board. The drops of masking material, which form upon impinging of the shots onto the circuit board, may be varied in volume and diameter. Where needed, a continuous bead of masking material may be formed on the circuit board by spacing the dots sufficiently close together.Type: GrantFiled: December 23, 1983Date of Patent: December 24, 1985Assignee: Universal Instruments CorporationInventor: Albert S. Henninger
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Patent number: 4560421Abstract: Disclosed is a method of manufacturing a semiconductor device comprising a step of forming a field region formation insulating film on a semiconductor substrate, a step of forming a mask pattern covering a portion of the insulating film corresponding to an intended element region, a step of ion implanting a field inversion prevention impurity into an element isolation region of the substrate with the mask pattern used as a shield, a step of forming an etching-proof layer on a portion of the insulating film corresponding to a field region, a step of removing the mask pattern to let an etching-proof layer portion be left on the intended element isolation region, and a step of selectively etching the insulating film with the remaining etching-proof layer used as a mask to form the element isolation region. Also disclosed is a semiconductor device manufactured by making use of this method.Type: GrantFiled: October 2, 1981Date of Patent: December 24, 1985Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Satoshi Maeda, Hiroshi Iwai
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Patent number: 4552785Abstract: The invention relates to a process for the production of patterned lustre coatings on surfaces of bodies of glazed ceramic, in particular, tiles, glass or enamel using a cover corresponding to the pattern to be produced. On the surface of the body acting as substrate, a negative of the pattern is produced by a paste applied by screen printing, the body provided with the pattern negative is heated in a furnace to a temperature above approximately 400.degree. C., the body is subsequently dipped into the solution of a metallic compound which reacts with the surface of the body not covered by screen printing to form a thin layer of the metal and oxides of the metal. In the metal/metal oxide layer of the body whose surface is cooled down by dipping, lustre colors are produced by heat input. Finally, after formation of the lustre colors, the screen printing paste constituting the pattern negative is removed from the body.Type: GrantFiled: November 1, 1983Date of Patent: November 12, 1985Inventor: Erwin W. Wartenberg
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Patent number: 4548967Abstract: A paint spray booth masking composition comprising:______________________________________ Ingredients % by weight ______________________________________ Water 30-50 Polyvinylpyrrolidone 2-30 Saccharide 16-60 Water-soluble surfactant 0.07-0.13 Preservative 0.05-0.Type: GrantFiled: June 15, 1984Date of Patent: October 22, 1985Assignee: Nalco Chemical CompanyInventors: William B. Brown, Cynthia E. Davis
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Patent number: 4539222Abstract: A process for forming a desired metal pattern on a substrate which comprises forming a mask of a thermally depolymerizable polymer on the substrate with a pattern of openings complementary to the desired metal pattern, blanket coating the substrate and the mask with a metal, heating to depolymerize the thermally depolymerizable polymer, and removing the thermally depolymerizable polymer and metal thereover in a mild solvent.Type: GrantFiled: November 30, 1983Date of Patent: September 3, 1985Assignee: International Business Machines CorporationInventors: Herbert R. Anderson, Jr., Constance J. Araps, Catherine A. Lotsko
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Patent number: 4537799Abstract: A selective metallization process particularly suited for making printed circuit boards comprises the step of treating a substrate having a negative mask thereon with a reactant, e.g., acetic acid, which modifies the surface of the mask without affecting the substrate so as to remove or prevent an active catalytic layer from remaining on the surface of the mask thereby preventing electroless plating on the mask.Type: GrantFiled: April 16, 1984Date of Patent: August 27, 1985Assignee: AT&T Technologies, Inc.Inventors: John K. Dorey, II, Steven L. Schmidt, Wesley P. Townsend
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Patent number: 4535022Abstract: Decorative tiles which may be bonded to the surfaces of columns and walls of a building are provided and a method for manufacturing the same is also disclosed. One surface of a tile blank made of a refractory material such as ceramic is coated with a metal layer by a metal spraying process so that a decorative tile looks gorgeous and even when a decorative tile is directly bonded to a concrete wall, it is not attacked or corroded.Type: GrantFiled: July 6, 1984Date of Patent: August 13, 1985Assignee: Aluteck Co., Ltd.Inventor: Chizuo Kato
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Patent number: 4533431Abstract: The invention relates to a process for producing conductors for integrated circuits using planar technology.According to this process, on a substrate is deposited an insulating material coating. A masking sheet is deposited on the insulating material coating and this sheet is cut to form windows corresponding to the conductors to be obtained. The insulating material sheet is etched facing the windows. A conductive material is deposited on the cut masking sheet. The masking sheet and the conductive material covering it are removed. This process consists of choosing a masking sheet having a first coating covering the insulating material coating and a second masking coating covering the first coating. The first coating is cut chemically facing the windows and after cutting the second masking coating, the edges of the first coating on the periphery of the windows are eroded by chemical cutting.Application to the production of planar integrated circuits.Type: GrantFiled: January 13, 1984Date of Patent: August 6, 1985Assignee: Commissariat a l'Energie AtomiqueInventor: Bruno Dargent
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Patent number: 4529618Abstract: The invention relates to a method of photolithographically treating a substrate, in which a surface of the substrate is treated at least at the area at which it consists of an inorganic material with an organosilicon compound.In order to improve the adhesion of a photolacquer layer to be applied, the organosilicon compound used is a 3-aminopropyl-trialkoxysilane in the form of an aqueous solution.Type: GrantFiled: October 3, 1983Date of Patent: July 16, 1985Assignee: U.S. Philips CorporationInventors: Johannes J. Ponjee, Franciscus J. B. Smolders, Christiaan J. A. Verwijlen
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Patent number: 4526810Abstract: A method which is particularly suitable to the manufacture of printed circuit boards of high resolution comprises the steps of forming a photoresist pattern having an ink coating over a substrate and subsequently depositing a species catalytic to electroless plating on the exposed substrate surface and then forming a flash electroless deposit thereon. The ink coating is then removed together with any overlying deposit leaving the photoresist intact so as to prevent spreading of the deposited flash metal pattern during the subsequent step of full buildup electroless and/or electrolytic plating.Type: GrantFiled: June 17, 1982Date of Patent: July 2, 1985Assignee: AT&T Technologies, Inc.Inventor: Raymond A. Nesbitt
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Patent number: 4526859Abstract: There is disclosed a method of selectively metallizing a ceramic substrate provided with a metallization pattern according by photoresist processing. A first layer of photoresist is blanket deposited over the substrate exposed through a coarse block out mask, and developed in order to protect those areas of the metallization pattern not to be covered with metal. A blanket metal layer is then formed over the entire substrate surface. A second layer of photoresist is deposited, exposed through a customized mask of the metallization pattern, and developed. The exposed metal is etched and the remaining first and second photoresist layers are removed, leaving a coating of metal only at desired locations.The method may be used for the heavy gold deposition over the Engineering change pads used as a standard in multilayer ceramic substrates.Type: GrantFiled: December 12, 1983Date of Patent: July 2, 1985Assignee: International Business Machines CorporationInventors: Richard G. Christensen, Robert L. Moore
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Patent number: 4525378Abstract: A method for manufacturing VLSI complementary MOS field effect transistor circuits (CMOS circuits). By use of a suitable gate material, preferably a gate material comprised of silicides of high melting point metals, a threshold voltage of n-channel and p-channel CMOS-FETs having gate oxide thicknesses d.sub.GOX in a range of 10 to 30 nm is simultaneously symmetrically set by means of a single channel ion implantation. Given employment of tantalum silicide, the gate oxide thickness d.sub.GOX is set to 20 nm and the channel implantation is executed with a boron dosage of 3.times.10.sup.11 cm.sup.-2 and an energy of 25 keV. In addition to achieving a high low-level break down voltage for short channel lengths, this enables the elimination of a photolithographic mask. This represents an improvement with respect to yield and costs. The method serves for the manufacture of analog and digital CMOS circuits in VLSI technology.Type: GrantFiled: June 5, 1984Date of Patent: June 25, 1985Assignee: Siemens AktiengesellschaftInventors: Ulrich Schwabe, Erwin P. Jacobs, Franz Neppl
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Patent number: 4521448Abstract: A method of manufacturing a semiconductor device comprises the steps of: forming a thin film on a semiconductor body on which a protruding pattern is formed with the film covering both the sides and the top of the protruding pattern; performing a selective anisotropic etching on the thin film for a distance corresponding to the thin film thickness, thereby removing a portion of the thin film including that portion covering the top of the protruding pattern and leaving a portion of the thin film covering the sides of the protruding pattern, thus forming a thin film pattern surrounding at least a portion of the protruding pattern; etching at least a top part of the protruding pattern while leaving the thin film pattern to extend upwardly from the surface of the semiconductor body; forming a conductive material film covering the semiconductor body including the thin film pattern; and dividing the conductive material film into portions by removing the thin film pattern.Type: GrantFiled: March 3, 1983Date of Patent: June 4, 1985Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventor: Yoshitaka Sasaki
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Patent number: 4521441Abstract: A process is disclosed for doping a semiconductor substrate which achieves a lower sheet resistivity than is otherwise obtainable. A spin-on dopant material is applied to the surface of the semiconductor substrate and subsequently heated to drive off solvents contained in the dopant material. The layer of spin-on dopant material is then plasma treated, preferably in an oxygen plasma, to enhance the diffusion properties of the spin-on material. The substrate and dopant material are then heated to an elevated temperature to accomplish the desired depth of diffusion.Type: GrantFiled: December 19, 1983Date of Patent: June 4, 1985Assignee: Motorola, Inc.Inventor: Dervin L. Flowers
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Patent number: 4508815Abstract: An improved method of planarizing a level of metallization employs a trench in a smooth-surfaced dielectric and a sequence of etching steps to cut the trench locally down to the substrate, while forming the main metallization pattern at the same time.Type: GrantFiled: November 3, 1983Date of Patent: April 2, 1985Assignee: Mostek CorporationInventors: Paul W. Ackmann, Frank R. Bryant
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Patent number: 4496648Abstract: During the preparation of a Josephson junction device, one of the steps for making a base electrode is to deposit a superconducting material on a substrate and to anneal the deposited material to make it a continuous homogeneous polycrystalline grain-like electrode material. Ordinarily, the base electrode and the counter electrode materials are deposited in a vacuum system at a vacuum pressure which is below one.times.10.sup.-6 torr to remove all contaminants such as oxygen, oxides of carbon and water vapor. It has been discovered that depositing conventional superconducting base electrode and counter electrode materials in the presence of an inert gas at much high vacuum pressures around 20.times.10-3 torr produce a superior lead-gold superconductive electrode which is substantially immune to thermal cycling.Type: GrantFiled: March 26, 1982Date of Patent: January 29, 1985Assignee: Sperry CorporationInventor: Peter L. Young
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Patent number: 4489101Abstract: A pattern forming method for semiconductor devices in which a film layer of a compound containing silicon and nitrogen is formed between a substrate and a resist layer with a desired pattern readily formed utilizing a lift-off technique. A first film layer of a compound such as Si.sub.3 N.sub.4 is formed on a semiconductor substrate with a resist film layer formed in a desired pattern upon the first film layer. The first film layer is etched using the resist film layer as a mask. A second film layer is then formed on the substrate after which the first film layer is removed with an etchant which does not attack the second film layer.Type: GrantFiled: September 24, 1982Date of Patent: December 18, 1984Assignee: ULSI Technology Research AssociationInventor: Hiroshi Shibata
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Patent number: 4488781Abstract: An electrochromic display matrix and method for making the same are disclosed wherein relatively small spacing distances between the individual electrochromic elements can be obtained. The method comprises exposing and developing photoresist through a pattern which defines strips and relatively narrow spacing distances. Solvent-permeable ion-conductive material and then solvent-permeable conductive material are applied over the photoresist. Photoresist solvent-remover is then applied, which releases the underlying photoresist and lifts off the ion-conductive material and conductive material to establish isolated regions of ion-conductive material and conductive material. Insulating paint is then applied in order to maintain isolation between the strips. The completed device, when addressed by a multiplexing method, is substantially free of any cross talk effects. High resolution display matrices are obtainable.Type: GrantFiled: January 25, 1982Date of Patent: December 18, 1984Assignee: American Cyanamid CompanyInventor: Robert D. Giglia
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Patent number: 4486466Abstract: A resinous protective coating useful in the manufacture of printed circuit boards with circuit patterns having a resolution of at least 0.25 mm lines and spaces thereon. The protective coating comprises resins dissolved in solvents, wherein the coating upon being subjected to heat goes from a high viscosity solution to a gel and then to a solid or from a soft "gel-like" state into a solid. The protective coating is resistant to copper electroplating baths, adheres to insulating substrates, adhesive coated base materials as well as metallic substrates and is capable of withstanding the thermal shock of dip soldering.Type: GrantFiled: July 29, 1982Date of Patent: December 4, 1984Assignee: Kollmorgen Technologies CorporationInventors: Edward J. Leech, Frank D. Russo
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Patent number: 4481233Abstract: A process for producing a solid-state color pickup array, which comprises forming a resist mask on a wafer having a solid image pickup array; vapor-depositing a colorant on the wafer having the resist mask and on the resist mask; and removing the resist mask by dissolution, thereby eliminating selectively the colorant film vapor-deposited on the resist mask.Type: GrantFiled: February 16, 1983Date of Patent: November 6, 1984Assignee: Canon Kabushiki KaishaInventors: Hajime Sakata, Kojiro Yokono, Seiichi Takahashi
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Patent number: 4478878Abstract: Method for preparation of metal-free strips in the metal vapor deposition of an insulating tape intended for use in electric capacitors, in which the insulating tape is covered, in the region of the metal-free strips to be prepared, by an endless cover tape which rests against the insulating tape and travels along with the same velocity as the former and is coated with oil on the side facing the metal evaporator before entering the vapor deposition zone. The invention is characterized by the features that first, the insulating tape and the cover tape are brought into contact with each other; that then by vapor deposition of oil, a film is prepared which also covers the lateral surfaces of the cover tape as well as slightly adjacent areas, and whereupon the metal vapor deposition takes place.Type: GrantFiled: August 23, 1982Date of Patent: October 23, 1984Assignee: Siemens AktiengesellschaftInventor: Anselm Neuwald
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Patent number: 4477486Abstract: The disclosed method is one for applying an opaque screening area (46) to a surface of a glass sheet (40). The method is initiated by applying to the surface of the glass sheet a masking material (42) which defines the edges of the opaque screening area. The masking material is nonreactive with the glass surface and is heat decomposable into products which can be removed from the glass surface without damage thereto. The masking material extends away from the defined edges of the opaque screening area to provide a wide area of masking material. A ceramic-containing material is applied on areas of the surface of the glass sheet to which the opaque screening areas are to be applied. The ceramic-containing material also coats at least a part of the masking material.Type: GrantFiled: February 16, 1984Date of Patent: October 16, 1984Assignee: Ford Motor CompanyInventor: Premakaran T. Boaz
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Patent number: 4465716Abstract: A method for selectively depositing a composite material over high-thermal-conductivity areas (such as silicon) and not over low-thermal-conductivity areas (such as oxide), which does not require any additional patterning step. A composite material, such as TiW is deposited overall by sputtering. A short pulse of light is then applied, and the composite material over the oxide separates and flakes off, while the composite material over the high-thermal-conductivity area remains in place.Type: GrantFiled: June 2, 1982Date of Patent: August 14, 1984Assignee: Texas Instruments IncorporatedInventors: Samuel C. Baber, Vernon R. Porter
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Patent number: 4464430Abstract: Very good masking of pack diffusion aluminizing on any metal to keep portions from being diffusion coated, is effected by localized coating the lowest layer of which is depletion-reducing masking powder that can have same composition as substrates, mixed with non-contaminating film-former such as acrylic resin. The upper coating layer can be of non-contaminating particles like nickel of Cr.sub.2 O.sub.3 that upon aluminizing or chromizing become coherently held together to form a secure sheath. Such sheath can also be used for holding localized diffusion-coating layer in place. Film-former can be dissolved in volatile solvent, preferably methyl chloroform, in which masking powder or sheath-forming powder is suspended. Chromizing can be performed before aluminizing for greater effects. Aluminized cases are stripped from superalloys by alternating dips in fluoride-containing and fluoride-free aqueous nitric acid.Type: GrantFiled: March 10, 1981Date of Patent: August 7, 1984Assignee: Alloy Surfaces Company, Inc.Inventor: Alfonso L. Baldi
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Patent number: 4459323Abstract: A complementary grid made from a volatile material is formed on the surface of the cathode, which is then covered with the material of the grid (parts 5 and 6). After the volatilization of the complementary grid there leaves an integrated grid (part 6) on this surface.Type: GrantFiled: April 15, 1981Date of Patent: July 10, 1984Assignee: Thomson-CSFInventors: Didier Grauleau, Arvind Shroff
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Patent number: 4457952Abstract: When an alkaline earth metal carbonate powder is mixed with an adhesive and is formed into an adhesive layer in a conventional covering method, a problem of the transfer of catalyst for electroless plating during a masking step or later electroless plating step is solved. Further, blisters under plated film caused by a fire retardant contained in an insulating substrate is also overcome by the use of alkaline earth metal powder.Type: GrantFiled: April 15, 1983Date of Patent: July 3, 1984Assignee: Hitachi, Ltd.Inventors: Mineo Kawamoto, Kanji Murakami, Yutaka Itoh, Youichi Matsuda, Motoyo Wajima, Hirosada Morishita, Shoji Kawakubo, Toyofusa Yoshimura
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Patent number: 4451971Abstract: An improved lift-off process for forming metallized interconnections between various regions on a semi-conductor device relies on the use of a particular polyimide in forming a protective mask over the device. The polyimide is a copolymer of an aromatic cycloaliphatic diamine and a dianhydride which allows the resulting structure to withstand particularly high temperatures in the fabrication process. In particular, the polyamide when subjected to high temperature metallization under vacuum remains sufficiently soluble to be substantially completely removed from the device by immersion in common organic solvents. This allows high temperature metallization as interconnects for integrated circuits.Type: GrantFiled: August 2, 1982Date of Patent: June 5, 1984Assignee: Fairchild Camera and Instrument CorporationInventor: Alvin Milgram