Nonuniform Or Patterned Coating Patents (Class 427/97.3)
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Publication number: 20130248232Abstract: A conductive pattern film substrate and manufacturing method for combining two anisotropic materials, namely a patterned body and a film layer, without assistance from an intermediate layer. The method includes producing a thermal spraying source for performing a heating operation on a film material to prepare the film material for thermal spraying or semi-thermal spraying and thereby decompose the film material into film particles; and spraying the film particles to a pattern layer disposed on the body and having the pattern by the thermal spraying source to form the film layer having the film particle on the pattern layer, thereby enabling the body to embody electrical characteristics of the pattern.Type: ApplicationFiled: March 22, 2012Publication date: September 26, 2013Inventors: JACKY CHANG, Eric Lin, Song-Jhe Liu
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Publication number: 20130249660Abstract: A parallel stacked symmetrical and differential inductor and manufacturing method of the same is disclosed. The parallel stacked symmetrical and differential inductor is disposed on a substrate and comprises at least one first conductive layer (202, 204) disposed on an insulating layer and at least one subsequent conductive layer (206, 208) disposed on a plurality of insulating layers stacked under the at least one first conductive layer (202, 204). The at least one first conductive layer (202, 204) and each of the at least one subsequent conductive layer (206, 208) are electrically connected by a first plurality of conductive plugs (214) in a winding region (104). Each of the at least one subsequent conductive layer (206, 208) are electrically connected by a second plurality of conductive plugs (212) in a bridge region (102).Type: ApplicationFiled: March 12, 2013Publication date: September 26, 2013Applicant: SILTERRA MALAYSIA SDN. BHD.Inventors: Chun Lee LER, Mohd Hafis MOHD ALI, Yusman YUSOF, Subhash Chander RUSTAGI
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Publication number: 20130250576Abstract: According to one embodiment, a wiring board device includes a ceramic board including a first surface and a second surface. A first electrode layer is formed on the first surface of the ceramic board, and a second electrode layer is formed on the second surface of the ceramic board. The first electrode layer and the second electrode layer are not electrically connected to each other. A first copper plated layer as a wiring pattern is formed on the first electrode layer, and a second copper plated layer is formed on the second electrode layer. The first copper plated layer and the second copper plated layer are not electrically connected to each other. A heat spreader is thermally connected to the second copper plated layer.Type: ApplicationFiled: June 26, 2012Publication date: September 26, 2013Applicant: Toshiba Lighting & Technology CorporationInventors: Nobuhiko BETSUDA, Hirotaka TANAKA, Takuya HONMA, Miho WATANABE, Kiyoshi NISHIMURA
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Publication number: 20130240366Abstract: Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations.Type: ApplicationFiled: March 15, 2013Publication date: September 19, 2013Applicant: AVX CORPORATIONInventors: Andrew P. Ritter, Robert Heistand, II, John L. Galvagni, Sriram Dattaguru
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Publication number: 20130229729Abstract: A main object of the present invention is to provide a suspension substrate such that design freedom of a wiring layer is improved while restraining the upsizing in accordance with an increase in a wiring layer. The present invention solves the problem by providing a suspension substrate comprising a metal supporting substrate, a first insulating layer, a first wiring layer, a second insulating layer, and a second wiring layer laminated in this order, characterized in that the first wiring layer has a functional element wiring layer connected to a functional element, and the second wiring layer has a signal transmission wiring layer comprising a pair of wiring layers and connected to a recording and reproducing element.Type: ApplicationFiled: October 28, 2011Publication date: September 5, 2013Applicant: DAI NIPPON PRINTING CO., LTD.Inventor: Tsuyoshi Yamazaki
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Publication number: 20130215200Abstract: According to the present disclosure, a manufacturing method of a fine wiring pattern is disclosed. The manufacturing method includes preparing a support member, forming a first layer on the support member by thick-film printing, and forming a second layer including Ag on the first layer by the thick-film printing. The method also includes forming a predetermined fine wiring pattern by performing an etching process upon the first layer and the second layer.Type: ApplicationFiled: January 23, 2013Publication date: August 22, 2013Applicant: ROHM CO., LTD.Inventor: ROHM CO., LTD.
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Patent number: 8507031Abstract: The microcomponent, for example a microbattery, comprising a stack with at least two superposed layers on a substrate, is made using a single steel mask able to expand under the effect of temperature. The mask comprises at least one off-centered opening. The mask being at a first temperature, a first layer is deposited through the opening of the mask. The mask being at a second temperature, higher than the first temperature, a second layer is deposited through the opening of the mask. Finally, the mask being at a third temperature, higher than the second temperature, a third layer is deposited through the opening of the mask.Type: GrantFiled: June 9, 2010Date of Patent: August 13, 2013Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Steve Martin, Nicolas Dunoyer, Sami Oukassi, Raphael Salot
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Publication number: 20130199826Abstract: An electronic component assembly comprises a printed component structure comprising at least one of a semiconducting ink, an insulating ink and a conducting ink deposited onto a substrate. The component structure defining at least one contact area, with a connecting lead disposed against or adjacent to the contact area. At least one layer of electrically insulating material encloses the component structure. At least one of the substrate and the layer of electrically insulating material comprises packaging material. The component structure can be printed on a substrate such as paper or another soft material, which is secured to a layer of insulating packaging material such as polyethylene. Instead, the substrate can be the insulating packaging material itself. Variations using hard and soft substrates are possible, and various examples of electronic component assembly are disclosed.Type: ApplicationFiled: September 13, 2011Publication date: August 8, 2013Applicant: PST SENSORS (PROPRIETARY) LIMITEDInventors: David Thomas Britton, Margit Harting
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Patent number: 8499446Abstract: A method of manufacturing a multilayer printed wiring board includes forming a first interlaminar resin insulating layer, a first conductor circuit on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer, opening portions in the second interlaminar resin insulating layer to expose a face of the first conductor circuit, an electroless plating film on the second interlaminar resin insulating layer and the exposed face, and a plating resist on the electroless plating film. The method further includes substituting the electroless plating film with a thin film conductor layer, having a lower ion tendency than the electroless plating film, and a metal of the exposed face, forming an electroplating film including the metal on a portion of the electroless plating film and the thin film conductor layer, stripping the plating resist, and removing the electroless plating film exposed by the stripping.Type: GrantFiled: July 20, 2011Date of Patent: August 6, 2013Assignee: Ibiden Co., Ltd.Inventors: Toru Nakai, Sho Akai
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Publication number: 20130188361Abstract: There is provided a wiring substrate. The wiring substrate includes: a heat sink; an insulating layer on the heat sink; first and second wiring patterns on the insulating layer to be separated from each other at a certain interval; a first reflective layer including a first opening on the insulating layer so as to cover the first and second wiring patterns, wherein a portion of the first and second wiring patterns is exposed from the first opening, and wherein the portion of the first and second wiring patterns is defined as a mounting region on which a light emitting element is to be mounted; and a second reflective layer on the insulating layer, wherein the second reflective layer is interposed between the first and second wiring patterns. A thickness of the second reflective layer is smaller than that of the first reflective layer.Type: ApplicationFiled: January 24, 2013Publication date: July 25, 2013Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: SHINKO ELECTRIC INDUSTRIES CO., LTD.
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Publication number: 20130186680Abstract: A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.Type: ApplicationFiled: January 23, 2013Publication date: July 25, 2013Applicant: Samsung Electronics Co., Ltd.Inventor: Samsung Electronics Co., Ltd.
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Publication number: 20130187813Abstract: A method for manufacturing a sensing electrical device includes the following steps; (a) forming a conductive trace on an insulating substrate; (b) placing the insulating substrate with the conductive trace in a mold cavity of a mold; (c) injecting an insulating material into the mold cavity to encapsulate the conductive trace to form an injection product; and (d) removing the injection product from the mold cavity.Type: ApplicationFiled: January 23, 2013Publication date: July 25, 2013Applicant: TAIWAN GREEN POINT ENTERPRISES CO., LTD.Inventor: TAIWAN GREEN POINT ENTERPRISES CO., LTD.
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Publication number: 20130181944Abstract: A touch panel according to the embodiment includes a substrate; a first electrode formed on the substrate in a first direction and including a plurality of sensor parts and connection parts connecting the sensor parts with each other; and a second electrode formed in a second direction crossing the first direction while being insulated from the first electrode and including a plurality of sensor parts and connection parts connecting the sensor parts with each other. The sensor parts and the connection parts include transparent conductive materials, and the connection parts have resistance lower than resistance of the sensor parts in at least one of the first and second electrodes.Type: ApplicationFiled: July 13, 2011Publication date: July 18, 2013Applicant: LG INNOTEK CO., LTD.Inventors: Dong Youl Lee, Yong Jin Lee, Young Sun You, Kyoung Hoon Chai, Young Jin Noh
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Publication number: 20130176070Abstract: In one embodiment, a touch sensor includes a substrate. A plurality of conductive elements are formed on the substrate. A plurality of sacrificial conductive members overlay portions of the plurality of conductive elements. The sacrificial conductive members function as sacrificial anodes for the conductive elements.Type: ApplicationFiled: January 11, 2012Publication date: July 11, 2013Inventor: David Brent Guard
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Publication number: 20130169557Abstract: The wiring substrate includes a substrate; a plurality of conductive patterns on a surface of the substrate, the plurality of conductive patterns including a plurality of sensing electrodes, a plurality of driving electrodes and a plurality of wirings connected to at least one of the plurality of sensing electrodes and the plurality of driving electrodes; and a photo solder resist layer on the surface of the substrate, the photo solder resist layer including a body and a plurality of protrusions extending from a side of the body, wherein an end portion of each protrusion is formed on each of the respective wirings, and a width of the end portion is smaller than a width of a starting portion of each protrusion that is in contact with the side of the body.Type: ApplicationFiled: August 28, 2012Publication date: July 4, 2013Inventor: Jae Hong KIM
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Publication number: 20130168215Abstract: The present disclosure discloses a touch panel and a method of manufacturing the same. The touch panel comprises a transparent substrate, a non-transparent insulation layer disposed on the transparent substrate, wherein the non-transparent insulation layer has a first opening and a second opening, transparent conductive patterns disposed in the first opening and the second opening, and non-transparent conductive patterns disposed on the non-transparent insulation layer beyond the first opening and the second opening, wherein the non-transparent conductive patterns electrically connect the transparent conductive pattern in the first opening and the transparent conductive pattern in the second opening.Type: ApplicationFiled: June 28, 2012Publication date: July 4, 2013Inventors: YANJUN XIE, Yau-Chen Jiang, Bin Lai, Limei Huang
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Patent number: 8475867Abstract: A method for forming electrical traces on a substrate includes the steps of: providing a substrate; printing an ink pattern using an ink on the substrate, the ink including a aqueous medium containing silver ions and a heat sensitive reducing agent; heating the ink pattern to reduce silver ions into silver particles thereby forming an semi-finished traces; and forming a metal overcoat on the semi-finished traces by electroless plating thereby obtaining patterned electrical traces.Type: GrantFiled: September 30, 2009Date of Patent: July 2, 2013Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., Zhen Ding Technology Co., Ltd.Inventors: Yao-Wen Bai, Cheng-Hsien Lin
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Publication number: 20130161083Abstract: A printed circuit board includes a substrate having a first surface, a first conductive circuit deposited on the first surface and a dielectric cover deposited on the first surface and covering at least a portion of the first conductive circuit. The dielectric cover has an edge and the first surface is exposed beyond the edge. A second conductive circuit is deposited on the dielectric cover and the substrate. The second conductive circuit spans the edge such that at least part of the second conductive circuit is deposited on the dielectric cover and at least part of the second conductive circuit is deposited on the first surface.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: Tyco Electronics CorporationInventors: CHARLES RANDALL MALSTROM, Joseph D. Locondro, Michael Fredrick Laub, David Bruce Sarraf
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Publication number: 20130153266Abstract: Disclosed herein is a printed circuit board, including: a base substrate; at least one circuit pattern formed on the base substrate; at least one dummy pattern formed on the base substrate; and an insulating layer formed on the circuit pattern and the dummy pattern, wherein a distance between adjacent patterns to each other among the circuit patterns and the dummy patterns meets the following Equation 1. D ? T ? ? 2 T ? ? 1 × 200 1.2 [ Equation ? ? 1 ] (Where D represents a distance between adjacent patterns to each other among the circuit patterns and the dummy patterns, T1 represents a thickness of the circuit pattern or the dummy pattern, and T2 represents a maximum thickness of the insulating layer formed on the circuit pattern or the dummy pattern.Type: ApplicationFiled: December 18, 2012Publication date: June 20, 2013Applicant: Samsung Electro-Mechanics Co., Ltd.Inventor: Samsung Electro-Mechanics Co., Ltd.
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Patent number: 8466374Abstract: A base of circuit board, a circuit board, and a method of fabricating thereof are provided. The circuit board includes a substrate, a plurality of elastic bumps and a patterned circuit layer. The elastic bumps arranged in at least an array are located on the substrate. The patterned circuit layer is located on a portion of the elastic bumps and a portion of the substrate. The base of the circuit board and the method of fabricating thereof are also included in the present invention.Type: GrantFiled: June 3, 2009Date of Patent: June 18, 2013Assignees: Taiwan TFT LCD Association, Chunghwa Picture Tubes, Ltd., Au Optronics Corporation, Hannstar Display Corporation, Chi Mei Optoelectronics Corporation, Industrial Technology Research InstituteInventors: Ngai Tsang, Kuo-Shu Kao
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Publication number: 20130146334Abstract: Embodiments of the present invention relate to circuit layouts that are compatible with printing electronic inks, printed circuits formed by printing an electronic ink or a combination of printing and conventional blanket deposition and photolithography, and methods of forming circuits by printing electronic inks onto structures having print-compatible shapes. The layouts include features having (i) a print-compatible shape and (ii) an orientation that is either orthogonal or parallel to the orientation of every other feature in the layout.Type: ApplicationFiled: February 1, 2013Publication date: June 13, 2013Inventors: Zhigang WANG, Vivek SUBRAMANIAN, Lee CLEVELAND
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Publication number: 20130146345Abstract: A printed wiring board includes a first insulation layer, a first conductive pattern formed on a first surface of the first insulation, a second conductive pattern formed on a second surface of the first insulation on the opposite side with respect to the first surface of the first insulation, a first buildup structure formed on the first surface of the first insulation and the first pattern, the first buildup structure including insulation layers and conductive patterns, and a second buildup structure formed on the second surface of the first insulation and the second pattern, the second buildup structure including insulation layers and conductive patterns. The second pattern and the patterns in the second buildup structure form an inductor, and the first and second patterns are positioned such that the distance between the first and second patterns in the thickness direction of the first insulation is set 100 ?m or greater.Type: ApplicationFiled: October 31, 2012Publication date: June 13, 2013Inventors: Kazuki KAJIHARA, Haruhiko MORITA
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Publication number: 20130133926Abstract: Disclosed herein is a method of manufacturing a build-up printed circuit board (PCB), the method including: providing a first resin substrate; forming a roughness by coating an epoxy emulsion solution on a surface of the first resin substrate; and providing a core layer by forming a core circuit layer on the first resin substrate on which the roughness is formed. According to the present invention, roughness of a substrate can be formed in an environment-friendly and economical way by introducing a process of coating epoxy emulsion on a resin substrate. Further, a highly reliable fine circuit can be implemented by enhancing an adhesive bond between a build-up board material and a metal circuit layer.Type: ApplicationFiled: February 29, 2012Publication date: May 30, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Tae Hoon Kim, Young Kwan Seo, Jun Young Kim, Sung Nam Cho
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Publication number: 20130126223Abstract: A cover insulating layer is formed on a base insulating layer. One of write wiring traces includes first to third lines, and the other write wiring trace includes fourth to sixth lines. The one and other write wiring traces constitute a signal line pair, the second and fifth lines are arranged on an upper surface of the cover insulating layer, and the third and sixth lines are arranged on an upper surface of the base insulating layer. At least parts of the second and fifth lines are respectively opposed to the sixth and third lines with the cover insulating layer sandwiched therebetween. The second and third lines are electrically connected to the first line, and the fifth and sixth lines are electrically connected to the fourth line. The fourth line is electrically connected to at least one of the fifth and sixth lines through a jumper wiring on a lower surface of the base insulating layer.Type: ApplicationFiled: November 7, 2012Publication date: May 23, 2013Applicant: NITTO DENKO CORPORATIONInventor: Daisuke YAMAUCHI
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Publication number: 20130126222Abstract: A method for producing an electrical multi-layer component is described, wherein a first ceramic layer (2) comprising a first and a second ceramic material (3, 4) is applied to a ceramic substrate (1). The first ceramic material (3) is applied to a first surface partition (5) of the substrate (1) by a first inkjet printing step and the second ceramic material (4) is applied to a second surface partition (6) of the substrate (1) by a second inkjet printing step, the second surface partition (6) surrounding and enclosing the first surface partition (5). The second ceramic material (4) is different from the first ceramic material (3). Furthermore, an electrical multi-layer component is described.Type: ApplicationFiled: April 18, 2011Publication date: May 23, 2013Applicant: EPCOS AGInventor: Andrea Testino
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Publication number: 20130122430Abstract: A method of manufacturing a printed circuit board for an optical waveguide includes forming an insulation layer having a through hole on a substrate; forming a lower clad layer on a bottom of the through hole; forming a core part on the lower clad layer; and forming an upper clad layer covering the core part on the lower clad layer and the core part.Type: ApplicationFiled: January 7, 2013Publication date: May 16, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: SAMSUNG ELECTRO-MECHANICS CO., LTD.
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Publication number: 20130120288Abstract: The present invention relates to a touch-sensing panel including an electrode-integrated window, and a manufacturing method thereof. The disclosed touch-sensing panel includes a transparent window and a wiring unit. A sensing electrode is formed in a certain pattern on one surface of the transparent window, and the transparent window allows touching on the opposite surface to the plane where the sensing electrode is formed. The wiring unit is connected to the sensing electrode, and the sensing electrode is integrated with the transparent window. According to the invention, it is used the transparent window in which the sensing electrode is integrated with the one surface so that the manufacturing processes may be simplified and the yield may be increased.Type: ApplicationFiled: September 20, 2012Publication date: May 16, 2013Applicant: Melfas, Inc.Inventor: Melfas, Inc.
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Publication number: 20130112464Abstract: Methods, systems, and apparatuses for circuit boards are provided herein. An electrically insulating material is formed over one or more traces on a circuit board. One or more further electrically conductive features are present on the circuit board. A layer of an electrically conductive material is formed over the one or more traces that is electrically isolated from the one or more traces by the electrically insulating material, and is in electrical contact with the one or more further electrically conductive features. The electrically conductive material confines magnetic and electric fields produced when the one or more traces conduct an alternating current. By confining the magnetic and electric field distributions in this manner, problems of interference and/or crosstalk with adjacent signal traces are reduced or eliminated.Type: ApplicationFiled: November 29, 2012Publication date: May 9, 2013Applicant: BROADCOM CORPORATIONInventor: Broadcom Corporation
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Publication number: 20130113752Abstract: The embodiments described herein are related to capacitive input device, including a substrate, a plurality of first sensor electrodes deposited on the substrate and arranged in a first direction, an insulating layer, a plurality of connecting elements deposited on the insulating layer, a plurality of second sensor electrodes. The plurality of second sensor electrodes includes a plurality of sensor electrode elements deposited on the substrate ohmically isolated from the plurality of first sensor electrodes. Each of the plurality of sensor electrode elements are connected to at least one other sensor electrode element arranged in a second direction by one of the plurality of connecting elements. The capacitive input device may further include a plurality of routing elements deposited on the insulating layer, wherein each of the plurality of routing elements coupled to one of the plurality of second sensor electrodes and is substantially disposed in the first direction.Type: ApplicationFiled: June 19, 2012Publication date: May 9, 2013Applicant: SYNAPTICS INCORPORATEDInventors: Yi-Yun Chang, Yeh-Cheng Tan
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Publication number: 20130105213Abstract: A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias.Type: ApplicationFiled: September 6, 2012Publication date: May 2, 2013Applicant: UNIMICRON TECHNOLOGY CORPORATIONInventors: Dyi-Chung Hu, Tzyy-Jang Tseng
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Publication number: 20130106528Abstract: Disclosed herein are an asymmetrical multilayer substrate, an RF module, and a method for manufacturing the asymmetrical multilayer substrate. The asymmetrical multilayer substrate includes a core layer, a first pattern layer formed on one side of the core layer and including a first signal line pattern, a second pattern layer formed on the other side and including a second metal plate and a second routing line pattern, a first insulating layer thinner than the core layer formed on the second pattern layer and including a first via, and a third pattern layer formed on the first insulating layer and including a third signal line pattern, wherein an impedance transformation circuit including an impedance load and a parasitic capacitance load on the transmission line is formed for impedance matching in signal transmission between the signal line patterns formed in the upper and lower side directions of the core layer.Type: ApplicationFiled: October 30, 2012Publication date: May 2, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: Samsung Electro-Mechanics Co., Ltd.
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Patent number: 8431184Abstract: Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings.Type: GrantFiled: May 7, 2011Date of Patent: April 30, 2013Assignee: Micron Technology, Inc.Inventor: Nishant Sinha
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Publication number: 20130098749Abstract: The present disclosure relates to a touch sensing device comprising a plurality of sensing electrode units and an insulating pattern layer. The insulating pattern layer covers the plurality of sensing electrode units and has a plurality of openings that are not corresponding to plurality of sensing electrode units. The present disclosure also discloses a method for manufacturing the touch sensing device.Type: ApplicationFiled: July 19, 2012Publication date: April 25, 2013Inventors: Yanjun Xie, Yau-Chen Jang, Limei Huang
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Publication number: 20130100626Abstract: Embodiments of the present invention provide a wiring substrate having a structure where a plurality of projection electrodes are arranged within an electrode formation region on a substrate main surface. At least one among a plurality of the projection electrodes is a variant projection electrode which has a recess portion on an upper surface, an outer diameter at the upper end that is larger than an outer diameter at the lower end, and a reverse trapezoidal cross-section shape. Embodiments of the present invention also provide methods for manufacturing wiring substrates having one or more of said variant projection electrode.Type: ApplicationFiled: October 24, 2012Publication date: April 25, 2013Applicant: NGK SPARK PLUG CO., LTD.Inventor: NGK SPARK PLUG CO., LTD.
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Publication number: 20130099273Abstract: A wiring substrate includes a substrate, a first insulating layer formed on the substrate, wiring patterns formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer. The second insulating layer covers the wiring patterns and includes a first opening that partially exposes adjacent wiring patterns as a pad. A projection is formed in an outer portion of the substrate located outward from where the first opening is arranged. The projection rises in a thickness direction of the substrate.Type: ApplicationFiled: October 19, 2012Publication date: April 25, 2013Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: SHINKO ELECTRIC INDUSTRIES CO., LTD.
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Patent number: 8414963Abstract: The structure comprises at least a device, for example a microelectronic chip, and at least a getter arranged in a cavity under a controlled atmosphere delineated by a substrate and a sealing cover. The getter comprises at least one preferably metallic getter layer, and an adjustment sub-layer made from pure metal, situated between the getter layer and the substrate, on which it is formed. The adjustment sub-layer is designed to modulate the activation temperature of the getter layer. The getter layer comprises two elementary getter layers.Type: GrantFiled: March 23, 2010Date of Patent: April 9, 2013Assignee: Commissariat a l'Energie AtomiqueInventor: Xavier Baillin
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Patent number: 8414962Abstract: The invention relates to thin film single layers, electronic components such as multilayer capacitors which utilize thin film layers, and to their methods of manufacture. Chemical solution deposition and microcontact printing of dielectric and electrode layers are disclosed. High permittivity BaTiO3 multilayer thin film capacitors are prepared on Ni foil substrates by microcontact printing and by chemical solution deposition. Multilayer capacitors with BaTiO3 dielectric layers and LaNiO3 internal electrodes are prepared, enabling dielectric layer thicknesses of 1 ?m or less. Microcontact printing of precursor solutions of the dielectric and electrode layers is used.Type: GrantFiled: October 28, 2005Date of Patent: April 9, 2013Assignee: The Penn State Research FoundationInventors: Susan Trolier McKinstry, Clive A. Randall, Hajime Nagata, Pascal I. Pinceloup, James J. Beeson, Daniel J. Skamser, Michael S. Randall, Azizuddin Tajuddin
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Publication number: 20130069087Abstract: A multiple-layer wiring substrate having a first conductive layer; an interlayer insulating layer; and a second conductive layer is disclosed, wherein the interlayer insulating layer includes a material whose surface energy is changed by receiving energy, and has a first region which does not include a contact hole and a second region which is formed such that its surface energy is higher than that of the first region, wherein a region within the contact hole of the first conductive layer has surface energy which is higher than surface energy of the second region of the interlayer insulating layer, and wherein the second conductive layer is formed by laminating, wherein the second conductive layer is in contact with the second region of the interlayer insulating layer along the second region, and is connected to the first conductive layer via the contact hole.Type: ApplicationFiled: September 13, 2012Publication date: March 21, 2013Applicant: RICOH COMPANY, LTD.Inventors: Atsushi ONODERA, Koei Suzuki, Hiroshi Miura, Takanori Tano
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Publication number: 20130064991Abstract: A manufacturing method of a flux gate sensor may include: a first step of forming a first wiring layer on a substrate; a second step of forming a first insulating layer to cover the first wiring layer; a third step of forming a magnetic layer on the first insulating layer, the magnetic layer constituting a core of a flux gate; a fourth step of forming a second insulating layer on the first insulating layer to cover the magnetic layer; and a fifth step of forming a second wiring layer on the second insulating layer. The first wiring layer and the second wiring layer may be electrically connected to each other so that each constitutes a magnetic coil and a pickup coil, and at least a process temperature in each of the third, fourth, and fifth steps may be lower than a glass transition temperature of the first resin.Type: ApplicationFiled: November 7, 2012Publication date: March 14, 2013Inventor: Kenichi OHMORI
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Publication number: 20130057497Abstract: Provided is a method for fabricating a transparent circuit board for a touch screen. The transparent circuit board includes a transparent substrate that has a conductive bridge layer deposited thereon. A liquid insulating layer is deposited on the transparent substrate and the bridge layer, and a sensor layer having first and second conductive patterns is deposited on the transparent substrate and the insulating layer.Type: ApplicationFiled: September 5, 2012Publication date: March 7, 2013Inventors: Yong-Gu Cho, Hae-Jung Yang
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Publication number: 20130056247Abstract: A wiring method is provided in which an insulating layer is formed on a surface of a semiconductor device 1 of which a plurality of connecting terminals are exposed, a resin film is formed on a surface of the insulating layer, a groove of a depth equal to or exceeding a thickness of the resin film is formed from a surface side of the resin film so that the groove passes in a vicinity of connecting terminals that are to be connected, and furthermore communicating holes which reach the connecting terminals to be connected from this portion that groove passes in the vicinity thereof are formed.Type: ApplicationFiled: May 11, 2011Publication date: March 7, 2013Applicant: PANASONIC CORPORATIONInventors: Shingo Yoshioka, Hiroaki Fujiwara, Hiromitsu Takashita, Tsuyoshi Takeda, Yuko Konno
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Publication number: 20130056245Abstract: Disclosed herein is a printed circuit board, including a base substrate; and a circuit pattern formed on the base substrate and including a first metal layer having an inclined surface on both upper sides thereof and a second metal layer formed on the inclined part.Type: ApplicationFiled: September 6, 2012Publication date: March 7, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: Min Sung Kim
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Publication number: 20130048358Abstract: A wiring structure includes: an insulating film formed over a substrate; a plurality of wirings formed on the insulating film; and an inducing layer, which is formed on the insulating film in a region between the plurality of wirings, a constituent atoms of the wirings are diffused in the inducing layer.Type: ApplicationFiled: June 22, 2012Publication date: February 28, 2013Applicant: FUJITSU LIMITEDInventors: Tsuyoshi KANKI, Shoichi Suda, Yoshihiro Nakata
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DECORATIVE FILM ON TRANSPARENT SUBSTRATE, A TOUCH SENSOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Publication number: 20130038547Abstract: A decorative film on a transparent substrate is provided. The decorative film includes a color transparent layer, a reflective layer and a protective layer. The color transparent layer is on a surface of a transparent substrate. The reflective layer is disposed on the color transparent layer and the protective layer is disposed on the reflective layer. The disclosure also describes a touch sensor device and a method of manufacturing a touch sensor device.Type: ApplicationFiled: August 1, 2012Publication date: February 14, 2013Applicants: CHIMEI INNOLUX CORPORATION, INNOCOM TECHNOLOGY(SHENZHEN) CO., LTD.Inventors: Su Peng LIN, Tsu-Hsien KU, Jyh-Douh TU, Szu-Wei LAI -
Publication number: 20130025915Abstract: A resistive device includes a resistive layer, a flexible substrate arranged on the resistive layer, and an electrode layer. The electrode layer includes two electrode sections arranged below the resistive layer and separate to each other. Moreover, a method for manufacturing the resistive device with flexible substrate is also disclosed.Type: ApplicationFiled: July 12, 2012Publication date: January 31, 2013Inventors: Yen-Ting LIN, Dar-Win LO, Sung-Chan YEN, Hsing-Kai CHENG
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Publication number: 20130014976Abstract: [Purpose] To provide a wired circuit board in which it is possible to inhibit a conductive adhesive from leaking to the outside, while inhibiting terminals from being increased in size, and also improve connection reliability. [Solving Means] A suspension board with circuit 3 includes power-source wires 25B, and piezoelectric-side terminals 40 formed continuously to the power-source wires 25B and electrically connected thereunder to piezoelectric elements 5. Each of the piezoelectric-side terminals 40 includes an outer contact portion 51, and an inner contact portion 53 provided around the outer contact portion 51 to protrude below the outer contact portion 51.Type: ApplicationFiled: May 31, 2012Publication date: January 17, 2013Applicant: NITTO DENKO CORPORATIONInventors: Saori ISHIGAKI, Jun ISHII, Yoshito FUJIMURA, Yuu SUGIMOTO
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Publication number: 20130015937Abstract: A laminate in which plural insulator layers are stacked includes an external electrode that is exposed to the exterior of the laminate and includes a plurality of conductive layers stacked in a staking direction and passing through some of the plural insulator layers in the stacking direction. At least one side of the external electrode facing in the stacking direction is overlaid with rest of the plural insulator layers. At least one side surface of the external electrode facing in the stacking direction is uneven with another portion of the side surface.Type: ApplicationFiled: July 10, 2012Publication date: January 17, 2013Applicant: MURATA MANUFACTURING CO., LTD.Inventor: Atsushi SEKO
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Publication number: 20130015234Abstract: In accordance with an embodiment, a method comprises providing a substrate having a conductive material thereon, forming a ground plane, a first trace rail, and a first perpendicular trace from the conductive material, and forming an insulator material over the ground plane, the first trace rail, and the first perpendicular trace. The ground plane is between the first trace rail and an area of the substrate over which will be a die. The first trace rail extends along a first outer edge of the ground plane, and the first perpendicular trace is coupled to the first trace rail and extends perpendicularly from the first trace rail.Type: ApplicationFiled: September 14, 2012Publication date: January 17, 2013Applicants: GLOBAL UNICHIP CORP., TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Sung Lin, Li-Hua Lin, Yu-Yu Lin
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Patent number: 8349393Abstract: Compositions and methods for silver plating onto metal surfaces such as PWBs in electronics manufacture to produce a silver plating which is greater than 80 atomic % silver, tarnish resistant, and has good solderability.Type: GrantFiled: July 29, 2004Date of Patent: January 8, 2013Assignee: Enthone Inc.Inventors: Yung-Herng Yau, Thomas B. Richardson, Joseph A. Abys, Karl F. Wengenroth, Anthony Fiore, Chen Xu, Chonglun Fan, John Fudala
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Publication number: 20120313886Abstract: A touch panel includes a substrate, an adhesive layer, a carbon nanotube film, an electrode and a conductive trace. The substrate has a surface defining a touch-view area and a trace area. The adhesive layer is located only on the surface of the touch-view area. The carbon nanotube film is located on the adhesive layer and only on the touch-view area. The electrode is located only on the trace area and electrically connected with the carbon nanotube film. The conductive trace is located only on the trace area and electrically connected with the electrode. A method for making the touch panel is also provided.Type: ApplicationFiled: December 29, 2011Publication date: December 13, 2012Applicant: Shih Hua Technology Ltd.Inventors: CHUN-YI HU, YI-LIN CHANG, CHIH-HAN CHAO, PO-SHENG SHIH