With Posttreatment Of Coating Or Coating Material Patents (Class 427/97.4)
-
Patent number: 8617656Abstract: A liquid processing apparatus processes an object to be processed W including a body part Wi and a plurality of projecting-shape parts Wm disposed on the body part Wi, with an inorganic film and a different film being laminated to each other. The liquid processing apparatus comprises: a support part 50 configured to support the body part Wi; a hydrophobic-liquid supply mechanism 30 configured to supply a hydrophobic liquid to the object to be processed W; and a rinse-liquid supply part 22 configured to supply a rinse liquid to the object to be processed W to which the hydrophobic liquid has been supplied. The hydrophobic-liquid supply mechanism 30 includes: a first hydrophobic-liquid supply part 32 configured to supply a first hydrophobic liquid for making hydrophobic the inorganic film; and a second hydrophobic-liquid supply part 37 configured to supply a second hydrophobic liquid for making hydrophobic the different film.Type: GrantFiled: May 21, 2010Date of Patent: December 31, 2013Assignee: Tokyo Electron LimitedInventors: Mitsunori Nakamori, Akira Fujita, Takayuki Toshima
-
Publication number: 20130335822Abstract: The disclosure is related to a method for manufacturing touch-sensitive element on a polarizer, and a polarization device made by the method. In one of the embodiments of the invention, a polarizing substrate is firstly prepared. The method then coats first transparent conductive material onto the substrate, and uses a patterning process to form multiple sensing areas and wiring areas. There are continuous paths and adjacent non-continuous paths are existed in between the sensing areas. A bridged insulating layer is formed as processing the step for spray-coating or inject-printing insulating material upon the areas of the non-continuous pads. A bridged conductive layer is formed upon the insulation layer as spray-coating or inject-printing a second transparent conductive material there-on. The bridged conductive layer is to electrically connect the non-continuous pads. The method is therefore forming the polarization device with the touch-screen elements.Type: ApplicationFiled: June 18, 2012Publication date: December 19, 2013Applicant: J TOUCH CORPORATIONInventors: YU-CHOU YEH, JUI-MING NI, PING-HSU LAI, HSIAO-SHUN JAN, CHENG-HSIUNG WU
-
Publication number: 20130335483Abstract: An inkjet print head includes a jet assembly which includes a nozzle plate, the nozzle plate including an ink transferring path on a bottom surface of the nozzle plate, and a jet jetting a transferred ink out of the head. A printed circuit substrate is connected to the jet assembly and includes an integrated circuit and a connection electrode. A barrier coating layer covers a surface of the printed circuit substrate and an inner surface and an outer surface of the jet assembly except a bottom surface of the nozzle plate and a surface of the connection electrode of the jet assembly and the printed circuit substrate being connected with each other. The barrier coating layer has a layered structure which includes a flexible layer, a diffusion barrier layer, and a hydrophobic layer.Type: ApplicationFiled: October 17, 2012Publication date: December 19, 2013Applicant: Samsung Display Co., Ltd.Inventors: Woo-Yong SUNG, A-Ram Lee, Tae-Woon Cha, Tae-Gyun Kim, Hyoung Sub Lee, Seung-Yeon Chae, Sang Gun Choi
-
Patent number: 8609201Abstract: An infrared energy oxidizing and/or curing process includes an infrared oxidation zone having an infrared energy source operable to emit infrared energy that oxidizes a conductive thin film deposited or established on a glass substrate to establish a light transmissive or transparent conductive thin film for manufacturing of a touch panel. Optionally, the infrared energy curing process provides an in-line infrared energy curing process that oxidizes the conductive thin film on the glass substrate as the glass substrate is moved past the infrared energy source. Optionally, the infrared energy curing process bonds a thick film silver frit electrode pattern to the conductively coated glass substrate. Optionally, the infrared energy curing process reduces the transparent conductive thin film.Type: GrantFiled: July 2, 2008Date of Patent: December 17, 2013Assignee: TPK Touch Solutions Inc.Inventor: Catherine A. Getz
-
Publication number: 20130327564Abstract: A circuit board and a manufacturing method thereof are provided. According to the method, a dielectric layer is formed on a dielectric substrate, and the dielectric layer contains active particles. A surface treatment is performed on a surface of the dielectric first conductive layer is formed on the activated surface of the dielectric layer. A conductive via is formed in the dielectric substrate and the dielectric layer. A patterned mask layer is formed on the first conductive layer, in which the patterned mask layer exposes the conductive via and a part of the first conductive layer. A second conductive layer is formed on the first conductive layer and conductive via exposed by the patterned mask layer. The patterned mask layer and the first conductive layer below the patterned mask layer are removed.Type: ApplicationFiled: August 9, 2012Publication date: December 12, 2013Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: Cheng-Po Yu, Shang-Feng Huang, Chang-Ming Lee, Young-Sheng Bai
-
Patent number: 8597424Abstract: A composition for forming an aluminum film, comprising a complex represented by the following formula (1) and a complex represented by the following formula (2), the molar ratio of the complex represented by the following formula (1) and the complex represented by the following formula (2) being 40:60 to 85:15: AlH3.NR1R2R3??(1) AlH3.(NR1R2R3)2??(2) (in the above formulas (1) and (2), R1, R2 and R3 are each independently a hydrogen atom, alkyl group, cycloalkyl group, alkenyl group, alkynyl group, aryl group or aralkyl group.).Type: GrantFiled: December 24, 2008Date of Patent: December 3, 2013Assignee: JSR CorporationInventors: Tatsuya Sakai, Yasuo Matsuki, Tetsuo Tominaga
-
Publication number: 20130316329Abstract: Among others, the present invention provides piezo-electric micro-devices for detecting at the microscopic level an electric, magnetic, electromagnetic, thermal, optical, acoustical, biological, chemical, physical, bio-chemical, bio-physical, physical-chemical, bio-physical-chemical, bio-mechanical, bio-electro-mechanical, electro-mechanical, or mechanical property of the biologic subject.Type: ApplicationFiled: October 5, 2011Publication date: November 28, 2013Inventors: Chris Chang Yu, Xuedong Du
-
Publication number: 20130302534Abstract: According to one embodiment, a method is disclosed for manufacturing a display device. A film material layer is formed on a support substrate. A first heating process for the film material layer at a first temperature to form a film layer and a second heating process for a second region surrounding a first region at a second temperature higher than the first temperature are performed. The first region is provided in a central part of the film layer. A display layer is formed in the first region and a peripheral circuit section is formed at least in a part of the second region. A third heating process is performed for at least a part of the film layer at a third temperature higher than the second temperature. In addition, the film layer is peeled off from the support substrate.Type: ApplicationFiled: July 17, 2013Publication date: November 14, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Tatsunori SAKANO, Kentaro Miura, Nobuyoshi Saito, Shintaro Nakano, Tomomasa Ueda, Hajime Yamaguchi
-
Patent number: 8574444Abstract: A method of fabricating a multilayer printed circuit board includes forming a first circuit-forming pattern and a via-forming pattern on a first carrier, and forming a first insulation layer; repeatedly forming inner circuit patterns and inner insulation layers over the first insulation layer by forming circuit-forming patterns and imprinting, and forming inner vias connecting the inner circuit patterns positioned on different insulation layers; forming a second circuit-forming pattern on a second carrier and inserting the first circuit-forming pattern and the second circuit-forming pattern respectively into the first insulation layer and a second insulation layer; removing the first carrier and the second carrier; forming circuit-forming grooves by removing the first circuit-forming pattern and the second circuit-forming pattern, and forming via-forming indentations connected with the circuit-forming grooves; and forming outer circuit patterns and outer vias by filling the circuit-forming grooves and the viaType: GrantFiled: August 14, 2012Date of Patent: November 5, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Ryoichi Watanabe
-
Publication number: 20130287935Abstract: A method of fabricating a circuit board is provided. An elastic bump material layer is formed on a substrate and then is patterned to form a plurality of first elastic bumps and a plurality of second elastic bumps, arranged in at least an array. A conductive layer is formed and then is patterned to form a patterned circuit layer to cover first plurality of elastic bumps and a portion of the substrate. An entirety of the plurality of second elastic bumps and another portion of the substrate are not covered by the patterned circuit layer. A protection layer is formed to cover a portion of the patterned circuit layer, a second number of the plurality of second elastic bumps entirely, a third number of the plurality of second elastic bumps partially and the another portion of the substrate, and expose the first number of the plurality of second elastic bumps.Type: ApplicationFiled: May 17, 2013Publication date: October 31, 2013Applicants: TAIWAN TFT LCD ASSOCIATION, CHUNGHWA PICTURE TUBES, LTD., INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, HANNSTAR DISPLAY CORPORATION, INNOLUX CORPORATION, AU OPTRONICS CORPORATIONInventors: Ngai Tsang, Kuo-Shu Kao
-
Publication number: 20130278521Abstract: A touch panel using a conductive mesh and a method of manufacturing the same are provided. The touch panel includes a substrate on which a conductive mesh is disposed, a plurality of driving channels for recognizing a horizontal axis coordinate, wherein the plurality of driving channels are formed by patterning a first conductive mesh disposed on the substrate, a plurality of sensing channels for recognizing a vertical axis coordinate, wherein the sensing channels are formed by patterning a second conductive mesh disposed on the substrate, and an insulating layer positioned between the first conductive mesh and the second conductive mesh.Type: ApplicationFiled: April 19, 2013Publication date: October 24, 2013Applicant: Samsung Electronics Co., Ltd.Inventor: Hakyeol KIM
-
Publication number: 20130277100Abstract: Disclosed herein are a touch panel and a method of manufacturing the same. The touch panel includes a transparent substrate, an insulating layer that is formed on the transparent substrate and has an intaglio portion formed thereon, an electrode layer that is embedded in the intaglio portion, and a light absorbing layer that is formed in an inner wall of the intaglio portion to be interposed between the inner wall of the intaglio portion and the electrode layer. In the touch panel, the electrode layer is formed to be embedded, and the light absorbing layer is further included, thereby durability and visibility of the touch panel.Type: ApplicationFiled: June 25, 2012Publication date: October 24, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Hyun Ra, Jin Uk Lee
-
Publication number: 20130256000Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer, a second insulation layer formed on the first insulation layer and the first conductive patterns and having an opening portion, a wiring structure accommodated in the opening portion of the second insulation layer and including an insulation layer and conductive patterns on the insulation layer, second conductive patterns formed on the second insulation layer; and a via conductor formed in the second insulation layer and connecting one of the first conductive patterns and one of the second conductive patterns.Type: ApplicationFiled: March 29, 2013Publication date: October 3, 2013Applicant: IBIDEN CO., LTD.Inventors: Makoto TERUI, Daiki Komatsu, Masatoshi Kunieda
-
Publication number: 20130248226Abstract: A printed electrical circuit and methods for additively printing electrical circuits. Patterned layers of conductive, insulating, semi-conductive materials, and other materials are print deposited on a flexible or rigid substrate to form electrical circuits. A buffering layer is selectively deposited to cover or encapsulate these materials to comprise a comfort layer that provides a soft and comfortable interface to the skin of a wearer. The comfort layer can be selectively deposited on the same press that the conductive, insulating, semi-conductive materials, and other materials are deposited. Further, the comfort layer is selectively deposited only where it is desired and exactly where it is desired.Type: ApplicationFiled: March 14, 2013Publication date: September 26, 2013Inventors: David G. Sime, Richard Koble
-
Publication number: 20130243369Abstract: The inventive concept provides optical switch devices and methods of manufacturing the same. The optical switch device may include a substrate including a first region and a second region, a first multi-mode optical waveguide disposed on the substrate of the first region, an electrode wire disposed on the substrate of the second region, a heater disposed on a top surface of the first multi-mode optical waveguide, and connection wires connecting the heater to the electrode wire. The first multi-mode optical waveguide may have incline sidewalls, and the connection wires may be disposed on the incline sidewalls of the first multi-mode optical waveguide.Type: ApplicationFiled: September 7, 2012Publication date: September 19, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang Ho PARK, Jang Uk Shin, Young-Tak Han, Yongsoon Baek
-
Publication number: 20130233608Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.Type: ApplicationFiled: March 8, 2012Publication date: September 12, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
-
Publication number: 20130213692Abstract: A method of fabricating a circuit board includes the following steps. A first and a second patterned conductive layer are plated on the first and the second surface of a core substrate, respectively. A first and a second extending pad are individually plated on a first and a second pad of the first and the second patterned conductive layer, respectively. A first and a second thermal-curing type dielectric layer are individually formed on the first and the second surface to cover the first and the second patterned conductive layer and the first and the second extending pad, respectively. A portion of the first and the second thermal-curing type dielectric layer respectively covering the top of the first and the second extending pad are removed. A protective film covers the second extending pad. The extending pad is removed by an etching process.Type: ApplicationFiled: July 10, 2012Publication date: August 22, 2013Applicant: VIA TECHNOLOGIES, INC.Inventor: Chen-Yueh Kung
-
Publication number: 20130188361Abstract: There is provided a wiring substrate. The wiring substrate includes: a heat sink; an insulating layer on the heat sink; first and second wiring patterns on the insulating layer to be separated from each other at a certain interval; a first reflective layer including a first opening on the insulating layer so as to cover the first and second wiring patterns, wherein a portion of the first and second wiring patterns is exposed from the first opening, and wherein the portion of the first and second wiring patterns is defined as a mounting region on which a light emitting element is to be mounted; and a second reflective layer on the insulating layer, wherein the second reflective layer is interposed between the first and second wiring patterns. A thickness of the second reflective layer is smaller than that of the first reflective layer.Type: ApplicationFiled: January 24, 2013Publication date: July 25, 2013Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: SHINKO ELECTRIC INDUSTRIES CO., LTD.
-
Publication number: 20130180766Abstract: The present invention relates to a printed circuit board which includes: a solder pad on which a solder ball is mounted; an insulator formed on the solder pad; and a protrusion formed under the insulator to support the solder ball when mounting the solder ball and can stably mount the solder ball.Type: ApplicationFiled: January 11, 2013Publication date: July 18, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: SAMSUNG ELECTRO-MECHANICS CO., LTD.
-
Patent number: 8475666Abstract: A toughening agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent selected from the group consisting of an amine, an onium compound and an alkali metal hydroxide.Type: GrantFiled: September 15, 2004Date of Patent: July 2, 2013Assignee: Honeywell International Inc.Inventors: Teresa A. Ramos, Robert R. Roth, Anil S. Bhanap, Paul G. Apen, Denis H. Endisch, Brian J. Daniels, Ananth Naman, Nancy Iwamoto, Roger Y. Leung
-
Patent number: 8475885Abstract: The method of forming an organic film, includes: an organic film formation step of forming an organic film on a surface of a base member using a silane coupling agent; and a post-processing step including a water vapor introduction step of holding the base member on which the organic film has been formed in an atmosphere containing at least water vapor, and a dehydration processing step of holding the base member in an atmosphere having a smaller presence of water vapor than the atmosphere in the water vapor introduction step.Type: GrantFiled: September 29, 2010Date of Patent: July 2, 2013Assignee: FUJIFILM CorporationInventor: Hiroki Uchiyama
-
Patent number: 8466582Abstract: A method and apparatus for applying an electric field to a photovoltaic element. In one embodiment, the apparatus comprises at least one photovoltaic (PV) cell having a P-N junction; and a voltage supply for (i) converting a first voltage to an e-field voltage, the first voltage generated local to the at least one PV cell, and (ii) coupling the e-field voltage to the at least one PV cell to create an electric field extending across the P-N junction.Type: GrantFiled: December 2, 2011Date of Patent: June 18, 2013Assignee: Enphase Energy, Inc.Inventor: Martin Fornage
-
Publication number: 20130146345Abstract: A printed wiring board includes a first insulation layer, a first conductive pattern formed on a first surface of the first insulation, a second conductive pattern formed on a second surface of the first insulation on the opposite side with respect to the first surface of the first insulation, a first buildup structure formed on the first surface of the first insulation and the first pattern, the first buildup structure including insulation layers and conductive patterns, and a second buildup structure formed on the second surface of the first insulation and the second pattern, the second buildup structure including insulation layers and conductive patterns. The second pattern and the patterns in the second buildup structure form an inductor, and the first and second patterns are positioned such that the distance between the first and second patterns in the thickness direction of the first insulation is set 100 ?m or greater.Type: ApplicationFiled: October 31, 2012Publication date: June 13, 2013Inventors: Kazuki KAJIHARA, Haruhiko MORITA
-
Publication number: 20130146340Abstract: A via-holed ceramic substrate can be manufactured in a simple method by providing a via-holed ceramic substrate comprising: a sintered ceramic substrate; an electroconductive via formed in the sintered ceramic substrate, the electroconductive via having an electroconductive metal closely filled in a through-hole, the electroconductive metal containing a metal (A) having a melting point of 600° C. to 1100° C., a metal (B) having a melting point higher than the melting point of the metal (A), and an active metal; and an active layer formed in the interface between the electroconductive via and the sintered ceramic substrate.Type: ApplicationFiled: December 2, 2011Publication date: June 13, 2013Applicant: TOKUYAMA CORPORATIONInventors: Naoto Takahashi, Yasuyuki Yamamoto
-
Publication number: 20130133926Abstract: Disclosed herein is a method of manufacturing a build-up printed circuit board (PCB), the method including: providing a first resin substrate; forming a roughness by coating an epoxy emulsion solution on a surface of the first resin substrate; and providing a core layer by forming a core circuit layer on the first resin substrate on which the roughness is formed. According to the present invention, roughness of a substrate can be formed in an environment-friendly and economical way by introducing a process of coating epoxy emulsion on a resin substrate. Further, a highly reliable fine circuit can be implemented by enhancing an adhesive bond between a build-up board material and a metal circuit layer.Type: ApplicationFiled: February 29, 2012Publication date: May 30, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Tae Hoon Kim, Young Kwan Seo, Jun Young Kim, Sung Nam Cho
-
Publication number: 20130122430Abstract: A method of manufacturing a printed circuit board for an optical waveguide includes forming an insulation layer having a through hole on a substrate; forming a lower clad layer on a bottom of the through hole; forming a core part on the lower clad layer; and forming an upper clad layer covering the core part on the lower clad layer and the core part.Type: ApplicationFiled: January 7, 2013Publication date: May 16, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: SAMSUNG ELECTRO-MECHANICS CO., LTD.
-
Publication number: 20130107485Abstract: The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (?m). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.Type: ApplicationFiled: March 31, 2011Publication date: May 2, 2013Applicant: Georgia Tech Research CorporationInventors: Pulugurtha Markondeya Raj, Nitesh Kumbhat, Venkatesh Sundaram, Rao R. Tummala
-
Patent number: 8431184Abstract: Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings.Type: GrantFiled: May 7, 2011Date of Patent: April 30, 2013Assignee: Micron Technology, Inc.Inventor: Nishant Sinha
-
Publication number: 20130098749Abstract: The present disclosure relates to a touch sensing device comprising a plurality of sensing electrode units and an insulating pattern layer. The insulating pattern layer covers the plurality of sensing electrode units and has a plurality of openings that are not corresponding to plurality of sensing electrode units. The present disclosure also discloses a method for manufacturing the touch sensing device.Type: ApplicationFiled: July 19, 2012Publication date: April 25, 2013Inventors: Yanjun Xie, Yau-Chen Jang, Limei Huang
-
Publication number: 20130075141Abstract: A wiring substrate includes a substrate main body having a first main face and a second main face opposite the first main face; a resistor formed on the first main face; a plurality of first-main-face-side wiring layers which are each formed on the resistor and which each include a grounding metal layer formed of a metal having a resistance lower than that of the resistor and a conductor layer formed on the grounding metal layer; a second-main-face-side wiring layer formed on the second main face; and a via which is formed in the substrate main body and which establishes electrical connectivity between the first-main-face-side wiring layers and the second-main-face-side wiring layer. The wiring substrate further includes a conductive covering layer which covers an upper surface and substantially covers the side surfaces of each of the first-main-face-side wiring layers.Type: ApplicationFiled: September 21, 2012Publication date: March 28, 2013Applicant: NGK SPARK PLUG CO., LTD.Inventor: NGK Spark Plug Co., Ltd.
-
Publication number: 20130057497Abstract: Provided is a method for fabricating a transparent circuit board for a touch screen. The transparent circuit board includes a transparent substrate that has a conductive bridge layer deposited thereon. A liquid insulating layer is deposited on the transparent substrate and the bridge layer, and a sensor layer having first and second conductive patterns is deposited on the transparent substrate and the insulating layer.Type: ApplicationFiled: September 5, 2012Publication date: March 7, 2013Inventors: Yong-Gu Cho, Hae-Jung Yang
-
Publication number: 20130048342Abstract: A circuit board includes a dielectric layer and sacrificial bumps on the dielectric layer in predetermined circuit common areas. A conductive seed layer is printed on the dielectric layer and the sacrificial bumps. A conductive circuit layer is plated onto the conductive seed layer. Sections of the conductive circuit layer and the conductive seed layer in the circuit common areas are removed. Optionally, the circuit board may include a metal substrate, with the dielectric layer applied on the metal substrate.Type: ApplicationFiled: August 23, 2011Publication date: February 28, 2013Applicant: TYCO ELECTRONICS CORPORATIONInventors: CHARLES RANDALL MALSTROM, MARJORIE KAY MYERS, JOHN PATTON GEIGER
-
Publication number: 20130050107Abstract: The present disclosure provides a manufacturing method of a touch panel that comprises of: simultaneously baking a sensing electrode layer and a protective layer that covers the sensing electrode layer. The present disclosure solves the issue of the sensing electrode layer being easily oxidized or corroded when baked alone. The present disclosure also simplifies the manufacturing process of the touch panel. The present disclosure also provides a touch panel on the basis of the manufacturing method.Type: ApplicationFiled: April 1, 2012Publication date: February 28, 2013Inventors: YANJUN XIE, YAU-CHEN JIANG, BIN LAI
-
Publication number: 20130037311Abstract: A base material or composite material such as graphite, may be combined with another material, such as aluminum oxide or polyimide, to produce a new insulating thermal management material. The base material may be impregnated with another metal to create a composite base material.Type: ApplicationFiled: August 9, 2012Publication date: February 14, 2013Applicant: APPLIED NANOTECH HOLDINGS, INC.Inventors: NAN JIANG, ZVI YANIV
-
Publication number: 20130033446Abstract: A manufacturing method of a touch panel is provided. The method includes the following steps. A conductive layer is formed on a substrate, and a dielectric layer is formed to cover the conductive layer. The conductive layer and the dielectric layer are then patterned to respectively form several sensing wires and several dielectric blocks by using a first mask, which is a half-tone mask. Next, a transparent conductive layer is first formed to cover the conductive layer and the dielectric layer, and is then patterned to form a touch sensing structure by using a second mask.Type: ApplicationFiled: August 3, 2012Publication date: February 7, 2013Applicants: CHIMEI INNOLUX CORPORATION, INNOCOM TECHNOLOGY(SHENZHEN)CO., LTD.Inventor: Chien-Hsin Liu
-
Publication number: 20130008706Abstract: A coreless packaging substrate is provided which includes: a circuit buildup structure having at least a dielectric layer, at least a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the lowermost one of the at least a dielectric layer, a plurality of metal bumps formed on the uppermost one of the at least a wiring layer, and a dielectric passivation layer formed on the surface of the uppermost one of the circuit buildup structure and the metal bumps, with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip is enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.Type: ApplicationFiled: March 12, 2012Publication date: January 10, 2013Applicant: UNIMICRON TECHNOLOGY CORPORATIONInventors: Tzyy-Jang Tseng, Chung-W. Ho
-
Publication number: 20120308718Abstract: A method of fabricating a multilayer printed circuit board includes forming a first circuit-forming pattern and a via-forming pattern on a first carrier, and forming a first insulation layer; repeatedly forming inner circuit patterns and inner insulation layers over the first insulation layer by forming circuit-forming patterns and imprinting, and forming inner vias connecting the inner circuit patterns positioned on different insulation layers; forming a second circuit-forming pattern on a second carrier and inserting the first circuit-forming pattern and the second circuit-forming pattern respectively into the first insulation layer and a second insulation layer; removing the first carrier and the second carrier; forming circuit-forming grooves by removing the first circuit-forming pattern and the second circuit-forming pattern, and forming via-forming indentations connected with the circuit-forming grooves; and forming outer circuit patterns and outer vias by filling the circuit-forming grooves and the viaType: ApplicationFiled: August 14, 2012Publication date: December 6, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: Ryoichi Watanabe
-
Patent number: 8318254Abstract: A copolymer deposited with particles of catalytic metal is disclosed in the present invention, which is formed from an ethylenically unsaturated monomer and a hydrophilic monomer, and the catalytic metal is Au, Ag, Pd, Pt or Ru. The copolymer is hydrophilic when the temperature is lower than a specific temperature, and will become hydrophobic when the temperature is greater than the specific temperature. The present invention also discloses a method for forming a metal layer on a substrate via electroless plating, which includes contacting the substrate with an ink composition, drying the ink composition on the substrate, and contacting the dried ink composition with an electroless plating solution, wherein the ink composition contains the copolymer of the present invention in an aqueous phase. The present invention further discloses a method for forming metal conductors in through holes of a substrate.Type: GrantFiled: October 30, 2008Date of Patent: November 27, 2012Assignee: National Defense UniversityInventors: Yuh Sung, Ming-Der Ger, Chang-Ping Chang, Chun-Chieh Tseng, Wen-Ding Chen
-
Publication number: 20120293852Abstract: A display substrate includes a base substrate, a micro shutter, a first driving electrode, a second driving electrode, and a plurality of anchors. The micro shutter includes a flat portion having at least one opening, a main concave portion adjacent to the opening and extending in from the flat portion to a first depth, and at least one sub-concave portion extending in from a bottom surface of the main concave portion to second depth. The first driving electrode is connected to a first side of the micro shutter. The second driving electrode is connected to a second side of the micro shutter. The second side is positioned opposite to the first side. The anchors fix the first and second driving electrodes on the base substrate.Type: ApplicationFiled: January 16, 2012Publication date: November 22, 2012Inventors: HYUN-MIN CHO, Sung-Sik YUN, Jae-Byung PARK, Don-Chan CHO, Dae-Hyun KIM, Seon-Tae YOON
-
Publication number: 20120274439Abstract: A metallization can be used for components working with acoustic waves. The metallization includes a base having a bottom layer comprising titanium, and an upper layer comprising copper. A top layer of the metallization disposed on the base comprises aluminum.Type: ApplicationFiled: November 18, 2010Publication date: November 1, 2012Applicant: EPCOS AGInventor: Guenter Feist
-
Publication number: 20120262385Abstract: A touch panel is made by forming a routing and pad pattern group on a substrate to include first and second routing lines, first pad electrodes connected to the first routing line, and second pad electrodes connected to the second routing line, by using a first mask; forming a sensor electrode pattern group on the substrate having the routing and pad pattern group formed thereon to include first sensor electrodes formed in a first direction, second sensor electrodes formed in a second direction, and connection portions that each connects adjacent first sensor electrodes, by using a second mask; forming a first insulating layer to include contact holes to expose portions of the second sensor electrodes, respectively, by using a third mask; and forming bridges that each connects adjacent second sensor electrodes through the contact holes and a second insulating layer on the bridges, by using a fourth mask.Type: ApplicationFiled: November 30, 2011Publication date: October 18, 2012Inventors: Seung-Hyun KIM, Hyung-Chul Kim, Tae-Yeon Yoo
-
Patent number: 8287943Abstract: The invention relates to the preparation of multilayer microcomponents which comprise one or more films, each consisting of a material M selected from metals, metal alloys, glasses, ceramics and glass-ceramics. The method consists in depositing on a substrate one or more films of an ink P, and one or more films of an ink M, each film being deposited in a predefined pattern selected according to the structure of the microcomponent, each film of ink P and each film of ink M being at least partially consolidated before deposition of the next film; effecting a total consolidation of the films of ink M partially consolidated after their deposition, to convert them to films of material M; totally or partially removing the material of each of the films of ink P. An ink P consists of a thermoset resin containing a mineral filler or a mixture comprising a mineral filler and an organic binder. An ink M consists of a mineral material precursor of the material M and an organic binder.Type: GrantFiled: January 5, 2007Date of Patent: October 16, 2012Assignee: Centre National de la Recherche ScientifiqueInventors: Claude Lucat, Francis Menil, Hélène Debeda-Hickel, Patrick Ginet
-
Publication number: 20120231154Abstract: A method for fabricating a ceramic device is provided. A green sheet is adhered on an adhesive film. A photoresist film is then formed on the green sheet. A photolithographic process is carried out to form circuit trenches in the photoresist film. The circuit trenches are filled with metal paste, thereby forming a circuit pattern. The photoresist film is then removed.Type: ApplicationFiled: January 19, 2012Publication date: September 13, 2012Inventors: Wen-Hsiung Liao, Wen-Yu Lin, Wei-Chien Chang
-
Publication number: 20120231155Abstract: A method of manufacturing a printed circuit board, including: applying a dry film on a carrier and then patterning the dry film to form holes for forming metal bumps; forming an upper circuit layer including metal bumps charged in the holes and connection pads on the dry film; forming an insulation layer on the dry film; forming a build-up layer including a lower circuit layer on the insulation layer; removing the carrier; and removing the dry film.Type: ApplicationFiled: May 22, 2012Publication date: September 13, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Yong AN, Jae Joon LEE
-
Publication number: 20120222892Abstract: To reduce the RF losses associated with high RF loss plating, such as, for example, Ni/Pd/Au plating, the solder mask is reconfigured to prevent the edges and sidewalls of the wire-bond areas from being plated in some embodiments. Leaving the edges and sidewalls of the wire-bond areas free from high RF loss plating, such as Ni/Pd/Au plating, provides a path for the RF current to flow around the high resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.Type: ApplicationFiled: March 3, 2011Publication date: September 6, 2012Applicant: Skyworks Solutions, Inc.Inventors: Weimin Sun, Peter J. Zampardi, Hongxiao Shao
-
Patent number: 8237057Abstract: A wiring board is provided that suppresses spreading of liquid droplets when liquid droplets are discharged using an ink-jet method. The wiring board has a plurality of layers and includes an ink-jet wiring pattern that is formed in a soluble porous membrane member of any single layer and that includes electrically conductive nanoparticles as a principal material, and a transferred wiring pattern that does not include electrically conductive nanoparticles as a principal material. One layer among the plurality of layers is an electrically insulative substrate. Another layer among the plurality of layers is a porous membrane treated member layer including a porous membrane member at one part of a region of the other layer. The ink-jet wiring pattern is formed in the porous membrane treated member layer. The transferred wiring pattern is formed in the substrate.Type: GrantFiled: June 17, 2009Date of Patent: August 7, 2012Assignee: Panasonic CorporationInventors: Takayuki Hirose, Norihito Tsukahara, Manabu Gokan
-
Publication number: 20120177814Abstract: A system and a method, the method includes determining or receiving a multiple iteration printing scheme indicative of multiple printing iterations of a coating material to be applied on an electrical circuit that comprises at least one three dimensional structure to be coated by the coating material; wherein the multiple iteration printing scheme is responsive to a shape and size of the at least one three dimensional structure; and performing multiple printing iterations of the coating material, according to the multiple iteration printing scheme; wherein at least one printing iteration is followed by at least partially curing the coating material printed during the at least one printing iteration.Type: ApplicationFiled: December 12, 2011Publication date: July 12, 2012Applicant: CAMTEK LTD.Inventors: Muhammad Iraqi, Noam Rozenstein, Eva Igner, Michael Litvin, Yaron Mazor
-
Publication number: 20120141665Abstract: Provided are methods of and apparatuses for forming a metal pattern. In the method, an initiator and a metal pattern are sequentially combined on a previously-formed bonding agent pattern improving adhesion and/or junction properties between the substrate and the metal. The bonding agent pattern may be formed using a reverse offset printing method. The metal pattern may be formed using an electroless electrochemical plating method. The metal pattern can be formed with improved uniformity in thickness and planar area.Type: ApplicationFiled: December 2, 2011Publication date: June 7, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Tae-Youb KIM, Kang-Jun Baeg, In-Kyu You, Minseok Kim, Jae Bon Koo
-
Patent number: 8176628Abstract: In accordance with one embodiment, a method of forming a protruding post substrate package includes applying a dielectric layer to a carrier. Via apertures are formed in the dielectric layer. Carrier cavities are formed in the carrier using the dielectric layer as a mask. The carrier cavities are lined with a first metal, the first metal being selectively etchable compared to the carrier. After encapsulation of an electronic component with an encapsulant, the carrier is removed such that protruding posts including the first metal protrude outward from a first surface of the dielectric layer.Type: GrantFiled: December 23, 2008Date of Patent: May 15, 2012Assignee: Amkor Technology, Inc.Inventors: Sukianto Rusli, Ronald Patrick Huemoeller, David Hiner
-
Publication number: 20120085730Abstract: A method for manufacturing a wiring board, includes: forming an insulating resin layer on a conductive layer; forming a metal chloride or a metal sulfate on the insulating resin layer; forming a protective layer on the metal chloride or the metal sulfate; forming an exposed portion in the insulating resin layer, the metal chloride or the metal sulfate, and the protective layer so as to at least partially expose the conductive layer; removing residues in the exposed portion; removing the protective layer; and forming a wiring on the insulating resin layer in which the protective layer has been removed.Type: ApplicationFiled: December 15, 2011Publication date: April 12, 2012Applicant: FUJITSU LIMITEDInventors: Shinya SASAKI, Motoaki TANI