Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region.

Abstract: A method for fabricating a touch sensor panel is disclosed. The method includes providing a substrate for the touch sensor panel, depositing a conductive material layer on a top surface of the substrate, depositing a metal layer on top of the conductive material layer, affixing a resist to a first area of the metal layer, the resist also adapted to serve as a passivation layer during passivation, removing metal from the metal layer outside of the first area; and performing passivation on the substrate while leaving the affixed resist intact.

Abstract: The present invention provides a metal ink composition, which includes 20 to 80 parts by weight of cupper nano-particle; 10 to 70 parts by weight of non-aqueous organic solvent; and 2 to 20 parts by weight of additive used for adjustment of the dry speed of coated metal ink when metal lines are formed.

Abstract: A method of manufacturing a substrate using a carrier, that includes preparing a carrier having a releasing layer, and insulating layers and metal layers sequentially disposed on both sides of the releasing layer; patterning the metal layers to form base circuit layers; forming buildup layers on the base circuit layers; executing a routing process to separate the insulating layers from the releasing layer; and forming solder resist layers on the buildup layers and forming openings in the solder resist layers and the insulating layers to expose pads.

Abstract: Disclosed is a printed circuit board, including a base substrate, a first bump including a first metal layer formed on the base substrate and a second metal layer formed on the first metal layer, and a second bump including a third metal layer formed on the base substrate, in which the first bump has a height greater than that of the second bump. Because the heights of the first bump and the second bump are different, even when the printed circuit board warps, an electrical connection between the printed circuit board and an external substrate does not become broken. A method of manufacturing the printed circuit board is also provided.

Abstract: A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad.

Abstract: A method of manufacturing a structure, including forming a composite film composed of a coating film and an organic or inorganic film on top of a substrate by forming the coating film on the surface of a template provided on top of the substrate; forming the organic or inorganic film on the surface of the coating film, and removing a portion of the organic or inorganic film and a portion of the coating film; forming a second coating film on the surface of the composite film; forming an organic coating film on the substrate that covers the second coating film; removing a portion of the second coating film; and forming a structure composed of a metal or metal oxide later on the substrate by removing all residues left on the substrate except for the coating film and the second coating film.

Abstract: A method for manufacturing a wiring structure of a wiring board is provided. In the method, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, a barrier layer completely covering the film is formed. Next, an intaglio pattern partially exposing the insulation layer is formed on an outer surface of the barrier layer. Next, an activated layer is formed on the outer surface and in the intaglio pattern. Then, the activated layer on the outer surface is removed, and the activated layer in the intaglio pattern is remained. After the activated layer on the outer surface is removed, a conductive material is formed in the intaglio pattern by using a chemical deposition method. After forming the conductive material, the barrier layer and the film are removed.

Abstract: A printed wiring board including an insulation layer made of a resin material and having first and second surfaces, the insulation layer having an opening portion opened on the second surface, a conductive circuit having first and second surfaces, the conductive circuit being embedded in the insulation layer such that the first surface of the conductive circuit is formed flush with the first surface of the insulation layer and that the second surface of the conductive circuit is exposed through the opening portion of the insulation layer, a first surface-treatment film formed on the conductive circuit and facing the first surface of the conductive circuit, and a second surface-treatment film formed on the conductive circuit and facing the second surface of the conductive circuit and in the opening portion of the insulation layer.

Abstract: Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings.

Abstract: An anisotropic conductive film includes a first thin film layer including concave portions, conductive balls arranged in the concave portions, insulating balls disposed on and between the conductive balls and each having a diameter smaller than the conductive balls, and a second thin film layer disposed covering the insulating balls. A display apparatus includes a pad part and a driving chip, which are electrically connected by the anisotropic conductive film.

Abstract: Disclosed is a trench substrate, which includes a first insulating layer having trenches formed therein, a second insulating layer disposed on a lower surface of the first insulating layer and having laser processability inferior to that of the first insulating layer, and a negative pattern formed in the trenches, and in which the second insulating layer having laser processability inferior to that of the first insulating layer functions as a stopper, so that the trenches having the same shape are formed in the first insulating layer, thus enabling the formation of a fine and uniform circuit pattern. A method of fabricating the trench substrate is also provided.

Abstract: Disclosed herein are a heat-dissipating substrate and a fabricating method thereof. The heat-dissipating substrate includes a plating layer divided by a first insulator formed in a division area. A metal plate is formed on an upper surface of the plating layer and filled with a second insulator at a position corresponding to the division area, with an anodized layer formed on a surface of the metal plate. A circuit layer is formed on the anodized layer which is formed on an upper surface of the metal plate. The heat-dissipating substrate and fabricating method thereof achieves thermal isolation by a first insulator formed in a division area and a second insulator.

Abstract: A method for manufacturing an organic device includes disposing a solution containing a conductive organic material in a first region on a substrate, drying the solution to form a conductive organic film in the first region, and irradiating the conductive organic film formed in a second region other than the first region with light to decrease the conductivity of the conductive organic film.

Abstract: The invention provides a method for preparing a pattern for an electric circuit comprising the steps of: (a) providing a substrate; (b) providing a pattern of an inhibiting material for an electrical circuit onto said substrate by i) applying a layer of the inhibiting material onto said substrate and mechanically removing locally the layer of the inhibiting material to obtain said pattern; or ii) applying a layer of the inhibiting material onto said substrate, wherein said layer has pre-determined pattern which incompletely covers said substrate; (c) establishing a distribution of particles of a first metal or alloy thereof on the layer of the inhibiting material and the pattern as obtained in step.

Abstract: A method of forming at least one electronic device on a substrate comprising creating a depository and an attached capillary; providing a liquid containing particles in the range 1 nanometer to 1 millimeter for deposit into the depository; the liquid flowing into the at least one capillary by capillary action; evaporating the liquid such that the particles form an agglomerate beginning at the end of the at least one capillary with a substantially uniform distribution of the particles within the agglomerate; whereby the agglomerate is used to form a part of the at least one electronic device. An microelectronic integrated circuit device comprising a substrate; a depository coupled to said substrate formed by at least one wall, a capillary channel coupled to said depository adapted to be filled with liquid comprising nanoparticles by capillary action, whereby as the liquid evaporates, an agglomerate forms in the capillary channel having a substantially uniform distribution of the particles.

Abstract: A touch screen sensor assembly and associated method for manufacturing the touch screen sensor assembly are provided. The touch screen assembly includes one or more transparent substrates that are arranged above a display. Each of the transparent substrates may include a conductive layer that is disposed adjacent to a surface of a corresponding one of the substrates. In addition, a set of conductive traces may be disposed on each of the transparent substrates and in conductive communication with the corresponding conductive layer. At least one of the sets of conductive traces may be deposited using electro deposition or vacuum deposition techniques so as to reduce a width of each trace, thereby reducing the size of a non-transparent border that surrounds the transparent substrates, maximizing the available portion of the transparent substrates for use in touch sensing.

Abstract: A method of forming an integrated silicon voltage regulator (ISVR) comprises providing a nano-encapsulated magnetic particle (NEMP) suspension, depositing a first layer of the NEMP suspension on an integrated circuit (IC) device, curing the first layer of the NEMP suspension to form a first NEMP composite layer, forming at least one inductor wire on the NEMP composite layer, depositing an interlayer dielectric material over the inductor wire, depositing a second layer of the NEMP suspension on the interlayer dielectric material, and curing the second layer of the NEMP suspension to form a second NEMP composite layer.

Abstract: A line pattern is formed on a substrate by performing a first step and a second step. In the first step, a liquid material containing a pattern formation material dispersed or dissolved therein is dropped onto the substrate and dried. In the second step, the liquid material is dropped onto a dried body that has been obtained by drying the liquid material in the first step. In the second step, the liquid material is dropped at a smaller ejection amount than that of the first step. Further, the pitch of dropping the liquid material onto the substrate in the first step and the pitch of dropping the liquid material onto the dried body in the second step are less than or equal to a jaggy generation limit.

Abstract: In a method for manufacturing a substrate, copper is applied to one surface of the substrate to form a plurality of circuit traces, defining one or more copper clearance areas therebetween. Dry film is coated on one portion of the circuit traces and the one or more copper clearance areas, and another portion of the plurality of copper traces remains uncoated. The dry film on the substrate is flattened to form a dry film layer. The other portion of the plurality of circuit traces is plated to form a plating layer. A surface of the plating layer is substantially coplanar with a surface of the dry film layer.

Abstract: A method for manufacturing a printed wiring board having one or more layers of a conductive pattern and an insulating pattern, including forming an insulating pattern on an insulating substrate; semi-hardening at least one of the insulating substrate and the insulating pattern; forming a conductive pattern on the insulating substrate and/or the insulating pattern, thereby providing a stack structure; performing a thermal treatment on the stack structure to fully harden the semi-hardened insulating substrate and/or insulating pattern; and firing the conductive pattern. In the method, the conductive pattern and the insulating pattern are simultaneously formed on the same layer using an inkjet process.

Abstract: A substrate has a first dielectric layer; a first conductive layer on the first dielectric layer; a second dielectric layer on the first conductive layer; an elongated signal conductor embedded within the second dielectric layer; a second conductive layer on the second dielectric layer; a first conductive groove and second conductive groove through the second conductive layer, the second dielectric layer, the first conductive layer and into the first dielectric layer and extending continuously along the length of and on opposing sides of the signal conductor, the grooves having conductive side walls providing an electrical connection between the first conductive layer and the second conductive layer; first and second conductive end walls joining the first groove and second groove; and at least one insulating area through at least one of the first and second conductive layers to provide conductor access.

Abstract: The insulation paste of the present invention contains (a) a glass powder, and (b) an organic solvent, wherein one or both of alumina (Al203) and titanium oxide (TiO2) are contained in the paste as a glass diffusion inhibitor, and the content of this glass diffusion inhibitor is 12 to 50% by weight based on the content of inorganic component in the paste.

Abstract: The present invention relates to a method for manufacturing a board that includes a conductive pattern, which comprises the steps of 1) discharging a conductive inorganic composition that includes a conductive inorganic metal particle on a substrate; 2) discharging a conductive organic composition that includes a conductive organic metal complex on the conductive inorganic composition; and 3) sintering the conductive inorganic composition and the conductive organic composition, and a board that includes a conductive pattern manufactured by using the same. A board that includes a conductive pattern according to the present invention may have high conductivity even though it is sintered at a lower sintering temperature than a board that includes a conductive pattern formed by using only an organic material or only an inorganic material.

Abstract: A method of manufacturing a multilayer wiring structure is disclosed. The method comprises a step of forming a via post on a first metal wiring element, a step of printing an interlayer insulation film on the first metal wiring element, with use of a screen mask having a non-ejection area slightly larger than a head of the via post, such that the interlayer insulation film has an upper surface at the level lower than the head of the via post, while generally aligning the non-ejection area with the head of the via post, a step of curing the interlayer insulation film, and a step of forming a second metal wiring element in contact with the via post on the interlayer insulation film such that the first metal wiring element and the second metal wiring element are connected through the via post.

Abstract: A method for forming electrical traces on a substrate includes the steps of: providing a substrate; printing an ink pattern using an ink on the substrate, the ink including a aqueous medium containing silver ions and a heat sensitive reducing agent; heating the ink pattern to reduce silver ions into silver particles thereby forming an semi-finished traces; and forming a metal overcoat on the semi-finished traces by electroless plating thereby obtaining patterned electrical traces.

Abstract: A method for low temperature bumping is disclosed. A resin capable of being cross-linked by free-radical or cationic polymerization at low temperature is provided. Electrically conductive particles are then added to the resin to form a mixture. The mixture is then activated by heat or exposure to light to polymerize the mixture. In an alternative embodiment, a vinyl ether resin is used, to which electrically conductive particles are added. The mixture is polymerized by exposure to light.

Abstract: A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The nanolayer deposition process is a cyclic sequential deposition process, comprising the first step of introducing a first plurality of precursors to deposit a thin film with the deposition process not self limiting, then a second step of purging the first set of precursors and a third step of introducing a second plurality of precursors to modify the deposited thin film. The deposition step in the NLD process using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film such as a modification of film composition, a doping or a removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film.

Abstract: A laminate comprising a polyimide and a conductor layer, which is obtained by forming at least one conductor layer directly on the surface of a thermoplastic polyimide, is thermally fused by pressurizing and heating to thereby enhance the adhesion strength between the thermoplastic polyimide and the conductor layer. Thus, a laminate having an excellent adhesion strength between a conductor layer and a polyimide film can be obtained without performing any surface roughening treatment or using any adhesive metal layer.

Abstract: The present invention provides a plated article that has a thin seed layer having uniform thickness, formed by electroless plating and allowing formation of ultrafine wiring, and that avoids the complicated formation of a bilayer of a barrier layer and a catalytic metal layer prior to forming the seed layer. The present invention also provides a method for manufacturing the plated article. The plated article has an alloy thin film formed on a substrate and having a catalytically active metal (A) for electroless plating and a metal (B) capable of undergoing displacement plating with a metal ion contained in an electroless plating solution, and a metal thin film formed on the alloy thin film by electroless displacement and reduction plating. The alloy thin film of the catalytically active metal (A) and the metal (B) capable of displacement plating has a composition comprising 5 at % to 40 at % of the metal (A).

Abstract: A method and apparatus are described for an electronic component package. A standoff is formed on an active side of a substrate. The substrate has an electronic circuit. A conductive layer is deposited over at least a portion of the active side of the substrate. The conductive layer electrically couples a contact area on the active side of the substrate. The standoff is removed to create a flexible conductor.

Abstract: A wiring board is provided that suppresses spreading of liquid droplets when liquid droplets are discharged using an ink-jet method. The wiring board has a plurality of layers and includes an ink-jet wiring pattern that is formed in a soluble porous membrane member of any single layer and that includes electrically conductive nanoparticles as a principal material, and a transferred wiring pattern that does not include electrically conductive nanoparticles as a principal material. One layer among the plurality of layers is an electrically insulative substrate. Another layer among the plurality of layers is a porous membrane treated member layer including a porous membrane member at one part of a region of the other layer. The ink-jet wiring pattern is formed in the porous membrane treated member layer. The transferred wiring pattern is formed in the substrate.

Abstract: A method of forming a circuit on a circuit board includes the following steps. Firstly, a surface of an insulating substrate is hydrophilically treated. Secondly, a first circuit layer having a number of electrical traces is formed on the hydrophilically treated surface, the first circuit layer is comprised of a soluble palladium salt. Thirdly, the soluble palladium salt of the first circuit layer is reduced into metallic palladium, thereby obtaining a second circuit layer comprised of metallic palladium. Lastly, an electrically conductive layer is formed on the second circuit layer.

Abstract: The present invention discloses a mixed-type heterojunction thin-film solar cell structure and a method for fabricating the same. Firstly, a conductive substrate and a template are provided, and the template has a substrate and an inorganic wire array formed on the substrate. Next, a conjugate polymer layer is formed on the conductive substrate. Next, the inorganic wire array is embedded into the conjugate polymer layer. Next, the substrate is separated from the inorganic wire array. Then, an electrode layer is formed over the inorganic wire array and the conjugate polymer layer. The solar cell structure of the present invention has advantages of flexibility, high energy conversion efficiency and low fabrication cost.

Abstract: A wired circuit board includes an insulating base layer, a conductive pattern formed on the insulating base layer, a tin-based thin layer formed on a surface of the conductive pattern, and containing at least tin oxide, and an insulating cover layer formed on the insulating base layer so as to cover the tin-based thin layer.

Abstract: A printed circuit board and a manufacturing method thereof are disclosed. The method of manufacturing a printed circuit board can include: forming surface roughness on an insulation layer, coating a chemical compound onto the insulation layer that lowers the surface energy of the insulation layer, and forming a circuit pattern by inkjet printing on the insulation layer coated with the chemical compound. Certain embodiments of the invention can be utilized to improve adhesive strength between the insulation layer and the inkjet-printed circuit patterns, suppress spreading in the inkjet-printed circuit patterns to improve resolution, and reduce manufacturing costs by forming the circuits using inkjet printing.

Abstract: A mounting region is provided at a substantially center of one surface of an insulating layer. A metal layer is provided on the other surface of the insulating layer. A slit is formed to cross a region (an opposite region) of the metal layer that coincides with the mounting region and to divide the metal layer. A plurality of regions (large regions) of the metal layer divided by the slit each include a partial region (small region) of the opposite region. The area of each large region is set corresponding to the area of the small region included therein. Specifically, the small region having the area of A [%] with respect to the whole area of the opposite region is included in the large region having the area of (A±?) [%] with respect to the whole area of the metal layer. Here, ? is an acceptable error range, and the acceptable error range ? is not more than (A×0.3).

Abstract: A circuit board having high thermal conductivity comprises a substrate, a plurality of thermal conductive insulating layers, a patterned electrical conductive layer, a plurality of through-holes and a soldering layer. The substrate has an upper surface and a lower surface; the thermal conductive insulating layers are respectively formed on the upper surface and the lower surface of the substrate. The patterned electrical conductive layer is disposed on the surfaces of the thermal conductive insulating layers. The plurality of through-holes are extended through the substrate and electrically connected to the patterned electrical conductive layer, and the soldering layer is partially formed on the patterned electric conductive layer. The present invention also discloses a method for manufacturing the circuit board as above-mentioned.

Abstract: A wiring board has a wiring board main body, a solder resist and solder bumps. The solder resist is formed on a top surface of the wiring board main body, and includes first openings, and second openings that have a diameter larger than that of the first openings. The solder bumps are disposed in the first openings and in the second openings. In addition, top portions of the solder bumps disposed in the first openings have a flat face, while top portions of the solder bumps disposed in the second openings have a non-flat face.

Abstract: Circuit carrier having a metal support layer, at least some portions of which are covered by a dielectric layer, the latter having a plurality of pores, with the pores being sealed by glass at least on the opposite side of the dielectric layer to the support layer.

Abstract: The wiring substrate 10 includes an insulating layer 13, a wiring 19, a bonding layer provided on such portion of the upper surface 13A of the insulating layer 13 as corresponds to the forming area of the wiring 19, and a seed layer 16 interposed between the bonding layer and wiring 19. The wiring substrate 10 further includes a Ni—Cu alloy layer 15 serving as the bonding layer.

Abstract: A method of fabricating an interconnect structure is described. A substrate is provided. A patterned interfacial metallic layer is formed on the substrate. An amorphous carbon insulating layer or a carbon-based insulating layer is formed covering the substrate and the interfacial metallic layer. A conductive carbon line or plug is formed in the amorphous carbon or carbon-based insulating layer electrically connected with the interfacial metallic layer. An interconnect structure is also described, including a substrate, a patterned interfacial metallic layer on the substrate, an amorphous carbon insulating layer or a carbon-based insulating layer on the substrate, and a conductive carbon line or plug disposed in the amorphous carbon or carbon-based insulating layer and electrically connected with the interfacial metallic layer.

Abstract: The electromagnetic wave shielding wiring circuit forming method of the present invention comprises the steps of: preparing a fine copper particle dispersion, by dispersing fine copper particles into a disperse medium (S) including an organic solvent (A) having an amide-based compound, an organic solvent (B) having a boiling point of 20° C. or higher at an ordinary pressure and having a donor number of 17 or more, an organic solvent (C) having a boiling point exceeding 100° C. at an ordinary pressure and comprising alcohol and/or polyhydric alcohol, and an organic solvent (E) having an amine-based compound, at specific ratios; coating or printing the fine copper particle dispersion onto a substrate, to form a wiring pattern comprising a liquid film of the fine copper particle dispersion; and firing the liquid film of the fine copper particle dispersion, to form a sintered wiring layer.

Abstract: The electromagnetic radiation detector compromises at least one radiation absorption membrane transforming the absorbed energy into heat transmitted to at least one resistive thermometer having a resistance varying with temperature. Each absorption membrane is suspended above a substrate by a nanowire connected to the central area of the membrane. The nanowire comprises an electrically conducting core and an electrically conducting external layer electrically insulated from one another and respectively connected to measuring areas of said thermometer. The nanowire serves the purpose both of support for the membrane and of electrical connection between the measuring areas and a circuit arranged at the level of the substrate.

Abstract: There is provided a method of manufacturing a non-shrinkage ceramic substrate, and a non-shrinkage ceramic substrate using the same.

Abstract: A conductive composition consisting essentially of (a) 50-95 wt % finely divided particles of an electrically-conductive material dispersed in (b) a liquid vehicle, for use in the manufacture of an electrically-conductive pattern on a substrate for the use of reducing cross-sectional area and width while retaining conductivity and resistivity.

Abstract: A disclosed laminated structure includes a wettability variable layer containing a wettability variable material whose surface energy changes when energy is applied thereto and including at least a high surface energy area having high surface energy and a low surface energy area having low surface energy; and a conductive layer disposed on the high surface energy area. The conductive layer includes a first high surface energy area, a second high surface energy area smaller in width than the first high surface energy area, and a third high surface energy area smaller in width than the second high surface energy area. The first high surface energy area and the second high surface energy area are connected by the third high surface energy area.

Abstract: A method for the attachment of solder powder includes the steps of treating an exposed metallic surface of an electronic circuit board with a tackifier compound, thereby imparting tackiness to the metallic surface to form a tacky part, and supplying the tacky part with a solder powder slurry suspended in a liquid, thereby inducing attachment of the solder powder. A method for the production of a soldered electronic circuit board, includes the steps of treating an exposed metallic surface of an electronic circuit board with a tackifier compound, thereby imparting tackiness to the metallic surface to form a tacky part; supplying the tacky part with a solder powder slurry suspended in a liquid, thereby inducing attachment of the solder powder, and thermally fusing the attached solder powder, thereby forming a circuit.

Abstract: A packaging substrate having an electrical connection structure and a method for fabricating the same are provided. The packaging substrate have a substrate body with a plurality of conductive pads on a surface thereof; a solder mask layer disposed on the substrate body with a plurality of openings corresponding to the conductive pads, the size of each of the openings being larger than each of the conductive pads; and electroplated solder bumps for covering the conductive pads to provide better bond strength and reliability.

Abstract: A method of manufacturing a multilayer wiring structure is disclosed. The method comprises a step of forming a via post on a first metal wiring element, a step of printing an interlayer insulation film on the first metal wiring element, with use of a screen mask having a non-ejection area slightly larger than a head of the via post, such that the interlayer insulation film has an upper surface at the level lower than the head of the via post, while generally aligning the non-ejection area with the head of the via post, a step of curing the interlayer insulation film, and a step of forming a second metal wiring element in contact with the via post on the interlayer insulation film such that the first metal wiring element and the second metal wiring element are connected through the via post.