Ge- Or Si-base Component Patents (Class 428/641)
  • Publication number: 20030207147
    Abstract: A post-etch treatment for enhancing and stabilizing the photoluminescence (PL) from a porous silicon (PS) substrate is outlined. The method includes treating the PS substrate with an aqueous hydrochloric acid solution and then treating the PS substrate with an alcohol. Alternatively, the post-etch method of enhancing and stabilizing the PL from a PS substrate includes treating the PS substrate with an aqueous hydrochloric acid and alcohol solution. Further, the PL of the PS substrate can be enhanced by treating the PS substrate with a dye. Furthermore, the PS substrate can be metallized to form a PS substrate with resistances ranging from 20 to 1000 ohms.
    Type: Application
    Filed: June 3, 2003
    Publication date: November 6, 2003
    Inventors: James L. Gole, Lenward T. Seals
  • Publication number: 20030207127
    Abstract: A composite of germanium film for a semiconductor device and methods of making the same. The method comprises growing a graded germanium film on a semiconductor substrate in a deposition chamber while simultaneously decreasing a deposition temperature and decreasing a silicon source gas and increasing a germanium source gas over a predetermined amount of time. The graded germanium film comprises an ultra-thin silicon-germanium buffer layer and a germanium film.
    Type: Application
    Filed: May 30, 2003
    Publication date: November 6, 2003
    Inventors: Anand Murthy, Ravindra Soman, Boyan Boyanov
  • Publication number: 20030203216
    Abstract: A bond pad structure formed over a predetermined area of an IC substrate comprising quickly and easily removable redundancy and passivation layers upon lithography and plasma etching in a plasma containing Cl2, the bond structure comprising:
    Type: Application
    Filed: April 30, 2002
    Publication date: October 30, 2003
    Applicant: Infineon Technologies North America Corp.
    Inventors: Gerald Friese, Werner K. Robl, Hans-Joachim Barth, Axel Brintzinger
  • Patent number: 6638629
    Abstract: A method and structure for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across a wafer surface. A substrate that includes a semiconductor material and a first dopant, has an amorphous layer formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. Heating of the wafer at 450 to 625 degree C. recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafer's surface.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: October 28, 2003
    Assignee: International Business Machines Corporation
    Inventors: Donna K. Johnson, Jerome B. Lasky, Glenn R. Miller
  • Publication number: 20030186073
    Abstract: A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 107cm−2 and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In another embodiment, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 107 cm−2; bonding the first substrate to the layered structure; and removing the second substrate.
    Type: Application
    Filed: March 18, 2003
    Publication date: October 2, 2003
    Applicant: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Publication number: 20030186033
    Abstract: A voltage variable composite structure comprising: a first layer of metal; a second layer of low-loss dielectric material impregnated with an array of first metal vias; a third layer of a voltage variable dielectric material; a fourth layer of a patterned thin metallic film; a fifth layer of low-loss dielectric material impregnated with an array of second metal vias; and a sixth layer of metal.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 2, 2003
    Inventor: William H. Henderson
  • Patent number: 6617010
    Abstract: A semiconductor thin film which is deposited by using a chemical vapor deposition method at an underlying layer temperature of 400° C. or less, and contains, as main component elements, a Group IV atom and hydrogen atom. A temperature dependency of an amount of release of hydrogen atoms within the film when the film is heated from room temperature exhibits a profile having a peak of the hydrogen releasing amount at 370° C. or higher and 410° C. or less, and a half-value width of the peak is 30° C. or less.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: September 9, 2003
    Assignee: Kaneka Corporation
    Inventors: Masashi Yoshimi, Takafumi Fujihara
  • Patent number: 6616857
    Abstract: A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7 A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: September 9, 2003
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Tingkai Li, Fengyan Zhang, Yoshi Ono, Sheng Teng Hsu
  • Patent number: 6617055
    Abstract: At least a portion of a free layer structure in a spin valve sensor is composed of nickel iron molybdenum (NiFeMo) so that the free layer structure does not have to be reduced in thickness in order to have a reduced magnetic moment for responding to lower signal fields from smaller bits on a rotating magnetic disk.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: September 9, 2003
    Assignee: International Business Machines Corporation
    Inventor: Hardayal Singh Gill
  • Publication number: 20030165697
    Abstract: A B-doped Si1-x-yGexCy layer 102 (where 0<x<1, 0.01≦y<1) is epitaxially grown on a Si substrate 101 using a UHV-CVD process. In the meantime, in-situ doping is performed using B2H6 as a source gas of boron (B) which is an impurity (dopant). Next, the Si1-x-yGexCy layer 102 is annealed to form a B-doped Si1-x-yGexCy crystalline layer 103. In this case, the annealing temperature is set preferably at between 700° C. and 1200° C., both inclusive, and more preferably at between 900° C. and 1000° C., both inclusive.
    Type: Application
    Filed: March 10, 2003
    Publication date: September 4, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tohru Saitoh, Yoshihiko Kanzawa, Katsuya Nozawa, Minoru Kubo
  • Patent number: 6607845
    Abstract: A rewritable or write-once medium with increased recording density and sensitivity is disclosed, the medium having at least a first dielectric layer, a recording layer and a second dielectric layer in this order on a substrate, wherein at least one of the first and second dielectric layers is formed by applying a colloidal dispersion which comprises inorganic dielectric nanoparticles having an average particle size of 1 to 50 nm and having the surface thereof modified with an adsorptive compound, and the recording layer is formed by applying a colloidal dispersion which comprises metal chalcogenide nanoparticles having an average particle size of 1 to 20 nm and having the surface thereof modified with an adsorptive compound. The dielectric layer and the recording layer are formed by spin coating or web coating.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: August 19, 2003
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Hiroyuki Hirai, Koukichi Waki, Takashi Ozawa
  • Patent number: 6607847
    Abstract: An article, such as an airfoil having a melting temperature of at least about 1500° C. and comprising a first piece and a second piece joined by a braze to the first piece. The first piece comprises one of a first niobium-based refractory metal intermetallic composite and a first molybdenum-based refractory metal intermetallic composite, and the second piece comprises one of a second niobium-based refractory metal intermetallic composite and a second molybdenum-based refractory metal intermetallic composite. The braze joining the first piece to the second piece comprises a first metallic element and a second metallic element, wherein the first metallic element is one of titanium, palladium, zirconium, niobium, and hafnium, and wherein the second metallic element is one of titanium, palladium, zirconium, niobium, hafnium, aluminum, chromium, vanadium, platinum, gold, iron, nickel, and cobalt, the first metallic element being different from the second metallic element.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: August 19, 2003
    Assignee: General Electric Company
    Inventors: Ji-Cheng Zhao, Melvin Robert Jackson, Bernard Patrick Bewlay
  • Patent number: 6605369
    Abstract: The present invention is directed to provision of a surface-treated copper foil exhibiting a maximum effect of a silane coupling agent which is adsorbed onto the copper foil and is employed in order to enhance adhesion between the copper foil and a substrate during manufacture of printed wiring boards. The invention is also directed to provision of a method for producing such a copper foil. To attain these goals, a surface-treated copper foil for producing printed wiring boards is provided, wherein an anti-corrosion treatment comprises forming a zinc layer or a zinc alloy layer on a surface of the copper foil and forming an electrodeposited chromate layer on the zinc or zinc alloy layer; forming a silane-coupling-agent-adsorbed layer on the electrodeposited chromate layer without causing the electrodeposited chromate layer of the nodular-treated surface to dry; and drying.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: August 12, 2003
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Naotomi Takahashi, Yutaka Hirasawa
  • Patent number: 6602613
    Abstract: A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 107 cm−2 and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In another embodiment, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 107 cm−2; bonding the first substrate to the layered structure; and removing the second substrate.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: August 5, 2003
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Patent number: 6586118
    Abstract: An airfoil having a melting temperature of at least about 1500° C. and comprising a first piece and a second piece joined by a braze to the first piece. The first piece comprises one of a first niobium-based refractory metal intermetallic composite and a first-based refractory metal intermetallic composite, and the second piece comprises one of a second niobium-based refractory metal intermetallic composite and a second molybdenum-based refractory metal intermetallic composite. The braze joining the first piece to the second piece is a semi-solid braze that comprises a first component and a second component.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: July 1, 2003
    Assignee: General Electric Company
    Inventors: Melvin Robert Jackson, Bernard Patrick Bewlay, Ji-Cheng Zhao
  • Patent number: 6586121
    Abstract: A spin-valve thin-film magnetic element includes a substrate; an antiferromagnetic layer; a pinned magnetic layer in contact with the antiferromagnetic layer, the magnetization direction of the pinned magnetic layer being pinned by an exchange coupling magnetic field with the antiferromagnetic layer; a nonmagnetic conductive layer in contact with the pinned magnetic layer; a free magnetic layer in contact with the nonmagnetic conductive layer, the magnetization direction of the free magnetic layer being aligned in a direction perpendicular to the magnetization direction of the pinned magnetic layer; and a back layer composed of a nonmagnetic conductive material formed in contact with the free magnetic layer at the opposite side of the nonmagnetic conductive layer. The back layer is composed of at least one metal selected from the group consisting of Ru, Pt, Ir, Rh, Pd, Os, and Cr.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: July 1, 2003
    Assignee: Alps Electric Co., Ltd.
    Inventors: Yosuke Ide, Masamichi Saito, Kenichi Tanaka, Naoya Hasegawa
  • Patent number: 6582827
    Abstract: Substrates having modified effective thermal conductivity for use in the sequential lateral solidification process are disclosed. In one arrangement, a substrate includes a glass base layer, a low conductivity layer formed adjacent to a surface of the base layer, a high conductivity layer formed adjacent to the low conductivity layer, a silicon compound layer formed adjacent to the high conductivity layer, and a silicon layer formed on the silicon compound layer. In an alternative arrangement, the substrate includes an internal subsurface melting layer which will act as a heat reservoir during subsequent sequential lateral solidification processing.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: June 24, 2003
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Patent number: 6572974
    Abstract: Changes in the infrared reflection spectrum of a thin film of silica-like resinous material sandwiched between metal electrodes can be induced by applying an electric potential to a top electrode which is semitransparent. Characteristic infrared absorption lines change in proportion to a small electric current flowing through the material. These changes occur with response times of the order of seconds, and show time constants of the order of minutes to reach stationary values.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: June 3, 2003
    Assignee: The Regents of the University of Michigan
    Inventors: Mark Angelo Biscotte, Mark Monroe Banaszak Holl, Bradford Grant Orr, Udo C. Pernisz
  • Patent number: 6565989
    Abstract: An airfoil having a melting temperature of at least about 1500° C. and comprising a first piece and a second piece joined by a braze to the first piece. The first piece comprises one of a first niobium-based refractory metal intermetallic composite and a first molybdenum-based refractory metal intermetallic composite, and the second piece comprises one of a second niobium-based refractory metal intermetallic composite and a second molybdenum-based refractory metal intermetallic composite. The braze joining the first piece to the second piece comprises one of germanium and silicon, and one of chromium, titanium, gold, aluminum, palladium, platinum, and nickel. This abstract is submitted in compliance with 37 C.F.R. 1.72(b) with the understanding that it will not be used to interpret or limit the scope of or meaning of the claims.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: May 20, 2003
    Assignee: General Electric Company
    Inventors: Ji-Cheng Zhao, Melvin Robert Jackson, Bernard Patrick Bewlay
  • Publication number: 20030087121
    Abstract: According to various embodiments and aspects of the present invention, there is provided a dynamically tunable thin film interference coating including one or more layers with thermo-optically tunable refractive index. Tunable layers within thin film interference coatings enable a new family of thin film active devices for the filtering, control, modulation of light. Active thin film structures can be used directly or integrated into a variety of photonic subsystems to make tunable lasers, tunable add-drop filters for fiber optic telecommunications, tunable polarizers, tunable dispersion compensation filters, and many other devices.
    Type: Application
    Filed: June 17, 2002
    Publication date: May 8, 2003
    Inventors: Lawrence Domash, Eugene Ma, Robert Murano, Nikolay Nemchuk, Adam Payne, Steven Sherman, Matthias Wagner, Ming Wu
  • Publication number: 20030054194
    Abstract: An environmentally resistant coating comprising silicon, titanium, chromium, and a balance of niobium and molybdenum for turbine components formed from molybdenum silicide-based composites. The turbine component may further include a thermal barrier coating disposed upon an outer surface of the environmentally resistant coating comprising zirconia, stabilized zirconia, zircon, mullite, and combinations thereof. The molybdenum silicide-based composite turbine component coated with the environmentally resistant coating and thermal barrier coating is resistant to oxidation at temperatures in the range from about 2000° F. to about 2600° F. and to pesting at temperatures in the range from about 1000° F. to about 1800° F.
    Type: Application
    Filed: September 24, 2002
    Publication date: March 20, 2003
    Inventors: Ji-Cheng Zhao, Bernard Patrick Bewlay, Melvin Robert Jackson
  • Patent number: 6521356
    Abstract: An environmentally resistant coating for improving the oxidation resistance of a niobium-based refractory metal intermetallic composite (Nb-based RMIC) at high temperatures, the environmentally resistant coating comprising silicon, titanium, chromium, and niobium. The invention includes a turbine system having turbine components comprising at least one Nb-based RMIC, the environmentally resistant coating disposed on a surface of the Nb-based RMIC, and a thermal barrier coating disposed on an outer surface of the environmentally resistant coating. Methods of making a turbine component having the environmentally resistant coating and coating a Nb-based RMIC substrate with the environmentally resistant coating are also disclosed.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: February 18, 2003
    Assignee: General Electric Company
    Inventors: Ji-Cheng Zhao, Melvin Robert Jackson, Bernard Patrick Bewlay
  • Patent number: 6511760
    Abstract: A method of passivating the interior surface of a gas storage vessel to protect the surface against corrosion. The interior surface of the vessel is first dehydrated and then evacuated. A silicon hydride gas is introduced into the vessel. The vessel and silicon hydride gas contained therein are heated and pressurized to decompose the gase. A layer of silicon is deposited on the interior surface of the vessel. The duration of the silicon depositing step is controlled to prevent the formation of silicon dust in the vessel. The vessel is then purged with an inert gas to remove the silicon hydride gas. The vessel is cycled through the silicon depositing step until the entire interior surface of the vessel is covered with a layer of silicon. The vessel is then evacuated and cooled to room temperature.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: January 28, 2003
    Assignee: Restek Corporation
    Inventors: Gary A. Barone, Andy S. Schuyler, Joseph Stauffer
  • Publication number: 20030008505
    Abstract: Self-assembled nanowires are provided, comprising nanowires of a first crystalline composition formed on a substrate of a second crystalline composition. The two crystalline materials are characterized by an asymmetric lattice mismatch, in which in the interfacial plane between the two materials, the first material has a close lattice match (in any direction) with the second material and has a large lattice mismatch in all other major crystallographic directions with the second material. This allows the unrestricted growth of the epitaxial crystal in the first direction, but limits the width in the other. The nanowires are grown by first selecting the appropriate combination of materials that fulfill the foregoing criteria. The surface of the substrate on which the nanowires are to be formed must be cleaned in order (1) to ensure that the surface has an atomically flat, regular atomic structure on terraces and regular steps and (2) to remove impurities.
    Type: Application
    Filed: November 13, 2001
    Publication date: January 9, 2003
    Inventors: Yong Chen, R. Stanley Williams, Douglas A. A. Ohlberg
  • Patent number: 6497968
    Abstract: An environmentally resistant coating comprising silicon, titanium, chromium, and a balance of niobium and molybdenum for turbine components formed from molybdenum silicide-based composites. The turbine component may further include a thermal barrier coating disposed upon an outer surface of the environmentally resistant coating comprising zirconia, stabilized zirconia, zircon, mullite, and combinations thereof. The molybdenum silicide-based composite turbine component coated with the environmentally resistant coating and thermal barrier coating is resistant to oxidation at temperatures in the range from about 2000° F. to about 2600° F. and to pesting at temperatures in the range from about 1000° F. to about 1800° F.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: December 24, 2002
    Assignee: General Electric Company
    Inventors: Ji-Cheng Zhao, Bernard Patrick Bewlay, Melvin Robert Jackson
  • Publication number: 20020182423
    Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm−3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.
    Type: Application
    Filed: April 20, 2001
    Publication date: December 5, 2002
    Applicant: International Business Machines Corporation
    Inventors: Jack Oon Chu, Basanth Jagannathan, Alfred Grill, Bernard Steele Meyerson, John Albrecht Ott
  • Patent number: 6489041
    Abstract: A practically realizable semiconductor magnetic body having a flat-band structure is disclosed. The semiconductor magnetic body is formed by semiconductor quantum dots arranged on lattice points such that electrons can transfer between neighboring quantum dots and the electron energy band contains a flat-band structure, where each quantum dot is a structure in which electrons are confined inside a region which is surrounded by high energy potential regions, and the flat-band structure is a band structure in which energy dispersion of electrons has hardly any wave number dependency.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: December 3, 2002
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hiroyuki Tamura, Kenji Shiraishi, Hideaki Takayanagi
  • Patent number: 6489005
    Abstract: A silicon article including a silicon base and columns extending from the silicon base. The columns define a gap between the columns which is devoid of material so that the article can act as a filter or heat sink. Also disclosed is a method of making the silicon article.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: December 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: Michael D. Armacost, Peter D. Hoh, Son V. Nguyen
  • Publication number: 20020119340
    Abstract: An environmentally resistant coating comprising silicon, titanium, chromium, and a balance of niobium and molybdenum for turbine components formed from molybdenum silicide-based composites. The turbine component may further include a thermal barrier coating disposed upon an outer surface of the environmentally resistant coating comprising zirconia, stabilized zirconia, zircon, mullite, and combinations thereof. The molybdenum silicide-based composite turbine component coated with the environmentally resistant coating and thermal barrier coating is resistant to oxidation at temperatures in the range from about 2000° F. to about 2600° F. and to pesting at temperatures in the range from about 1000° F. to about 1800° F.
    Type: Application
    Filed: February 26, 2001
    Publication date: August 29, 2002
    Applicant: General Electric Company
    Inventors: Ji-Cheng Zhao, Bernard Patrick Bewlay, Melvin Robert Jackson
  • Patent number: 6413310
    Abstract: Silicon single crystal wafers for semiconductor devices of high quality are obtained with high productivity by effectively reducing or eliminating grown-in defects in surface layers of silicon single crystal wafers produced by the CZ method. The present invention provides a method for producing a silicon single crystal wafer, which comprises growing a silicon single crystal ingot by the Czochralski method, slicing the single crystal ingot into a wafer, subjecting the wafer to a heat treatment at a temperature of 1100-1300° C. for 1 minute or more under a non-oxidative atmosphere, and successively subjecting the wafer to a heat treatment at a temperature of 700-1300° C. for 1 minute or more under an oxidative atmosphere without cooling the wafer to a temperature lower than 700° C. The present invention also provides a CZ silicon single crystal wafer, wherein density of COPs having a size of 0.09 &mgr;m or more in a surface layer having a thickness of up to 5 &mgr;m from a surface is 1.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: July 2, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masaro Tamatsuka, Norihiro Kobayashi, Shoji Akiyama, Masaru Shinomiya
  • Patent number: 6391479
    Abstract: A coated metal component made of an alloy containing an intentional addition of nitrogen, comprising an oxidation-resistant coating layer and an intermediate layer disposed between the oxidation-resistant coating layer and the component. The intermediate layer is substantially devoid of nitrogen which if present would form a nitride with the oxidation-resistant layer.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: May 21, 2002
    Assignee: General Electric Company
    Inventor: John Herbert Wood
  • Publication number: 20020018913
    Abstract: A magneto-optical body with a reduced manufacturing cost and an improved yield and an optical isolator using the same are provided. The magneto-optical body includes two dielectric multilayered films each consisting of a Si thin film having a refractive index (Ms) of 3.11 and a SiO2 thin film having a refractive index (Mt) of 1.415 and provided at both sides of a magnetic thin film. By using the dielectric multilayered films each comprising two types of dielectric thin films having a refractive index largely different from each other, light is intensely localized at the center. A great magneto-optical effect may be obtained and a large Faraday rotation angle may be obtained with a reduced number of layers of the dielectric thin films. A manufacturing cost is reduced, and process control also is relaxed, thereby improving a manufacturing yield.
    Type: Application
    Filed: August 1, 2001
    Publication date: February 14, 2002
    Applicant: Minebea Co., Ltd.
    Inventors: Hideki Kato, Mitsuteru Inoue, Akio Takayama
  • Patent number: 6344281
    Abstract: IC fabrication employs the deposition of aluminum as a metallization layer. Frequently, the aluminum is doped with copper in small amounts to improve electric properties. Low temperature deposition of these layers is preferred to ensure the proper microstructure and surface roughness. Low temperature deposition (below about 300° C.) results in the formation of copper precipitates which can be difficult to remove. Annealing the layer formed, either prior to, or after formation of capping layers and additional layers thereon, drives the copper precipitate back into solution, permitting small dimension fabrication.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: February 5, 2002
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mark Smith, Ivan Ivanov, Frederick Eisenmann
  • Publication number: 20020006525
    Abstract: A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.
    Type: Application
    Filed: August 28, 2001
    Publication date: January 17, 2002
    Applicant: Micron Technology, Inc.
    Inventors: Gurtej Singh Sandhu, Donald L. Westmoreland
  • Patent number: 6335104
    Abstract: A method for preparing a copper pad surface for electrical connection that has superior diffusion barrier and adhesion properties is provided. In the method, a copper pad surface is first provided that has been cleaned by an acid solution, a protection layer of a phosphorus or boron-containing metal alloy is then deposited on the copper pad surface, and then an adhesion layer of a noble metal is deposited on top of the protection layer. The protection layer may be a single layer, or two or more layers intimately joined together formed of a phosphorus or boron-containing metal alloy such as Ni-P, Co-P, Co-W-P, Co-Sn-P, Ni-W-P, Co-B, Ni-B, Co-Sn-B, Co-W-B and Ni-W-B to a thickness between about 1,000 Å and about 10,000 Å. The adhesion layer can be formed of a noble metal such as Au, Pt, Pd and Ag to a thickness between about 500 Å and about 4,000 Å.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: January 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Carlos J. Sambucetti, Daniel C. Edelstein, John G. Gaudiello, Judith M. Rubino, George Walker
  • Publication number: 20010052573
    Abstract: A target mark member having a mark pattern with a plurality of marks and a controlled width of the marks provides accuracy and efficiency in electron beam shape measurement and focus of the electron beam. The target mark member for adjusting a focus of an electron beam and measuring a shape of said electron beam in an electron beam processing apparatus includes a metal mark portion having a predetermined mark pattern, said metal mark portion comprising an epitaxial metal material; and a substrate that supports said metal mark portion.
    Type: Application
    Filed: June 14, 2001
    Publication date: December 20, 2001
    Applicant: ADVANTEST CORPORATION
    Inventor: Masaki Takakuwa
  • Patent number: 6329070
    Abstract: The periodic stress and strain fields produced by a pure twist grain boundary between two single crystals bonded together in the form of a bicrystal are used to fabricate a two-dimensional surface topography with controllable, nanometer-scale feature spacings (e.g., from 50 nanometers down to 1.5 nanometers). The spacing of the features is controlled by the misorientation angle used during crystal bonding. One of the crystals is selected to be thin, on the order of 5-100 nanometers. A buried periodic array of screw dislocations is formed at the twist grain boundary. To bring the buried periodicity to the surface, the thin single crystal is etched to reveal an array of raised elements, such as pyramids, that have nanometer-scale dimensions. The process can be employed with numerous materials, such as gold, silicon and sapphire. In addition, the process can be used with different materials for each crystal such that a periodic array of misfit dislocations is formed at the interface between the two crystals.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: December 11, 2001
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Stephen L. Sass, Christopher K. Ober, Yuri Suzuki
  • Patent number: 6329074
    Abstract: This invention provides a copper foil for a printed wiring board, which comprises a copper foil, an alloy layer (A) comprising copper, zinc, tin and nickel which is formed on a surface of the copper foil, said surface to be brought into contact with a substrate for a printed wiring board, and a chromate layer which is formed on a surface of the alloy layer (A,. The copper foil for a printed wiring board has the following features: even if a printed wiring board is produced using a long-term stored copper foil, the interface between the copper foil and the substrate is only slightly corroded with chemicals; even if the copper foil contacts a varnish containing an organic acid, e.g., a varnish for an acrylic resin, in the formation of a copper-clad laminate, the bond strength is sufficient. Even if a printed circuit board made by using the copper foil is placed in a high temperature environment, e.g.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: December 11, 2001
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Kazuhisa Fujiwara, Hiroshi Tan, Mitsuo Fujii, Masanobu Tsushima
  • Patent number: 6329063
    Abstract: A method for producing a stress-engineered substrate includes selecting first and second materials for forming the substrate. An epitaxial material for forming a heteroepitaxial layer is then selected. If the lattice constant of the heteroepitaxial layer (aepi) is greater than that (asub) of the immediate substrate layer the epitaxial layer is deposited on, then the epitaxial layer is kept under “compressive stress” (negative stress) at all temperatures of concern. On the other hand, if the lattice constant of the heteroepitaxial layer (aepi) is less than that (asub) of the immediate substrate layer the epitaxial layer is deposited on, then the epitaxial layer is kept under “tensile stress” (positive stress). The temperatures of concern range from the annealing temperature to the lowest temperature where dislocations are still mobile.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: December 11, 2001
    Assignee: Nova Crystals, Inc.
    Inventors: Yu-Hwa Lo, Felix Ejeckam
  • Publication number: 20010041258
    Abstract: A standard for calibrating and checking a nanotopography unit, includes a substrate and at least one structure which is deposited on the substrate. It has a lateral extent of 0.5 to 20 mm and a vertical extent of 5 to 500 nm and is bounded by edges which have a gradient of at most 1*10−3. There is also a method for producing the standard, with material being deposited on the substrate at an inhomogeneous deposition rate.
    Type: Application
    Filed: March 28, 2001
    Publication date: November 15, 2001
    Applicant: WACKER SILTRONIC GESELLSCHAFT FUR HALBLEITERMATERIALIEN AG
    Inventors: Friedrich Passek, Reinhard Schauer, Rudiger Schmolke, Ralf Kumpe
  • Patent number: 6315830
    Abstract: In a molten metal plating apparatus all surfaces of a sinking roller and a supporting roller to be in contact with a molten metal are coated with iron silicide films. A bearing comprises a holder made of a heat resistant steel and lined with a carbon-carbon fiber complex material. A surface of the holder is coated with an Fe3Si film similar to the sinking roller. There is an Fe3Si film on a surface of a shaft portion, and the Fe3Si is in contact with and slides on the carbon-carbon fiber complex material.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: November 13, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Nakagawa, Yukio Saito, Junji Sakai, Osamu Shitamura, Yasutsugu Yoshimura, Yoshio Takakura, Hironori Shimogama, Takehisa Kimura
  • Patent number: 6316123
    Abstract: The present invention is directed to a method of forming a new material layer or region near an interface region of two dissimilar materials, and an optional third layer, wherein at least one of said dissimilar materials or optional third is capable of being heated by microwave energy. The method of the present invention includes a step of irradiating a structure containing at least two dissimilar materials and an optional third layer under conditions effective to form the new material layer in the structure. An apparatus for conducting the microwave heating as well as the structures formed from the method are also described herein.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: November 13, 2001
    Assignee: International Business Machines Corporation
    Inventors: Kam Leung Lee, David Andrew Lewis, Ronnen Andrew Roy, Raman Gobichettipalayam Viswanathan
  • Patent number: 6316132
    Abstract: A structure and method to prevent barrier failure is provided. The present invention replaces a standard titanium-nitride (TiN) barrier metal layer with two separately-formed TiN layers. The two TiN layers provide smaller, mismatched grain boundaries. During subsequent tungsten deposition using WF6, the WF6 finds it difficult to penetrate through the mismatched grain boundaries, thereby minimizing any possibility of “tungsten volcano”. One embodiment includes a native or a grown oxide formed between the two TiN layers, thereby providing yet another diffusion barrier to the WF6 and acting as a glue layer between the two TiN layers. The present invention provides a thin and strong barrier metal layer with minimal barrier failures.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: November 13, 2001
    Assignee: Xilinx, Inc.
    Inventor: James Karp
  • Patent number: 6299986
    Abstract: A high rhenium-containing nickel superalloy article (10) has a multilayer coating (12) comprising a barrier coating (14) and an aluminide coating (16). The aluminide coating (16) is a corrosion and oxidation protective coating for the superalloy article (10). The barrier coating (14) comprises an alloy with a similar composition to the high rhenium-containing nickel superalloy article (10) but with less rhenium. The barrier coating (14) minimises diffusion of elements between the aluminide coating (16) and the superalloy article (10) to minimise the formation of topologically close packed phases at the interface between the superalloy article (10) and the multilayer coating (12). The barrier coating (12) preferably has some rhenium to minimise diffusion of rhenium from the superalloy article (10) to the barrier coating (14).
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: October 9, 2001
    Assignee: Rolls-Royce plc
    Inventor: Meehar C. Meelu
  • Publication number: 20010019737
    Abstract: A method of treating structures (and the structure formed thereby), so as to prevent or retard the oxidation of a metal film, and/or prevent its delamination a substrate, includes providing a structure including a refractory metal film formed on a substrate, placing the structure into a vessel having a base pressure below approximately 10−7 torr, exposing the structure to a silane gas at a sufficiently high predetermined temperature and predetermined pressure to cause formation of a metal silicide layer on the refractory metal film, and exposing the structure to a second gas at a sufficiently high temperature and pressure to nitride the metal silicide layer into a nitrided layer.
    Type: Application
    Filed: March 23, 2001
    Publication date: September 6, 2001
    Inventors: Kevin K. Chan, Erin C. Jones, Fenton R. McFeely, Paul M. Solomon, John J. Yurkas
  • Patent number: 6277501
    Abstract: The present invention has as an objective providing a silicon epi-wafer, and a manufacturing method therefor, which simplifies processing as much as possible in an attempt to lower the cost of an epi-wafer, and which is capable of manifesting a sufficient IG effect even in low-temperature device fabrication processing of under 1080° C. in an epi-wafer, and furthermore, in device processing, which enhances gettering capabilities for a variety of impurities in wafer device processing, without performing, following wafer slicing, any process from which an EG effect can be anticipated. As for the silicon single crystal, which is grown via the CZ method so as to make the oxygen concentration relatively high, and to intentionally make the carbon concentration high, outstanding gettering capabilities are manifested in the wafer itself, without performing EG processing.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: August 21, 2001
    Assignee: Sumitomo Metal Industries, Ltd.
    Inventor: Takashi Fujikawa
  • Patent number: 6270573
    Abstract: A silicon carbide thin film is epitaxially grown by an MBE or the like method with silicon atoms 2 being maintained to be in excess of carbon atoms on a growth surface 1a of a silicon carbide crystal in a substrate 1. A silicon carbide substrate with a good crystallinity is thereby achieved at a low temperature with a good reproducibility. This crystal growth is possible at a low temperature of 1300° C. or lower, and the productions of a high-concentration doped film, a selectively grown film, and a grown film of a cubic silicon carbide on a hexagonal crystal are achieved. In crystallizing a cubic silicon carbide on a hexagonal crystal, the use of an off-cut surface inclined towards a <1{overscore (1)}00> direction is effective to prevent an occurrence of twin.
    Type: Grant
    Filed: April 26, 1999
    Date of Patent: August 7, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Makoto Kitabatake, Masao Uchida, Kunimasa Takahashi
  • Patent number: 6268068
    Abstract: Multi-layer assemblies of polysilicon thin films having predetermined stress characteristics and techniques for forming such assemblies are disclosed. In particular, a multi-layer assembly of polysilicon thin film may be produced that has a stress level of zero, or substantially so. The multi-layer assemblies comprise at least one constituent thin film having a tensile stress and at least one constituent thin film having a compressive stress. The thin films forming the multi-layer assemblies may be disposed immediately adjacent to one another without the use of intermediate layers between the thin films.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: July 31, 2001
    Assignee: Case Western Reserve University
    Inventors: Arthur H. Heuer, Harold Kahn, Jie Yang
  • Patent number: 6261705
    Abstract: To provide a poly-Si film which has excellence in its characteristics themselves concerning transistor characteristics, such as the diffusion and precipitation of dopant, the interface and surface state or the carrier mobility, and excellence in controllability of those characteristics as well, a poly-Si film grown on an amorphous layer (12) comprises; a base layer (131) interfacing with the amorphous layer (12) and having a preferred orientation rate comparatively high; a low-energy layer (133) grown at an upper side of the base layer (131) and having a preferred orientation rate which varies little and is lower than the preferred orientation rate of the base layer (131); and a surface layer (135) grown at the upper side of the low-energy layer (133) and having a preferred orientation rate which becomes higher towards a surface of the poly-Si film.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: July 17, 2001
    Assignee: NEC Corporation
    Inventors: Akio Tanikawa, Hiroshi Okumura
  • Publication number: 20010007718
    Abstract: A practically realizable semiconductor magnetic body having a flat-band structure is disclosed. The semiconductor magnetic body is formed by semiconductor quantum dots arranged on lattice points such that electrons can transfer between neighboring quantum dots and the electron energy band contains a flat-band structure, where each quantum dot is a structure in which electrons are confined inside a region which is surrounded by high energy potential regions, and the flat-band structure is a band structure in which energy dispersion of electrons has hardly any wave number dependency.
    Type: Application
    Filed: December 8, 2000
    Publication date: July 12, 2001
    Inventors: Hiroyuki Tamura, Kenji Shiraishi, Hideaki Takayanagi