Registration Or Layout Process Other Than Color Proofing Patents (Class 430/22)
  • Patent number: 7211369
    Abstract: The invention relates to using VLSI techniques to store information on a substrate. One embodiment of a die with text deposited upon the die uses semiconductor processing techniques during fabrication. Included in the die are a substrate, a first paragraph and a second paragraph. The first and second paragraphs are in contact with the substrate. The second paragraph is aligned with the first paragraph in a column.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: May 1, 2007
    Inventors: Pawan Sinha, Pamela R. Lipson, Keith R. Kluender
  • Patent number: 7211354
    Abstract: A mask substrate comprises a transparent substrate including a reference mark and a light shielding film formed on the transparent substrate.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: May 1, 2007
    Assignees: Kabushiki Kaisha Toshiba, Dai Nippon Printing Co., Ltd.
    Inventor: Masamitsu Itoh
  • Patent number: 7212286
    Abstract: A method of selecting alignment marks, to be detected, from a plurality of alignment marks formed on a substrate includes the step of calculating a deviation between a distance of a designed position of an alignment mark from a reference position and a reference value, with respect to each of the plurality of alignment marks. The alignment marks, to be detected, are selected based on the deviations.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: May 1, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tai Hoshi
  • Patent number: 7192676
    Abstract: The present invention provides an MR element bar that permits the fabrication of MR elements in which a variation in characteristics is suppressed, as well as an MR element bar exposure method and formation method enabling the fabrication of the MR element bar. The MR element bar exposure method according to the present invention comprises the steps of: detecting the positions of a plurality of alignment marks P1 to P4 formed on a wafer W; correcting an exposure position correction region R on the basis of the positions of detected alignment marks P1? to P4?; and exposing a resist which is formed on the wafer W, wherein an MR element bar region B comprises a plurality of MR elements (patterns MRE) aligned in the longitudinal direction of the region B, and one exposure position correction region R is established for one MR element bar region B.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: March 20, 2007
    Assignee: TDK Corporation
    Inventors: Teruyo Kagotani, legal representative, Hitoshi Hatate, Noriaki Kasahara, Tetsuya Kuwashima, Tsuneo Kagotani, deceased
  • Patent number: 7193715
    Abstract: A method for measuring overlay in semiconductor wafers includes obtaining diffraction based and imaging based measurements of the same target. The two separate measurements are then combined in a way that is consistent to both measurements to obtain an overlay measurement that has high precision and large range.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: March 20, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Rodney Smedt, Abdurrahman Sezginer, Hsu-Ting Huang
  • Patent number: 7190456
    Abstract: An apparatus for determining positions of a plurality of regions formed on a substrate based on positions of a plurality of sample regions sampled from the plurality of regions. The apparatus includes a processor configured to control operation of a stage and an alignment optical system so as to obtain positions of the plurality of the sample regions sampled from the plurality of regions, to calculate a first conversion parameter and a second conversion parameter for converting designed positions of the plurality of regions into first and second determined positions of the plurality of regions based on at least designed positions of the plurality of the sample regions and positions of the plurality of the sample regions measured by the alignment optical system, and to determine whether to finish the position determinations based on a difference between the first conversion parameter and the second conversion parameter.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: March 13, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takeshi Yamamoto
  • Patent number: 7186484
    Abstract: A measurement mark (3) for determining the relative positional accuracy of a progressive projection onto a wafer (5), the projection being performed with two masks (3, 4), comprising two structure elements (10, 20) formed on a respective one of the masks (1, 2). The structure elements (10, 20) overlap with regard to their position on the masks so that, during the projection of the second structure element (20), an electrically conductive structure (30) formed on the basis of the first structure element on the wafer (5) is overformed by removal of a portion (31). In an electrical line width measurement, the reduced width (CD, CD30a) of the structure (30) is measured and compared either with the original width (62) or with that width (CD30b) of a further partial element (30b) produced by the overforming.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: March 6, 2007
    Assignee: Infineon Technologies AG
    Inventors: Heiko Hommen, Jens Stäcker, Maria de la Piedad Fernandez-Martinez, Jens Uwe Bruch, Thorsten Schedel
  • Patent number: 7186483
    Abstract: The present invention includes a method of aligning a substrate and a template spaced-apart from the substrate with an activating light curable liquid disposed therebetween, the substrate having substrate alignment marks and the template having template alignment marks, the method including, reducing a distance between the substrate and the template to cause a spreading of the activating light curable liquid; and varying an overlay placement of the template with respect to the substrate such that the template alignment marks are substantially aligned with the substrate alignment marks before the spreading causes the activating light curable liquid to cover an area between the substrate alignment marks and the template alignment marks.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: March 6, 2007
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Byung-Jin Choi, Matthew E. Colburn, Todd C. Bailey
  • Patent number: 7180593
    Abstract: The present invention provides an overlay mark for aligning different layers on a semiconductor wafer. The overlay mark comprises a bar-in-bar mark and two bar sets on the semiconductor wafer. The bar-in-bar mark comprises an inner bar mark positioned in one of the pre-layer and an outer bar mark positioned in the other pre-layer. The two bar sets are perpendicular to each other, and each of two bar sets comprises two parallel bars. The bars can be connected and the lengths of the bars can be the same or different.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: February 20, 2007
    Assignee: Macronix International Co., Ltd.
    Inventor: Yen Yu Lin
  • Patent number: 7179571
    Abstract: An optical apparatus used for the efficient characterization of photoresist material includes at least one grating interferometer having at least two gratings that together define an optical recombination plane. An optical stop blocks any zeroth order beam from propagating through the apparatus. A reticle positioned at the recombination plane has at least one fiducial marking therein. A lithographic imaging optical tool is positioned so that its input optical plane is substantially coincident with the optical recombination plane and its output imaging plane is substantially coincident with photoresist on a wafer. The apparatus writes in the photoresist latent, sinusoidal grating patterns, preferably of different spatial frequencies, as well as at least one fiducial mark whose pattern is determined by the marking in the reticle. After the photoresist is developed, its intrinsic spatial resolution may be determined by automated means.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: February 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: William Dinan Hinsberg, III, John Allen Hoffnagle, Frances Anne Houle, Martha Inez Sanchez
  • Patent number: 7175951
    Abstract: A method for in-situ overlay accuracy checking using a first mask having a first pattern and a second mask having a second pattern to expose a layer of photosensitive material formed on a wafer. The first pattern and the second pattern are exposed in the layer of photosensitive material using the first mask, the second mask, and a photolithographic alignment and exposure system. The layer of photosensitive material is then developed and the relative position between the first pattern and the second pattern is analyzed.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: February 13, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Hong-Shing Chou
  • Patent number: 7171901
    Abstract: Methods and apparatus are provided for improving the accuracy and streamlining the process of preparing an imaged flexographic printing sleeve. Seam layout details are determined by a controller and transferred to an automated cutting device to cut flexographic precursor sections. The controller can also control a printing device to print indicia on a sleeve substrate for use in aligning the cut precursor sections. The controller can also control a mounting device for the mounting of the cut precursor sections. An imaging engine for imaging a flexographic printing sleeve is equipped with an edge detection system for determining the location of seams between abutting precursor sections.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: February 6, 2007
    Assignee: Kodak Graphic Communications Canada Company
    Inventor: Aldo Salvestro
  • Patent number: 7170604
    Abstract: An overlay target includes two pairs of test patterns used to measure overlay in x and y directions, respectively. Each test pattern includes upper and lower grating layers. A single pitch (periodic spacing) is used for all gratings. Within each test pattern, the upper and lower grating layers are laterally offset from each other to define an offset bias. Each pair of test patterns has offset biases that differ by the grating pitch/4. This has the important result that the combined optical response of the test patterns is sensitive to overlay for all values of overlay. An algorithm obtains overlay and other physical properties of the two or more test patterns from their optical responses in one combined regression operation.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: January 30, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Abdurrahman Sezginer, Kenneth Johnson
  • Patent number: 7170603
    Abstract: An exposure apparatus includes an image sensing section and image sensing control section for measuring the average position of a mark formed on a wafer during a predetermined observation period before a stage completely stops, an interferometer for measuring any deviation of the stage during the observation period, a stage deviation storage section for storing the measurement result by the interferometer in a memory and calculating the average deviation of the stage on the basis of the measurement result, and a shift amount calculation section for calculating the actual position of the mark, while the stage is at rest, on the basis of the average position of the mark and the average deviation of the stage.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: January 30, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shoshi Katayama
  • Patent number: 7166395
    Abstract: A method and system of processing stamps comprising providing a template containing openings, each opening corresponding with an image to be imprinted on a material, whereby the openings are sized to align such material with the images.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: January 23, 2007
    Assignee: M&R Marking Systems, Inc.
    Inventors: Doogong Yip, Steven J. Sculler
  • Patent number: 7164463
    Abstract: An apparatus, system, and method for configuring a dual isolation system lithography tool is described. An isolated base frame is supported by a non-isolated tool structure. A wafer stage component is supported by the isolated base frame. The wafer stage component provides a mount for a semiconductor wafer. A reticle stage component is supported by the isolated base frame. The reticle stage component provides a mount for a reticle. An isolated bridge provides a mount for a projection optics. The isolated bridge is supported by the isolated base frame. Alternatively, an isolated bridge is supported by a non-isolated base frame. A wafer stage component is supported by the non-isolated base frame. A reticle stage component is supported by the non-isolated base frame. An isolated optical relay is supported by the non-isolated base frame. The isolated optical relay includes one or more individually servo controlled framing blades.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: January 16, 2007
    Assignee: ASML Holding N.V.
    Inventors: Daniel N. Galburt, Peter C. Kochersperger
  • Patent number: 7160657
    Abstract: An apparatus and method for manufacturing and using a calibrated registration reference wafer in a semiconductor manufacturing facility. A reference reticle consisting of a 2-dimensional array of standard alignment attributes is exposed several times onto a photoresist coated semiconductor wafer using a photolithographic exposure tool. After the final steps of the lithographic development process the resist patterned wafer is physically etched using standard techniques to create a permanent record of the alignment attribute exposure pattern. The permanently recorded alignment attributes are measured for placement error using a conventional overlay metrology tool. The resulting overlay error data is used to generate a calibration file that contains the positions of the alignment attributes on the reference wafer. The reference wafer and calibration file can be used to determine the wafer stage registration performance for any photolithographic exposure tool.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: January 9, 2007
    Assignee: Litel Instruments
    Inventors: Adlai Smith, Bruce McArthur, Robert Hunter, Jr.
  • Patent number: 7160655
    Abstract: To provide an exposure method and an exposure apparatus, using a complementary divided mask, designed to enable alignment of a complementary divided mask at a high precision over the entire region of a semiconductor wafer. Further, to provide a semiconductor device fabricated by the exposure method and a method of producing a semiconductor device using the exposure method.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: January 9, 2007
    Assignee: Sony Corporation
    Inventors: Shinichiro Noudo, Kumiko Oguni, Hiroyuki Nakano, Hiroki Hane
  • Patent number: 7160654
    Abstract: A method is provided for improving layer to layer overlay of a second layer pattern on a first layer pattern formed in a substrate. A plurality of first reference marks is placed inside a pattern area on a first layer mask which is used to form the first layer pattern. A plurality of second reference marks is placed on a second layer mask which is used to form the second layer pattern and in which one second reference mark is matched with a first reference mark having the same (x,y) coordinates. Reference mark placement in the resulting first and second layer patterns is determined by metrology to determine an x-deviation and a y-deviation for each matched pair of reference marks. A correction algorithm is then used to calculate adjustments in exposure tool settings for improved overlay of the second layer pattern on the first layer pattern in subsequent exposures.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: January 9, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Fei-Gwo Tsai
  • Patent number: 7160656
    Abstract: A two dimensional vernier is provided along with a method of fabrication. The two dimensional vernier has a reference array patterned into a substrate, or a material overlying the substrate. An active array is patterned into photoresist overlying the substrate or the material. Both the reference array and the active array each comprise a two dimensional array of shapes. A difference between a combination of size or spacing of the shapes in each array determines vernier resolution. Vernier range is determined by a combination of vernier resolution and an integer related to a total number of shapes along a given axis. The two dimensional vernier allows an operator to readily measure the misalignment of a pattern to be processed relative to a previous pattern in two dimensions using a microscope. The two dimensional vernier reduces, or eliminates, repositioning of the microscope to determine both x-axis misalignment and y-axis misalignment.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: January 9, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Bruce D. Ulrich
  • Patent number: 7158233
    Abstract: An alignment mark includes a first mark usable for global alignment measurement in the direction of a scribe line, and a second mark usable for pre-alignment measurement in a direction perpendicular to the direction of the scribe line. The first mark is formed by arranging a plurality of strip-shaped X measurement marks whose longitudinal direction is perpendicular to the direction of the scribe line. In the second mark, strip-shaped second measurement marks are arranged at the two ends of the first mark such that the longitudinal direction of the second measurement mark is perpendicular to that of the first measurement mark. The alignment mark can be shared by global alignment and pre-alignment, and applied to a narrow scribe line.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: January 2, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroshi Tanaka
  • Patent number: 7158213
    Abstract: An apparatus, system, and method for configuring a dual isolation system lithography tool is described. An isolated base frame is supported by a non-isolated tool structure. A wafer stage component is supported by the isolated base frame. The wafer stage component provides a mount for a semiconductor wafer. A reticle stage component is supported by the isolated base frame. The reticle stage component provides a mount for a reticle. An isolated bridge provides a mount for a projection optics. The isolated bridge is supported by the isolated base frame. Alternatively, an isolated bridge is supported by a non-isolated base frame. A wafer stage component is supported by the non-isolated base frame. A reticle stage component is supported by the non-isolated base frame. An isolated optical relay is supported by the non-isolated base frame. The isolated optical relay includes one or more individually servo controlled framing blades.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: January 2, 2007
    Assignee: ASML Holding N.V.
    Inventors: Daniel N. Galburt, Peter C. Kochersperger
  • Patent number: 7154105
    Abstract: Provided is a method of exposing using an electron beam. The provided method of exposing using the electron beam includes defining main fields on an exposure area of an electron beam exposure target and defining a plurality of sub-fields on the main fields, selecting a main field to be exposed, selecting at least one sub-field of the selected main field, exposing the selected sub-field by using the electron beam, and selecting at least one of the other sub-field, which is not adjacent to the previously selected sub-field and not exposed yet, and exposing the sub-field by using the electron beam.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: December 26, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hae-sung Kim, Myung-bok Lee, Jin-seung Sohn, Mee-suk Jung, Eun-hyoung Cho
  • Patent number: 7150948
    Abstract: A photomask includes a main mask pattern having first chip patterns and having a first size corresponding to a maximum exposure area of a projection exposure apparatus. The mask further includes a sub-mask pattern having second chip patterns different from the first chip patterns, having a second size smaller than the first size, and arranged adjacently to the main mask pattern.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: December 19, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Tuguto Maruko
  • Patent number: 7132201
    Abstract: A transparent amorphous carbon layer is formed. The transparent amorphous carbon layer has a low absorption coefficient such that the amorphous carbon is transparent in visible light. The transparent amorphous carbon layer may be used in semiconductor devices for different purposes. The transparent amorphous carbon layer may be included in a final structure in semiconductor devices. The transparent amorphous carbon layer may also be used as a mask in an etching process during fabrication of semiconductor devices.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: November 7, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Zhiping Yin, Weimin Li
  • Patent number: 7129024
    Abstract: An electron beam lithography method includes extending the widths of a plurality of stripes which divide a region where an electron beam exposure is to be performed, so that the boundaries of the stripes overlap adjacent stripes at each boundary, and sequentially exposing each of the stripes to an electron beam.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: October 31, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Won-Tai Ki
  • Patent number: 7126689
    Abstract: An exposure apparatus for exposing a substrate with an exposure light beam passing through a mask comprises a movable stage for moving the substrate, a stage chamber for accommodating the movable stage, a transport system for transporting the substrate into the stage chamber, and a first alignment system for performing positional adjustment for the substrate with respect to the movable stage in the stage chamber. The position of an exposure objective delivered from the transport system into the stage chamber can be subjected to positional adjustment by using the first alignment system. The stage chamber and the movable stage can be assembled to a frame of the exposure apparatus in accordance with the module system. The exposure apparatus includes a second alignment system for performing positional adjustment for the substrate installed on the movable stage at an exposure position.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: October 24, 2006
    Assignee: Nikon Corporation
    Inventor: Kenji Nishi
  • Patent number: 7108946
    Abstract: Methods of fabricating an integrated circuit on a wafer using dual mask exposure lithography is disclosed. Improved mask image alignment between a first mask image and a second mask image of a dual mask exposure technique can be achieved by aligning the second mask image to a latent image created by an exposure using the first mask image.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: September 19, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Todd P. Lukanc, Sarah N. McGowan, Bhanwar Singh, Joerg Reiss
  • Patent number: 7099011
    Abstract: A projection lens distortion error map is created using overlay targets and a special numerical algorithm. A reticle including an array of overlay targets is exposed several times onto a photoresist coated silicon wafer using a photolithographic stepper. After exposure, the overlay targets are measured for placement error. The resulting overlay error data is then supplied to a software program that generates a lens distortion error map for the photolithographic projection system.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: August 29, 2006
    Assignee: Litel Instruments
    Inventors: Bruce McArthur, Adlai Smith, Robert Hunter, Jr.
  • Patent number: 7099010
    Abstract: A two-dimensional periodic pattern that is symmetrical with respect to a first and a second direction allows the determination of an overlay accuracy that is obtained during the fabrication of the two-dimensional structure. Due to the symmetry of the structure, the overlay accuracy in the first direction may be determined on the basis of substantially the same reference data as used for the determination of the overlay accuracy of the second direction so that establishing libraries is simplified. Moreover, depending on the capability of the metrology tool, the overlay accuracy in both directions may be obtained simultaneously.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: August 29, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Bernd Schulz
  • Patent number: 7087352
    Abstract: Non-imaging measurement is made of misalignment of lithographic exposures by illuminating periodic features of a mark formed by two lithographic exposures with broadband light and detecting an interference pattern at different wavelengths using a specular spectroscopic scatterometer including a wavelength dispersive detector. Misalignment can be discriminated by inspection of a spectral response curve and by comparison with stored spectral response curves that may be empirical data or derived by simulation. Determination of best fit to a stored spectral curve, preferably using an optimization technique can be used to quantify the detected misalignment. Such a measurement may be made on-line or in-line in a short time while avoiding tool induced shift, contact with the mark or use of a tool requiring high vacuum.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: August 8, 2006
    Assignee: Nikon Corporation
    Inventors: Bernard Fay, Arun A. Aiver
  • Patent number: 7083882
    Abstract: A coating method for a color filter, including the steps of: coating a first photoresist layer on a substrate; forming at least a aligning pattern and a first color film pattern on the first photoresist layer by exposure and development; coating a first dye on the aligning pattern and the first color film pattern; stripping the first photoresist layer; coating a second photoresist layer on the substrate, wherein the aligning pattern and the first color film pattern are formed on the substrate; aligning position by using the aligning pattern of the substrate; forming a second color film pattern on the second photoresist layer by exposure and development; coating a second dye on the second color film pattern; and stripping the second photoresist layer. The invention also discloses an aligning-assembling method for a color wheel, which includes the color filter.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: August 1, 2006
    Assignee: Prodisc Technology Inc.
    Inventors: Chih-Neng Chang, Jui Hung Yen, Wen Hu Wang, Ke-Shu Chin, An-Hwa Yu
  • Patent number: 7070891
    Abstract: Provided are a photomask, a method for manufacturing the photomask and a method for measuring optical characteristics of a wafer exposure system, the measuring method using the photomask during manufacture. The photomask includes a substrate and a measuring pattern including a light opaque region pattern formed on the substrate and a plurality of light transmitting region patterns that are formed in regions divided by the light opaque region pattern and provoke phase shifts to provide phase differences to light transmitted through light transmitting regions. Precise measurements of the degree of a focus and lens aberrations of an exposure system using the photomask are obtained.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: July 4, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-moon Jeong, Seong-hyuck Kim, Seong-woon Choi
  • Patent number: 7065737
    Abstract: A system facilitating measurement and correction of overlay between multiple layers of a wafer is disclosed. The system comprises an overlay target that represents overlay between three or more layers of a wafer and a measurement component that determines overlay error existent in the overlay target, thereby determining overlay error between the three or more layers of the wafer. A control component can be provided to correct overlay error between adjacent and non-adjacent layers, wherein the correction is based at least in part on measurements obtained by the measurement component.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: June 20, 2006
    Assignee: Advanced Micro Devices, Inc
    Inventors: Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh
  • Patent number: 7063925
    Abstract: The invention relates to a photographic article comprising a base material carrying at least one layer comprising a photographic image formed by combination of dyes formed from couplers wherein areas of said photo image are colored without dyes formed by couplers.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: June 20, 2006
    Assignee: Eastman Kodak Company
    Inventors: William T. Rochford, Robert P. Bourdelais, Mridula Nair
  • Patent number: 7061615
    Abstract: An overlay target for spectroscopic measurement includes at least two diffraction gratings, one grating overlying the other. The diffraction gratings may include an asymmetry relative to each other in order to improve resolution of the presence as well as the direction of any mis-registration. For example, the asymmetry between the two diffraction gratings may be a phase offset, a difference in pitch, line width, etc. The overlay target may be spectroscopically measuring, for example, using an optical model and a best fit analysis. Moreover, the overlay target may be optimized by modeling the overlay target and adjusting the variable parameters and calculating the sensitivity of the overlay target to changes in variable parameters.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: June 13, 2006
    Assignee: Nanometrics Incorporated
    Inventor: Roger R. Lowe-Webb
  • Patent number: 7060402
    Abstract: The present invention includes a method of orientating a template with respect to a substrate spaced from the template, the method including, rotating the template about a first and a second axis to orientate the template with respect to the substrate and maintain the orientation in response to a force being exerted upon the template.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: June 13, 2006
    Assignee: Board of Regents, The University of Texas System
    Inventors: Byung Jin Choi, Sidlgata V. Sreenivasan, Stephen C. Johnson
  • Patent number: 7060403
    Abstract: A mask structure and method of quantitatively measuring pellicle degradation in production photomasks by measuring overlay in test structures on the mask. A structure is located in a high transmission region close to a transition region between a low transmission and a high transmission region of the mask such that pellicle degradation impacts the printing of the object. A second structure is located in low transmission region such that the printing of the second structure overlaps the first and provides a measure of pellicle degradation.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: June 13, 2006
    Assignee: International Business Machines Corporation
    Inventor: Michael Straight Hibbs
  • Patent number: 7057715
    Abstract: Test patterns and a method for evaluating and adjusting the resolution of an electron beam lithography tool. The test patterns include multiple feature patterns that are repeated throughout the test pattern. Each feature pattern can be interleaved with horizontal and/or vertical line patterns that facilitate cleaving of a test substrate for three dimensional analysis of the developed image. Further, each feature pattern can comprise multiple sub-patterns. Each sub-pattern includes at least one feature having a size that varies from less than a nominal resolution limit of the lithography tool to greater than the nominal resolution limit. The lithography tool resolution can be evaluated by exposing a test pattern on a resist coated substrate, and analyzing the developed image.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: June 6, 2006
    Assignee: International Business Machines Corporation
    Inventor: Christopher F. Robinson
  • Patent number: 7056631
    Abstract: An exposure system with group compensation. The exposure system includes a lot classification database, a compensation unit and a first exposure device. The lot classification database records a group classification of at least one lot wafer. The compensation unit obtains the group classification of the lot wafer from the lot classification database, retrieves a group compensation value according to the group classification, and compensates overlay parameters according to the group compensation value. The first exposure device performs a back-end process including overlay and exposure processes on the lot wafer using the compensated overlay parameters.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: June 6, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Jung-Chih Kuo, Jen-Ho Chen
  • Patent number: 7054007
    Abstract: There is a method for manufacturing wafers. In an example embodiment, the method employs a stepper with a reticle, lens, and stage movement parameters that comprise providing a set of intentionally-misaligned calibration wafers with predetermined input corrections, the input corrections accounting for linearity of response and interactions between the reticle, lens and stage movement parameters of the stepper. The stepper is calibrated by using the predetermined input corrections from the set of intentionally misaligned calibration wafers. Using the calibrated stepper, aligned patterns on the wafers are printed.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: May 30, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Pierre Leroux, David H. Ziger
  • Patent number: 7053371
    Abstract: A scanning electron microscope which efficiently makes measurements for plural measurement items at a time and allows easy entry, confirmation and revision of auto measurement parameters. Parameters for creation of a line profile from an image captured by the scanning electron microscope are entered as auto measurement parameters (AMP) to be used as common conditions for all measurement items. Also, plural combinations of edge detection methods and measurement calculation methods are entered as auto measurement parameters to make measurements for plural items.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: May 30, 2006
    Assignees: Hitachi High-Technologies Corporation, Hitachi Science Systems, Ltd.
    Inventors: Yuuki Ojima, Katsuhiro Sasada, Kazuhiro Ueda, Tsuyoshi Morimoto
  • Patent number: 7052986
    Abstract: A method for manufacturing a semiconductor apparatus device includes a plurality of layers on a semiconductor substrate. The method includes the steps of dividing a pattern of at least a layer into a plurality of sub-patterns, and joining the divided sub-patterns to perform patterning. The layer including wiring substantially affects operation of the semiconductor device depending on a positional relationship to any other wiring, the patterning is performed by one-shot exposure using a single mask, and only as to the layer including the wiring substantially affecting the operation of the semiconductor device depending on the positional relationship to any other wiring, the patterning is performed by one-shot exposure, and as to all of the other layers, the patterning is performed by division exposure.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: May 30, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yasuo Yamazaki
  • Patent number: 7046408
    Abstract: Exemplary embodiments of the present invention provide a method of hologram exposure that is capable of making accurate alignment. A method of exposure according to one exemplary aspect of the present invention includes providing a mask for hologram exposure M2 including first alignment marks A1 through A4 that is readable with an alignment optical system 40 and a hologram exposure area D2 to which a hologram is recorded by hologram exposure so as to form a desirable coherent pattern and second alignment marks AL1 through AL4 on a substrate 10.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: May 16, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Patent number: 7046332
    Abstract: An exposure system with group compensation. The exposure system includes a lot classification database, a compensation unit and a first exposure device. The lot classification database records a group classification of at least one lot wafer. The compensation unit obtains the group classification of the lot wafer from the lot classification database, retrieves a group compensation value according to the group classification, and compensates overlay parameters according to the group compensation value. The first exposure device performs a back-end process including overlay and exposure processes on the lot wafer using the compensated overlay parameters.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: May 16, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Jung-Chih Kuo, Jen-Ho Chen
  • Patent number: 7045254
    Abstract: A mask, and in particular a phase shift product mask, utilizes predetermined defects being produced during the fabrication thereof in the so-called “second layer” process. The defects are identified by markers in their direct vicinity. The markers are quadrangular and indicate, by virtue of their number in combination with their configuration, information about the respectively assigned defect, such as, for example, defect type, defect size, etc.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: May 16, 2006
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Dettmann, Gunter Antesberger, Jan Heumann, Mario Hennig
  • Patent number: 7041418
    Abstract: A method of measuring a gap between a mask and a substrate by providing a mask and a substrate facing each other. The mask includes an array of patterns, and a at least one window disposed between two of the patterns. Each of the patterns corresponds to a display device. The method also includes projecting an incident laser beam onto the substrate through the window of the mask and determining a gap between the mask and the substrate in a middle region of the substrate in response to first and second reflected beams. The first reflected beam is generated by the reflection of the incident laser beam by the mask, and the second reflected beam is generated by the reflection of the incident laser beam by the substrate. Determining the gap between the mask and the substrate in the middle region allows for the correction of any undesirable deflection of the mask.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: May 9, 2006
    Assignee: NEC Plasma Display Corporation
    Inventor: Takeshi Shimizu
  • Patent number: 7027156
    Abstract: Described are methods for patterning a substrate by imprint lithography. Imprint lithography is a process in which a liquid is dispensed onto a substrate. A template is brought into contact with the liquid and the liquid is cured. The cured liquid includes an imprint of any patterns formed in the template. Alignment of the template with a previously formed layer on a substrate, in one embodiment, is accomplished by using scatterometry.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: April 11, 2006
    Assignee: Molecular Imprints, Inc.
    Inventors: Michael P. C. Watts, Ian McMackin
  • Patent number: 7018753
    Abstract: A method of fabricating integrated circuits according to a first design by imaging a first layer on a substrate using a first mask having a block of first patterns in common with a second design, but without any other patterns of the first or second designs and imaging a second layer on the substrate using a second mask having a block of second patterns unique to the first design and at least one third layer pattern. The block of first patterns is repeatedly exposed in a first grid and the block of second patterns is repeatedly exposed in a second grid, each without overlap in the corresponding layer. The grids are aligned such that the integrated circuits and test structures in scribe lines between the integrated circuits are properly formed on the substrate. The first patterns can be for large fields and the second patterns can be for small fields.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: March 28, 2006
    Assignee: LSI Logic Corporation
    Inventors: David J. Sturtevant, Duane B. Barber, Ann I. Kang
  • Patent number: RE39083
    Abstract: Constant speed drive of a reticle and a wafer in a relative scanning direction and positioning of the reticle and the wafer are simultaneously performed with high precision by a slit scanning exposure scheme. A reticle side scanning stage for scanning a reticle relative to a slit-like illumination area in the relative scanning direction is placed on a reticle side base. A reticle side fine adjustment stage for moving and rotating the reticle within a two-dimensional plane is placed on the reticle side scanning stage. The reticle is placed on the reticle side fine adjustment stage. Constant speed drive and positioning of the reticle and a wafer are performed by independently controlling the reticle side scanning stage and the reticle side fine adjustment stage.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: May 2, 2006
    Assignee: Nikon Corporation
    Inventor: Kenji Nishi