Abstract: A method for generating a plurality of reticle layouts is provided. A feature layout with a feature layout pitch is received. A plurality of reticle layouts is generated from the feature layout where each reticle layout of the plurality of reticle layouts has a reticle layout pitch and where each reticle layout pitch is at least twice the feature layout pitch.

Abstract: Multi-exposure lithography systems are provided for improved overlay accuracy. In one aspect, a method for multi-exposure lithography operates by determining overlay parameters corresponding to each of a plurality of sub-layouts, inputting the overlay parameters into an exposure system, exposing each sub-layout to photoresist on a wafer by using the exposure system, wherein prior to the exposure process for a given sub-layout, a correction process is performed for the sub-layout using a corresponding overlay parameter to correct an overlay of the sub-layout, and developing the exposed photoresist after exposing all of the sub-layouts.

Abstract: A complementary mask has a plurality of pattern forming regions 34a, 34 having arranged on them complementary patterns 26, 28 obtained by dividing first circuit patterns into complementary patterns 26, 28 complementary with each other and formed by openings. The complementary patterns 26, 28 are arranged in the pattern forming regions 34a, 34b so that pattern densities of the pattern forming regions 34a, 34b become substantially the same.

Abstract: A system and method use a substrate with a pattern of individual, indiscrete alignment marks, i.e., the marks are separate and distinct from each other, and each mark is not divided into component parts. The pattern of marks is distributed over an area of the substrate, and the method also comprises the steps of providing a beam of radiation using an illumination system and an array of individually controllable elements to impart the beam with a pattern in its cross-section, providing a projection system to project the patterned beam onto the substrate, and providing a movement system to effect relative movement between the substrate and the projection system.

Abstract: To provide an exposure apparatus and an exposure method able to correct an image-placement error during an exposure which is unable to decrease only by correcting electron beam description data of a mask pattern, and a semiconductor device manufacturing method used the same, wherein an image placement R2 of a mask is measured at an inversion posture against an exposure posture (ST7), the measured image placement R2 is corrected with considering a pattern displacement caused by gravity at the exposure posture and a first correction data ?1 is prepared based on a difference of the corrected image placement and a designed data (ST10), and an exposure is performed by deflecting charged particle beam to correct a position of a pattern to be exposed to a subject based on the first correction data ?1 (ST13).

Abstract: In repeated processes (steps 201 to 213) of lot processing, an analytical apparatus detects abnormality of overlay, that is, deterioration of overlay accuracy in step 211 and optimizes an apparatus parameter of an exposure apparatus so that the abnormality is solved (so that the overlay accuracy is improved), and then the optimization result is promptly reflected in the exposure apparatus and a measurement/inspection instrument. Since such optimization is performed without stopping the lot processing, the productivity of devices is not lowered.

Abstract: A photomask with photoresist test patterns and pattern inspection method using four test patterns on the photomask to perform the exposure on the first photoresist layer in order to adjust the photomask. The present invention prevents misalignment of the first photomask. The information associated with the misalignment is provided to the process engineer based on the location of the test patterns.

Abstract: The invention can provide a method of processing a wafer using segmented multi-dimensional targets that can be used in Double-Patterning (D-P) procedures.

Abstract: A method for fabricating mechanical structures from bonding substrates. The method includes providing a bonded substrate structure, which includes a first substrate having a first thickness of silicon material and a first face. The bonded substrate also includes a second substrate having a second thickness and a second face. At least the first substrate or at least the second substrate (or both) has an alignment mark comprising a front-size zero mark within a portion of either the first thickness or the second thickness. The method includes applying a layer of photomasking material overlying a first backside surface of the first substrate. The method includes illuminating electromagnetic radiation using a coherent light source through the layer of photoresist material and through a portion of the first thickness. The method includes detecting an indication of the alignment mark using a signal associated with a portion of the electromagnetic radiation from a second backside of the second substrate.

Abstract: Disclosed herein is a fabrication method for a semiconductor device, including a lithography step of connecting a plurality of mask patterns to each other to form a pattern image of an area greater than the size of the mask patterns. The lithography step includes the steps of: assuring an overlapping exposure region to be exposed in an overlapping relationship by both of two mask patterns to be connected to each other, carrying out exposure transfer of the pattern portions of the two mask patterns to the overlapping exposure region to form a first measurement mark and a second measurement mark in the overlapping exposure region, and carrying out positional displacement measurement of pattern connection by the two mask patterns based on a manner of combination of main marks and sub marks of the measurement marks formed in the overlapping exposure region.

Abstract: A substrate bonding system has a first and a second substrate table for holding a first substrate and a second substrate, respectively, and a controller. The first substrate includes a first device having first contact pads and the second substrate a second device having second contact pads. The wafer bonding system is arranged to bond the first and second device in such a way that a circuit may be formed by the first and second device. The first and second substrate tables each include a position sensor arranged to measure an optical signal generated on an alignment marker of the first and second substrate, respectively. The first and second substrate tables include a first and second actuator respectively that is arranged to alter a position and orientation of the respective substrate table.

Abstract: An exposing apparatus for irradiating desired spots on a substrate to be exposed relatively moving with respect to two or more light sources arranged along the direction of the relative movement to form a desired exposure pattern using the light sources comprises a control means for controlling the turning-on of only specific light sources out of the two or more light sources at a specific timing.

Abstract: A method for determining rotational error portion of total misalignment error in a stepper. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer, having a first pattern and an error-free fine alignment target, in the stepper. In another step, the wafer is aligned in the stepper using the error-free fine alignment target. Then a second pattern is created on the wafer overlaying said first pattern. In another step, the rotational error portion of the total misalignment error is determined by measuring the circumferential misalignment between the first pattern and the second pattern.

Abstract: A recticle pattern applied to a mix-and-match lithography process is described. The recticle has a transparent region and a non-transparent region. The transparent region includes a device region and a scribe line region. The recticle pattern includes a plurality of device patterns, a portion of a first and a second set of alignment measure figures, and a set of overlay measure figures. The first and the second sets of the alignment measure figures are disposed on the scribe line region and the non-transparent region. The first and the second sets of the alignment measure figures respectively self-align to produce two sets of composite alignment measure figures after the exposure process. A set of overlay measure figures includes four rectangular boxes respectively disposed in the four areas formed in the corners of where the non-transparent region and the scribe line region meet to correct the overlay error caused by recticle rotation.

Abstract: A method for reducing an overlay error of structures of a layer to be patterned relative to those of a reference layer includes formation of standard measurement marks assigned to one another in the two layers for determining an overlay error and for setting up further measurement marks for determining an additional optical imaging error of the projection system at least in the current layer. The further measurement marks have a geometry adapted to the geometry of selected structures of the circuit patterns to be transferred by projection from masks onto semiconductor substrates. An imaging error affects circuit structures and further measurement marks in the same way. An alignment correction for a subsequent exposure can be calculated from the measured positional deviations between the two standard measurement marks and between the standard measurement mark and the further measurement mark of the layer currently to be patterned.

Abstract: In a drawing method for drawing an image on a substrate by relatively moving a drawing head that forms, based on input drawing-point data, drawing points on the substrate with respect to the substrate and by sequentially forming the drawing points on the substrate by the drawing head based on the movement of the drawing head, a relative positional deviation between the substrate and the drawing head during drawing of the image is obtained. Further, formation positions of the drawing points by the drawing head are corrected based on the obtained relative positional deviation.

Abstract: In a method of measuring front to backside alignment error according to one embodiment, a transparent substrate has a plurality of marks on both the front and backside. The relative location of the marks on the front and backside of the substrate is determined to calculate the front to backside alignment error for the whole substrate. In a further embodiment, the substrate is rotated by 180° within the plane of the substrate and the front relative location of the marks is again determined.

Abstract: An imprint lithography apparatus is disclosed that has a substrate table configured to hold a substrate, a template holder configured to hold an imprint template, the imprint template or the template holder having a template alignment mark configured to be imprinted onto the substrate table or onto a substrate to form an imprinted alignment mark, the imprint template having a functional pattern, and the template alignment mark and the functional pattern having a known spatial relationship, and an alignment sensor configured to determine the location of the imprinted alignment mark.

Abstract: A photomask with alignment marks for the current layer is provided with four edges. The photomask includes main patterns, an inter-scribe lane pattern sited between the main patterns, an extra-scribe lane pattern only sited on the three edges of the photomask, a first set of alignment marks for the current layer on opposite edges having the extra-scribe lane patterns. The photomask further includes a second set of alignment marks for the current layer on opposite edges in which only one has the extra-scribe lane pattern, and they are placed on opposite locations in the inter-scribe lane pattern and the extra-scribe lane pattern, respectively. Moreover, each one of the second set of alignment marks for the current layer include multiple parallel patterns and at least one vertical pattern sited on at least one end of the parallel patterns which are parallel to an extended direction of the opposite edges.

Abstract: A system in which deformation of a substrate wafer is monitored during processing of the wafer is disclosed. In one embodiment, the distortion in the substrate wafer is measured after each exposure and processing operation by comparing the position of a plurality of reference marks to values in a database.

Abstract: Dicing lines extending longitudinally and transversely, and chip areas surrounded by the dicing lines are formed in a resist mask. Critical-dimension patterns are formed in the dicing lines so as to be paired while placing the center line thereof in between. The dimensional measurement of the resist film having these patterns formed therein is made under a CD-SEM, by specifying a measurement-target chip area out of a plurality of chip areas, and by specifying a position of a critical-dimension pattern on the left thereof. Then, the distance of two linear portions configuring the critical-dimension pattern is measured, wherein a portion at a point of measurement on the measurement-target chip area side as viewed from the center line of the dicing line is measured.

Abstract: Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.

Abstract: A method including: providing collinear first and second lines in a mask layer over a substrate, the first line having at one end a first line end and having a first line body adjacent the first line end, and the second line having at one end a second line end and having a second line body adjacent the second line end; measuring line widths of the first line body and the second line body; locating effective line end positions for the first line end based on the line width of the first line body and for the second line end based on the line width of the second line body; and measuring a distance between the effective line end positions, as an effective line end spacing.

Abstract: A lithographic projection apparatus includes an alignment sensor having an electron beam source constructed and arranged to provide an electron beam for impinging on an alignment marker on a substrate, and a back-scattered electron detector constructed and arranged to detect electrons back-scattered from the alignment marker. The alignment sensor is independent of the projection system and projection radiation, and is an off-axis alignment sensor.

Abstract: In an embodiment, an imprint lithography apparatus is disclosed that includes a support structure configured support an imprint template, the imprint template having a neutral plane which substantially bisects the imprint template, and an actuator located in a position such that, when the imprint template is supported by the support structure, the actuator is located between the support structure and a side of the imprint template, wherein the actuator is configured to meet the imprint template at a location which is displaced from the neutral plane of the imprint template.

Abstract: An imprint lithography apparatus including a service station.

Abstract: We have developed a method of registration of a particle beam to internal alignment targets present within photoresist areas which are to be imaged. The method does not affect the photoresist, so the quality of pattern produced in the resist after imaging is not affected. The method used for registration of the particle beam to internal alignment targets also can be used to align a pattern in real time, while the pattern is being created, with the internal alignment targets. The real time alignment during creation of a pattern image in the photoresist can be used to correct for drift, or thermal expansion, or gravitational sag, by way of example.

Abstract: A method for measuring overlay shift is disclosed. An image is acquired of at least one reference element that comprises at least one first pattern element in a first plane and at least one second pattern element in a second plane. An image of a measurement element is likewise acquired. The shift value between the reference element and measurement element is ascertained by comparing the image of the reference element with the image of the measurement element. An output on a user interface indicates whether a predefined tolerance value is being exceeded.

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern.

Abstract: An apparatus and method for manufacturing and using a calibrated registration reference wafer in a semiconductor manufacturing facility where an archive media includes etched alignment attributes. Exposing a pattern of complementary alignment attributes onto the archive media such that the pattern of complementary alignment attributes overlay and interlock with the etched alignment attributes thereby forming completed alignment attributes. Then, measuring offsets in the completed alignment attributes and constructing a calibration file for the archive media based upon the offset measurements and other characteristic data of the exposure tool.

Abstract: A thick pellicle is allowed to have a non-flat shape and its shape is characterized to calculate corrections to be applied in exposures to compensate for the optical effects of the pellicle. The pellicle may be mounted so as to adopt a one-dimensional shape under the influence of gravity to make the compensation easier.

Abstract: A lithographic apparatus is disclosed that has an imprint template or a template holder configured to hold an imprint template, and a substrate table arranged to receive a substrate, the apparatus further comprising walls which together with the substrate table and the imprint template or the template holder, are configured to form an enclosed space which is substantially sealed from a surrounding area.

Abstract: Siloxane epoxy materials employed as redistribution layers in electronic packaging and coatings for imprinting lithography, and methods of fabrication are disclosed.

Abstract: A method for dynamically registering multiple patterned layers on a substrate (3) comprises: depositing a first layer on the substrate; printing a first pattern (20) on the first layer; depositing a second layer on the first pattern; and printing a second pattern on the second layer while dynamically detecting the first pattern to align the second pattern with the first pattern.

Abstract: Methods and apparatus for producing a semiconductor. A production reticle having a pattern that includes circuit features, phase shift target structures and overlay target structures is provided. The pattern is transferred multiple times across a test wafer surface for various focus levels to form a focus matrix. The pattern shift of the phase shift target structures is measured using an overlay metrology tool. The phase difference is calculated for each phase shift target structure, based on the pattern shift and the phase shift target structure focus level to qualify the phase difference of the production reticle. The pattern is transferred onto a production wafer when the phase difference meets desired limits. The pattern shift of the overlay target structures transferred to the production wafer is measured using an overlay metrology tool. The pattern placement error of the overlay target structures is calculated and the pattern placement error is qualified.

Abstract: Non-imaging measurement is made of misalignment of lithographic exposures by illuminating periodic features of a mark formed by two lithographic exposures with broadband light and detecting an interference pattern at different wavelengths using a specular spectroscopic scatterometer including a wavelength dispersive detector. Misalignment can be discriminated by inspection of a spectral response curve and by comparison with stored spectral response curves that may be empirical data or derived by simulation. Determination of best fit to a stored spectral curve, preferably using an optimization technique can be used to quantify the detected misalignment. Such a measurement may be made on-line or in-line in a short time while avoiding tool induced shift, contact with the mark or use of a tool requiring high vacuum.

Abstract: A mask for laser crystallization includes a transmissive portion defining a crystallization pattern and an alignment pattern. The alignment pattern includes a first pattern group having a size corresponding to the crystallization pattern and a second pattern group having a plurality of radial bars surrounding the first pattern group. A shielding portion surrounds the transmissive portion.

Abstract: A method of manufacturing a semiconductor device. The device includes a plurality of layers on a semiconductor substrate. The method includes the steps of dividing a pattern of at least one layer into a plurality of sub-patterns, and joining the divided sub-patterns to perform patterning. A layer that includes wiring substantially affects operation of the semiconductor device depending on a positional relationship to any other wiring. The patterning is performed by one-shot exposure using a single mask.

Abstract: A system and method are used to increase alignment accuracy of feature patterns through detection of alignment patterns on both a surface layer and at least one below surface layers of an object. Visible light is used to detect alignment patterns on the surface layer and infrared light is used to detect patterns one layers below the surface. For example, reflected visible light and transmitted infrared light are co-focused onto detector after impinging on respective alignment patterns. The co-focused light is then used to determine proper alignment of the object for subsequent pattern features. This substantially increases accuracy of alignment of pattern features between layers, as compared to conventional systems.

Abstract: A method for producing an alignment mark is performed such that the alignment mark can be removed from the surface of a substrate without leaving any trace thereof after the alignment mark has been used for alignment. After a first photoresist layer has been formed on a substrate, the first photoresist layer is subjected to patterning, and the alignment mark is thereby formed from the first photoresist layer. In the next step, after a second photoresist layer has been formed so as to cover the alignment mark, the second photoresist layer is subjected to patterning on the basis of the alignment mark. After the surface of the substrate has been subjected to etching by use of a resist mask thus formed, the resist mask and the alignment mark are removed, and the region where the alignment mark has been located is made flat.

Abstract: A photomask with alignment marks for the current layer is provided with four edges. The photomask includes main patterns, an inter-scribe lane pattern sited between the main patterns, an extra-scribe lane pattern only sited on the three edges of the photomask, a first set of alignment marks for the current layer on opposite edges having the extra-scribe lane patterns. The photomask further includes a second set of alignment marks for the current layer on opposite edges in which only one has the extra-scribe lane pattern, and they are placed on opposite locations in the inter-scribe lane pattern and the extra-scribe lane pattern, respectively. Moreover, each one of the second set of alignment marks for the current layer include multiple parallel patterns and at least one vertical pattern sited on at least one end of the parallel patterns which are parallel to an extended direction of the opposite edges.

Abstract: The invention is directed to increasing the number of semiconductor dice obtained from one semiconductor wafer and enhancing the reliability and yield of the semiconductor dice when the semiconductor dice as products and TEG dice are formed on the semiconductor wafer. TEG die pattern regions are respectively placed on the top and bottom placing a plurality of semiconductor die pattern regions regularly arrayed in a longitudinal direction therebetween. The vertical length of each of the TEG die pattern regions is substantially half of the vertical length of the semiconductor die pattern region. With this reticle, two adjacent TEG die patterns respectively formed by two continuous exposure processes form the area of one semiconductor die pattern. In this manner, the area of the TEG die patterns on the semiconductor wafer is reduced and the yield of the semiconductor dice is increased correspondingly.

Abstract: The present invention provides an indexed support substrate. The support substrate comprises at least one set of indexing features that are distinguishable from one another and from the surrounding substrate. The support substrate also comprises a set of useful domains. The indexing features are positioned on the substrate in such a way as to correspond to the useful domains in an identifying fashion.

Abstract: A methodology to improve the through-process model calibration accuracy of a semiconductor manufacturing process using lithographic methods by setting the correct defocus and image plane position in a patterning process model build. Separations of the optical model and the photoresist model are employed by separating out the adverse effects of the exposure tool from the effects of the photoresist. The exposure tool is adjusted to compensate for the errors. The methodology includes a determination of where the simulator best focus location is in comparison to the empirically derived best focus location.

Abstract: The present invention enables the user to measure process line shortening (PLS) on an overlay tool. In an example embodiment (900), to obtain the PLS, the user applies a method to determine the misalignment (MA) of a composite image on a substrate (940a), from the composite image the user may determine the total line (940b) shortening (TLS) and the equipment line (940c) shortening (ELS). The process line shortening (PLS) is determined (940d) as a function of TLS and ELS.

Abstract: A pattern decomposition and optical proximity correction method for double exposure comprises defining second exposure patterns by performing a logical operation on target patterns and first exposure patterns, comparing the first and second exposure patterns with the target patterns by performing a logical operation on the first and second exposure patterns, performing optical proximity correction on the first exposure patterns to form fourth exposure patterns, performing the optical proximity correction on the second exposure patterns to form fifth exposure patterns, and comparing the fourth and fifth exposure patterns with the target patterns by performing a logical operation on the fourth and fifth exposure patterns.

Abstract: A marker structure on a substrate for optical alignment of the substrate includes a plurality of first structural elements and a plurality of second structural elements. In use, the marker structure allows the optical alignment based upon providing at least one light beam directed on the marker structure, detecting light received from the marker structure at a sensor, and determining alignment information from the detected light, the alignment information comprising information relating a position of the substrate to the sensor.

Abstract: An overlay mark formed on a photomask, comprising a first rectangular region, a second rectangular region, a third rectangular region, and a fourth rectangular region, each rectangular region having the same pattern configuration, a longer side of the first rectangular region and a longer side of the third rectangular region being parallel to each other, and a longer side of the second rectangular region and a longer side of the fourth rectangular region being parallel to each other, the longer side of the first rectangular region being perpendicular to the longer side of the second rectangular region; wherein each pattern configuration has at least two different pattern elements allowing other pattern elements be chosen to align when any one of the pattern elements on the substrate was damaged during process.

Abstract: Systems and methods of optical proximity correction are disclosed. A preferred embodiment comprises a method of determining optical proximity correction, which includes providing a design for a lithography mask. The design comprises a layout for a material layer of a semiconductor device. A predicted wafer image producible by the design for the lithography mask is calculated, and an amount of error between a target image and the calculated predicted wafer image is measured over a plurality of pixels of the predicted wafer image. The plurality of pixels comprises a plurality of different sizes.

Abstract: A lithographic method includes patterning a beam of radiation with a patterning device. The patterning device includes at least two image patterning portions and at least two metrology mark patterning portions. The method also includes projecting at least two image portions of the patterned beam of radiation sequentially onto target portions of a substrate such that the projected image portions are substantially adjacent to each other on the substrate and collectively form a composite image on the substrate. The method also includes projecting a metrology mark onto the substrate outside of the area of the composite image at the same time as projecting each of at least two of the image portions, and measuring the alignment of the metrology marks to determine the relative positions of the at least two image portions.