Registration Or Layout Process Other Than Color Proofing Patents (Class 430/22)
  • Patent number: 7651825
    Abstract: A system and method are provided for determining an overlay of a first layer N-1 and a second layer N that are positioned one over the other on a substrate. The first layer includes a first overlay portion. The second layer includes a first complementary overlay portion. The first overlay portion and first complementary overlay portion are arranged to form an overlay mark for determining the overlay of the first and second layers. In the second layer a stitching portion and a complementary stitching portion are formed. The stitching portion and complementary stitching portion are arranged to form a stitching mark for determining a stitching overlay between the second layer and an adjacent second layer, with the adjacent second layer being positioned adjacent to the second layer.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: January 26, 2010
    Assignee: ASML Netherlands B.V.
    Inventor: Franciscus Bernardus Maria Van Bilsen
  • Patent number: 7645546
    Abstract: The invention is directed to a method for determining an overlay correlation set between two successive patterned material layers on a substrate. The method comprises steps of providing a first material layer having a first overlay mark formed therein over the substrate and then using an exposure tool with a first overlay correlation set to form a patterned photoresist layer on the first material layer, wherein the patterned photoresist layer comprises a mark pattern and the mark pattern is located over the first overlay mark for defining a later formed second material layer on the first material layer to be a second overlay mark. Thereafter, a pre-process metrology overlay parameter set between the first overlay mark and the mark pattern is obtained. The first overlay correlation set at the exposure tool is adjusted according to the pre-process metrology overlay parameter set.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: January 12, 2010
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chin-Cheng Yang, Chih-Hao Huang
  • Patent number: 7642020
    Abstract: A methodology to improve the through-process model calibration accuracy of a semiconductor manufacturing process using lithographic methods by setting the correct defocus and image plane position in a patterning process model build. Separations of the optical model and the photoresist model are employed by separating out the adverse effects of the exposure tool from the effects of the photoresist. The exposure tool is adjusted to compensate for the errors. The methodology includes a determination of where the simulator best focus location is in comparison to the empirically derived best focus location.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: January 5, 2010
    Assignee: International Business Machines Corporation
    Inventors: Geng Han, Scott M. Mansfield
  • Patent number: 7638263
    Abstract: An overlay accuracy measurement vernier and a method of forming the same. According to one embodiment, the method of forming the overlay accuracy measurement vernier includes the steps of forming a first vernier pattern in a predetermined region on a semiconductor substrate; etching the semiconductor substrate using the first vernier pattern as a mask, forming a trench of a first depth; forming a second vernier pattern having a width wider than that of the first vernier pattern, the second vernier pattern including the first vernier pattern; performing an etch process using the second vernier pattern as a mask, thus forming a trench of a second depth, which has a step of a predetermined width; stripping the first and second vernier patterns and then forming an insulating film to bury the trench; and, etching the insulating film so that the semiconductor substrate of the vernier region is exposed.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: December 29, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Guee Hwang Sim
  • Publication number: 20090317732
    Abstract: A pattern verification-test method according to an embodiment of the present invention includes: deriving an illumination condition at a verification-test subject position in a photomask surface of a mask pattern as a verification or a test subject based on the verification-test subject position and illumination condition information about a distribution of an illumination condition in a photomask surface of exposure light incident on the mask pattern, performing lithography simulation on the mask pattern based on the derived illumination condition and the mask pattern, and verifying or testing the mask pattern based on a result of the lithography simulation.
    Type: Application
    Filed: June 18, 2009
    Publication date: December 24, 2009
    Inventors: Masamitsu ITOH, Satoshi Tanaka
  • Patent number: 7629093
    Abstract: A method for correcting a critical dimension (CD) of a mask pattern includes forming an light shielding layer over a substrate including a main cell region and a frame region at a periphery of the main cell region; forming an light shielding main pattern in the main cell region and a frame pattern in the frame region by patterning the light shielding layer; measuring a CD of the light shielding main pattern; extracting a CD correction amount from the measured CD; self-aligning a conductive high polymer layer over the frame pattern with electrochemical polymerization; correcting the CD of the main pattern depending on the CD correction amount by performing etch on the main pattern exposed by the conductive high polymer layer; and selectively removing the conductive high polymer layer.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: December 8, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Soo Kyeong Jeong
  • Patent number: 7625679
    Abstract: A significant improvement in the alignment of a particle-beam-generated pattern relative to a pre-existing pattern present on a substrate has been accomplished using optical measurement to register the particle beam to the pre-existing pattern. Use of a position fiducial which can be accurately measured by both an optical microscope and a particle beam axis is used to align a pre-existing pattern with a particle-beam-generated pattern during writing of the particle-beam-generated pattern. Registration of the pre-existing pattern to the fiducial and registration of the particle beam axis to the fiducial periodically during production of the particle-beam-generated pattern continually provides an improvement in the overall alignment of the pattern being created to the pre-existing pattern on the substrate. The improved method of alignment can be used to correct for drift, or thermal expansion, or gravitational sag, by way of example.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: December 1, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey S. Sullivan, Tony Tiecheng Young
  • Patent number: 7611810
    Abstract: A charged beam processing apparatus for processing an object to form structures on the object includes a processing chamber, a multi-charged beam optical system configured to generate a plurality of charged beams, and to converge and to deflect the plurality of charged beams to irradiate the object in the processing chamber with the plurality of charged beams, and a supply port configured to supply a gas into the processing chamber. The multi-charged beam optical system includes (i) a lens array, and (ii) a pattern forming plate configured to select a portion of the lens array to be used to form the structures. The charged beam processing apparatus includes a controller configured to control an exchange of the pattern forming plate in accordance with an arrangement pattern of the structures to be formed on the object.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: November 3, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahiko Okunuki, Haruhito Ono, Shinan Wang, Kenji Tamamori
  • Publication number: 20090263734
    Abstract: In optical maskless lithography, scanning of a single substrate is typically much slower than in conventional lithography. Solutions are described for the adoption of immersion lithography techniques into optical maskless lithography and in particular provides one or more solutions to reduce the amount of time which the immersion liquid is in contact with any given part of the top surface of the substrate during imaging.
    Type: Application
    Filed: June 29, 2009
    Publication date: October 22, 2009
    Applicant: ASML Netherlands B.V.
    Inventors: Johannes Catharinus Hubertus MULKENS, Robert-Han Munnig Schmidt
  • Patent number: 7604907
    Abstract: Mask sets are provided which may be used to define a first pattern region that has a first pitch pattern and a second pattern region that has a second pitch pattern during the fabrication of a semiconductor device. These mask sets may include a first mask that has a first exposure region in which a first halftone pattern defines the first pattern region and a first screen region in which a first shield layer covers the second pattern region. These mask sets may further include a second mask that has a second exposure region in which a second halftone pattern defines the second pattern region and a second screen region in which a second shield layer covers the first pattern region. The second shield layer also extends from the second screen region to cover a portion of the second halftone pattern.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: October 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-Youl Lee, Seok-Hwan Oh, Gi-Sung Yeo, Sang-Gyun Woo, Sook Lee, Joo-On Park, Sung-Gon Jung
  • Patent number: 7598024
    Abstract: A method for alignment mark preservation includes a step of preparing a lower alignment mark structure on a substrate. In one configuration of the invention, the alignment mark structure includes a lower trench. In a further step, a hard mask coating is applied to a substrate that includes the alignment marks. Preferably, the hard mask material is an amorphous carbon material. In a further step, a selected portion of the hard mask located above the lower alignment mark structure is exposed to a dose of radiation. In one aspect of the invention, the surface of regions of the hard mask coating that receive the dose of radiation become elevated with respect to other regions of the hard mask surface. For those elevated regions of the hard mask that are aligned with an underlying alignment mark trench, the elevated regions serve as an alignment mark that preserves the original horizontal position of the underlying alignment mark.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: October 6, 2009
    Assignee: ASML Netherlands B.V.
    Inventors: Sanjaysingh Lalbahadoersing, Sami Musa
  • Patent number: 7599063
    Abstract: A method for checking the alignment accuracy using an overlay mark is provided. The overlay mark includes an inner mark and an outer mark formed on a wafer. The outer mark is formed in a lower layer on the wafer when the lower layer is patterned. The inner mark is formed within the outer mark over the lower layer when a lithography process for defining an upper layer is performed. A measurement process is conducted to obtain a first relation between each of the interior profiles of the outer marks and a second relation between each of the inner marks. Alternatively, a third relation between each of the interior profiles of the outer marks and each of the inner marks is obtained. The X-directional alignment accuracy and y-directional alignment accuracy are computed according to the first and the second relations, or the third relation.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: October 6, 2009
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Patent number: 7598006
    Abstract: A method and apparatus for embedded encoding of overlay data ordering in an in-situ interferometer is described. An in-situ interferometer is encoded, or augmented, with special or missing alignment attributes at desired positions. Exposing a sequence of the encoded in-situ interferometer onto a silicon wafer coated with a suitable recording media. Then measuring the alignment attributes. The encoded overlay data is processed to verify the proper order and physical location of each overlay measurement. The data is collected without increasing the overall number of required overlay measurements required. Collection of overlay data allows for the proper reconstruction of the aberrated wavefront. Non-coupling alignment attribute offsets can also be used to perform similar operations using singular value decomposition and null space operations.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: October 6, 2009
    Assignee: Litel Instruments
    Inventors: Adlai H. Smith, Robert O. Hunter, Jr., Joseph J. Bendik, Jr.
  • Patent number: 7599064
    Abstract: An overlay marker for use with a scatterometer includes two overlying two-dimensional gratings. The two gratings have the same pitch but the upper grating has a lower duty ratio. Cross-talk between X and Y overlay measurements can therefore be avoided. The gratings may be directly overlying or off set so as to be interleaved in one or two directions.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: October 6, 2009
    Assignee: ASML Netherlands B.V.
    Inventors: Everhardus Cornelis Mos, Arie Jeffrey Den Boef, Maurits Van Der Schaar
  • Patent number: 7592108
    Abstract: A near-field exposure method including preparing a photomask for near-field exposure, having a light blocking film provided on a base material constituting a membrane portion and a support member supporting the base material, wherein a first alignment mark for rough alignment is provided on the support member and a second alignment mark for fine alignment is provided on the membrane portion, setting the photomask and an object to be exposed in a near-field exposure apparatus, aligning the photomask and the object using the first alignment mark, flexing the membrane portion to contact with the object and detecting a positional relation between the membrane portion and the object using the second alignment mark, aligning the photomask and the object based on the detected positional relation and flexing the membrane portion to contact with the object, and exposing the object to light from a light source by way of the photomask.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: September 22, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takako Yamaguchi, Ryo Kuroda
  • Patent number: 7592130
    Abstract: An exposure method includes the steps of illuminating a mask that has a contact hole pattern using an illumination light, and projecting, via a projection optical system, the contact hole pattern onto a substrate to be exposed, wherein three lights among diffracted lights from the contact hole pattern interfere with each other, wherein said mask is an attenuated phase shift mask, and wherein said illumination light forms a radial polarization illumination.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: September 22, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Miyoko Kawashima
  • Patent number: 7588869
    Abstract: A divided exposure method for a photolithography process is disclosed, which uses a mask. The mask for an exposer having a left and right light intensity deviation includes a substrate; a first pattern in a middle of the substrate; and second and third patterns on left and right sides of the first pattern, respectively, wherein the first and second patterns compensate for the left and right light intensity deviation of the exposer.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: September 15, 2009
    Assignee: LG Display Co., Ltd.
    Inventors: Su Woong Lee, Sang Yoon Paik
  • Patent number: 7588868
    Abstract: First and second exposures of a mask onto a wafer are performed such that the exposure field of the second exposure partially overlaps the exposure field of the first exposure. A characteristic of a set of features is determined, and a value of a parameter of an optical proximity correction model is determined. An alignment feature can be used to align a measurement tool. In yet another embodiment, pupil intensity distribution of an imaging system is measured by exposing an image field of a radiation detector with a bright feature, positioning the detector at a distance away from the image plane, and exposing the image field of the detector with a bright feature, resulting in a cumulative exposure of the image field of the detector from the two exposures. A characteristic of a spatial pattern in the cumulative exposure of the image field of the detector is then determined.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: September 15, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Franz X. Zach, Abdurrahman Sezginer, Gokhan Percin
  • Publication number: 20090202925
    Abstract: A first photomask 1 has a first transfer pattern to be transferred onto an object and is adapted to be used in combination with a second photomask having a second transfer pattern to be transferred onto the object. Among pattern defects 4 and 5 generated in the first transfer pattern, defect correction is performed only for the pattern defect 4 which is to be transferred onto the object within a region out of an area where a pattern corresponding to the first transfer pattern is not formed on the object as a result of transferring the second transfer pattern.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 13, 2009
    Applicant: HOYA CORPORATION
    Inventor: Hideki Suda
  • Patent number: 7573574
    Abstract: A lithographic apparatus and method comprise an illumination system arranged to provide a radiation beam, a support structure configured to support a product patterning device and a metrology target patterning device. The product patterning device imparts a radiation beam derived from the illumination system with a product pattern in its cross-section representing features of a product device to be formed. The metrology target patterning device imparts the radiation beam with a metrology target pattern in its cross-section representing at least one metrology target. The product patterning device is separate from the metrology target patterning device. A substrate table holds a substrate. A projection system project the radiation patterned by the product patterning device and the metrology target patterning device onto a target portion of the substrate. A metrology target patterning device controller adjusts the metrology target pattern independently of the product pattern.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: August 11, 2009
    Assignee: ASML Netherlands BV
    Inventors: Paul Christiaan Hinnen, Richard Johannes Franciscus Van Haren, Hubertus Johannes Gertrudus Simons
  • Patent number: 7569332
    Abstract: A processing method of a thin-film includes a step of forming a predetermined pattern film or predetermined elements on a substrate or on a film formed in an upstream process, a step of forming a transparent film over the formed predetermined pattern film or predetermined elements, a step of forming a pattern-transferred film having shapes corresponding to shapes of the formed predetermined pattern film or predetermined elements, on the formed transparent film, and a step of forming an opaque film on the pattern-transferred film.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: August 4, 2009
    Assignees: TDK Corporation, SAE Magnetics (H.K.) Ltd.
    Inventors: Mitsuharu Isobe, Hiromichi Umehara, Hirotaka Gomi, Tomohide Yokozawa
  • Patent number: 7566516
    Abstract: A photomask for defining a photoresist layer formed on a wafer having at least an alignment mark region, wherein each alignment mark region has an alignment mark. The photomask comprises a shot region and an alignment mark pattern region. The alignment mark pattern region has a profile equal to the profile of the alignment mark region on the wafer. Further, the alignment mark pattern region comprises a block region, a clean-out region and a dummy pattern region. The position of the block region in the alignment mark pattern region corresponds to the relative position of the alignment mark in the alignment mark region. The clean-out region is adjacent to one side of the block region and the dummy pattern region is adjacent to another side of the block region.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: July 28, 2009
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Patent number: 7564556
    Abstract: The present disclosure provides a method for measuring lens contamination in a lithography apparatus. The method includes imaging an asymmetric pattern utilizing a lens system and measuring an alignment offset of the asymmetric pattern associated with the lens system. A contamination of the lens system is determined by comparing the alignment offset to a reference value.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: July 21, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Keh-Wen Chang, Jun-Ren Chen
  • Patent number: 7560224
    Abstract: According to the present invention, there are provided an ink jet recording head capable of performing high-precision printing and recording and having a high reliability, and a method of manufacturing the head. The ink jet recording head of the present invention has: an element substrate on whose surface an ink discharge energy generating element is formed and which is made of silicon; and a thin and flat inorganic substrate in which an ink discharge port is formed in a portion disposed vertically above the ink discharge energy generating element. Furthermore, the head includes a photosensitive material layer which bonds the element substrate to the inorganic substrate and which is to constitute a wall forming an ink flow path which communicates with the ink discharge port. The inorganic substrate is laminated on the element substrate provided with the photosensitive material layer, and is thereafter provided with the ink discharge port.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: July 14, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tamaki Sato, Ryoji Kanri, Masataka Kato
  • Patent number: 7560196
    Abstract: A mask provided with an alignment mark is presented. That mask includes at least one relatively high reflectance area(s) for reflecting radiation of an alignment beam of radiation, and relatively low reflectance areas for reflecting less radiation of the alignment beam, wherein the high reflectance area(s) is (are) segmented in first and second directions both directions being substantially perpendicular with respect to each other so that the high reflectance areas include predominantly rectangular segments.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: July 14, 2009
    Assignee: ASML Netherlands B.V.
    Inventor: Eugenio Guido Ballarin
  • Publication number: 20090176167
    Abstract: A lithographic apparatus according to one embodiment of the invention includes an alignment system for aligning a substrate or a reticle. The alignment system includes a radiation source configured to illuminate an alignment mark on the substrate or on the reticle, the alignment mark comprising a maximum length sequence or a multi periodic coarse alignment mark. An alignment signal produced from the alignment mark is detected by a detection system. A processor determines an alignment position of the substrate or the reticle based on the alignment signal.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 9, 2009
    Applicant: ASML Netherlands B.V.
    Inventors: Edo Maria HULSEBOS, Franciscus Godefridus Casper Bijnen, Patrick Warnaar
  • Patent number: 7556893
    Abstract: A system and method for fabricating integrated circuits using four fine alignment targets per stepper shot. The four alignment targets are disposed within the scribe line on each side of a four-sided stepper shot. The targets on opposites sides of the region are located in mirror-image positions. For example, in a square or rectangular region, the targets could be at the mid-point of each side, or at each corner. Because the scribe lines for adjoining stepper shots overlap, a target in one shot will overlay a target from a preceding shot. In a positive resist process, for example, the target resulting from the overlay will be reduced in size by an amount corresponding to the amount of rotational error, if any. However, the target will still indicate the center of the stepper shot, thereby compensating for the rotational error with no further measurements.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: July 7, 2009
    Assignee: NXP, B.V.
    Inventor: Pierre Leroux
  • Patent number: 7556898
    Abstract: A target and method for use in polarized light lithography. A preferred embodiment comprises a first structure located on a reference layer, wherein the first structure is visible through a second layer, and a second structure located on the second layer, wherein the second structure is formed from a photomask containing a plurality of sub-structures oriented in a first orientation, wherein a polarized light is used to pattern the second structure onto the second layer, and wherein a polarization of the polarized light is the same as the orientation of the plurality of sub-structures. The position, size, and shape of the second structure is dependent upon a polarity of the polarized light, permitting a single design for an overlay target to be used with different polarities of polarized light.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: July 7, 2009
    Assignee: Infineon Technologies AG
    Inventor: Sajan Marokkey
  • Patent number: 7556900
    Abstract: In photo-lithography, one may assess the effect of flare due to various exposure tools. In an example embodiment, in a photo-lithography process on a photo resist coated substrate, there is a method (600) for determining the effect of flare on line shortening. The method (600) comprises, at a first die position on the substrate and in a first exposure, printing a first mask (610) that includes a flare pattern (110) corresponding to one corner of the first mask (610), and in a second exposure, printing a second mask (620) that includes another flare pattern corresponding to an opposite corner of the second mask. At a second die position on the substrate, a composite mask pattern (630) based on features of the first mask and the second is printed. The printed patterns (640) are developed and measurements (650) are obtained therefrom. The effect of flare (660) is determined as a function of the measurements.
    Type: Grant
    Filed: July 31, 2004
    Date of Patent: July 7, 2009
    Assignee: NXP B.V.
    Inventors: David Ziger, Pierre Leroux
  • Patent number: 7556899
    Abstract: A system for controlling an overlay includes a processing data receiving module receiving a processing data string describing a name of an exposure process for a target layer and an original control set value of overlays between the target layer and underlying layers below the target layer; an inspection data receiving module receiving inspection data strings describing names of inspection processes and inspection values determined by the inspection processes inspecting respective overlays between the target layer and the underlying layers; a data combining module combining the processing data string and each of the inspection data strings using a combining condition table so as to create a correction data table; and a control set value calculation module calculating a corrected control set value based on the inspection values of the correction data table.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: July 7, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Ikeda, Shoichi Harakawa, Takuya Kono
  • Patent number: 7547502
    Abstract: An exposure method includes the step of illuminating a mask having a contact hole pattern that includes a hybrid pattern using an illumination light that forms an effective source that has plural poles, and projecting an image of the mask onto a plate through a projection optics. The hybrid pattern includes a matrix pattern in which plural contact holes are arranged in a matrix shape, and a checker pattern in which plural contact holes are arranged in a checker shape. Three or four diffracted lights from the contact hole pattern interfere with each other.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: June 16, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Miyoko Kawashima
  • Patent number: 7541120
    Abstract: After forming a resist film on a Si substrate, a circuit pattern for a semiconductor integrated circuit, a first L-shaped length measuring pattern and a cross-shaped monitor pattern for alignment are formed on the resist film. Next, based on these patterns, the Si substrate is patterned. Thereafter, a polysilicon film is formed above the Si substrate. Subsequently, a resist film is formed on the polysilicon film. Next, a circuit pattern for a semiconductor integrated circuit, a second L-shaped length measuring pattern and a cross-shaped monitor pattern for alignment are formed on the resist film. At this time, the second L-shaped length measuring pattern is made to face in a direction in which the first L-shaped length measuring pattern is rotated 180 degrees in plane view. By patterning the polysilicon film with these patterns as a mask, a gate electrode is formed.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: June 2, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Masanori Terahara
  • Patent number: 7538344
    Abstract: The present invention provides photolithographic device and method for photolithography process window. The photolithography device comprises a substrate; and a pattern layer having radiant energy transparent portions and radiant energy blocking portions, where the pattern layer has features with a varying overlay. The overlay tolerance is determined by varying the misalignment the features of the pattern. The photolithography device is a reticle. The method for determining an optimum photolithography process window comprises exposing a portion of a wafer to a pattern produced by a reticle, the pattern having a varying overlay that produces multiple photolithography conditions, wherein each photolithography condition has an overlay tolerance; and stepping the reticle across a remaining portion of the wafer, where each step exposes an other region of the wafer to the pattern producing multiple photolithography conditions.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: May 26, 2009
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Mellinger, Timothy C. Milmore, Matthew C. Nicholls
  • Patent number: 7535549
    Abstract: The present invention provides a method for determining the forces to be applied to a substrate in order to deform the same and correct for overlay misalignment.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: May 19, 2009
    Assignee: Board of Regents, University of Texas System
    Inventors: Anshuman Cherala, Sidlgata V. Sreenivasan, Kranthimitra Adusumilli
  • Patent number: 7524595
    Abstract: A method for forming an anti-reflection coating (ARC) with no hole over an overlay mark is described, which applies a fluid material of the ARC onto a substrate and then conducts at least two curing steps to convert the fluid material into the ARC. Such a bottom anti-reflection coating with no hole over the overlay mark can improve accuracy of the overlay measurement of lithography, thereby improving the alignment accuracy of the lithography process.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: April 28, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Kuang Lin, Huan-Hsin Yeh, Chung-An Chen
  • Patent number: 7521697
    Abstract: A method for fabricating a semiconductor device and an equipment for fabricating the semiconductor device are described. According to the method and the equipment, a semiconductor substrate is irradiated with a particle beam through an opening formed in a thin film portion of a stencil mask having the thin film portion and a supporting portion supporting the thin film portion. The method and the equipment are controlled so that the supporting portion of the stencil mask can be irradiated with the fringe of the particle beam. As a result, the method and the equipment provide suppressing deterioration such as deformation or breakage of the stencil mask.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: April 21, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Shibata, Kyoichi Suguro
  • Patent number: 7508515
    Abstract: A system and method for fabricating an electrical circuit in which a digital control image (46) is generated by non-uniformly modifying (44) a representation of an electrical circuit (40), such that an electrical circuit pattern (72) recorded on a substrate (12) using the digital control image (46) precisely fits an already formed electrical circuit portion (62).
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: March 24, 2009
    Assignee: Orbotech Ltd
    Inventors: Golan Hanina, Hanan Gino, Steffen Ruecker, Ido Ben-Tov
  • Patent number: 7508051
    Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided and two control module fields (A1, A2, B1, B2, C1, D1, D2, E1, E2, F1) are assigned to each exposure field (2), each of which control module fields extends parallel to a first direction (X) and contains at least one optical control module (OCM-A1, OCM-A2, OCM-BI, OCM-B2, OCM-C1, OCM-D1, OCM-D2, OCM-E1, OCME2, OCM-F1), wherein a first control module field (OCM-A1, OCM-B1, OCM-C1, OCMD1, OCM-E1, OCM-F1) of each exposure field (2) is located between a first edge (R1, S1, T1, U1, V1, Z1) and a row of lattice fields (3) of the exposure field (2) in question and a second control module field (OCM-A2, OCM-B2, OCM-D2, OCM-E2) is located between two rows of lattice fields (3) of the exposure field (2) in question, which are arranged adjacent to a second edge (R2, S1, U2, V2), and wherein both the first contr
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: March 24, 2009
    Assignee: NXP B.V.
    Inventor: Heimo Scheucher
  • Patent number: 7501214
    Abstract: A semiconductor device fabrication method includes preparing a substrate having a first circuit pattern of a semiconductor device; providing a mask with at least part of second circuit pattern of the semiconductor device; collimating incident direction of particles; changing at least one of the a substrate angle between a vertical axis of the substrate and the incident direction of the particles and a mask angle between a vertical axis of the mask and the incident direction so that the second circuit pattern on the mask can be aligned to the first circuit pattern on the substrate with a design margin; and selectively irradiating the particles to the substrate using the mask.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: March 10, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Shibata
  • Patent number: 7501215
    Abstract: The present invention relates to a device manufacturing method wherein a plurality of front side marks are manufactured on the front side of the substrate. These marks are used to locally align the substrate when exposing. After certain processing steps, the positions of the front side marks are measured and compared with respect to their original positions. The measured position changes of the front side marks, i.e. their behaviour, can then be analyzed. The original positions and actual positions are defined with respect to a nominal grid which is defined using global alignment marks which are positioned at the back side of the substrate. Because the global alignment marks are positioned at the back side, they are not affected by any processing step.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: March 10, 2009
    Assignee: ASML Netherlands B.V.
    Inventors: Keith Frank Best, Joseph J. Consolini, Alexander Friz
  • Patent number: 7492443
    Abstract: A device manufacturing method according to one embodiment of the invention includes positioning a reflective patterning structure to reflect at least a portion of a beam of radiation as a patterned beam of radiation having a pattern in its cross-section. The method also includes using a projection system to project the patterned beam of radiation to form an image on a target portion of a layer of radiation-sensitive material. Positioning includes at least one among shifting and tilting a nominal reflective surface of the reflective patterning structure with respect to a nominal object plane of the projection system according to a distortion value.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: February 17, 2009
    Assignee: ASML Netherlands B.V.
    Inventors: Jan Evert Van Der Werf, Erik Roelof Loopstra, Hans Meiling, Johannes Hubertus Josephina Moors, Martinus Hendrikus Antonius Leenders
  • Publication number: 20090042115
    Abstract: An exposure apparatus for exposing a bright-dark pattern on a substrate via a projection optical system includes a position detection system which detects a plurality of predetermined positions in a unit exposure field of the substrate. A plurality of reference detection positions fall within a range substantially equal to the unit exposure field. A deformation calculation unit calculates a state of deformation in the unit exposure field based on the detection result of the position detection system. A shape modification unit modifies a shape of the bright-dark pattern to be exposed on the substrate based on the deformation state calculated by the deformation calculation unit.
    Type: Application
    Filed: February 27, 2008
    Publication date: February 12, 2009
    Applicant: NIKON CORPORATION
    Inventors: Hideya Inoue, Naomasa Shiraishi
  • Publication number: 20090035669
    Abstract: A work position information obtaining apparatus capable of obtaining a position of a work with respect to a table with high accuracy. Moving a table with a work placed thereon relative to an imaging section. Obtaining work position information representing a position of the work with respect to the table based on imaged information obtained by imaging table and work reference marks by the imaging section and moving direction positions of the table at the time of imaging the table and work reference marks. Obtaining the positional deviations of the table at the time of imaging the table and work reference marks, with reference to a positional deviation of the table obtained in advance in association with each of the moving direction positions of the table. Then, eliminating an error included in the work position information arising from the difference between each imaged positional deviation.
    Type: Application
    Filed: April 26, 2006
    Publication date: February 5, 2009
    Applicant: FUJIFILM CORPORATION
    Inventors: Hiroshi Uemura, Kazuhiro Terada, Takashi Fukui
  • Patent number: 7479356
    Abstract: A method, wherein a plurality of first patterns are formed in an exposure region, and second patterns are formed by plural shots, with positions of alignment marks measured for said plurality of first patterns to give first positional information; relative positions of said plurality of first patterns to a first coordinate system are measured, to thereby compute first disalignments relative to the first coordinate system; second positional information is computed by subtracting the first disalignments from the first positional information; relative positions of said plural basic regions with respect to a second coordinate system are measured, to thereby compute second disalignments of the first pattern relative to the second coordinate system; third positional information is computed by subtracting the first and second disalignments from the first positional information; third disalignments of the first pattern with respect to a third coordinate system are computed; and positioning with respect to the first p
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: January 20, 2009
    Assignee: Fujitsu Limited
    Inventor: Teruyoshi Yao
  • Patent number: 7477390
    Abstract: An exposure method of exposing a substrate arranged on a stage, which holds the substrate and moves, to light through an original and a projection optical system. A first measurement is performed for measuring a first drive characteristic of the stage by detecting a position of a pattern on the stage using a first detection system, which detects a position of a pattern on the substrate through an optical system, which does not include the projection optical system, a second measurement is performed for measuring a second drive characteristic of the stage by detecting the position of the pattern on the stage using a second detection system, which detects the position of the pattern on the stage through the projection optical system, and the original and the substrate are aligned based on the first and second drive characteristics.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: January 13, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shinichiro Koga
  • Patent number: 7477403
    Abstract: An optical position assessment apparatus and method has an illumination system that supplies an alignment beam of radiation, and positional data is derived from reflections of the alignment beam. A substrate is supported on a substrate table and a projection system is used to project the alignment beam onto a target portion of the substrate. A positioning system causes relative movement between the substrate and the projection system. An array of lenses is arranged such that each lens in the array focuses a respective portion of the alignment beam onto a respective part of the target portion. An array of detectors is arranged such that each detector in the array detects light reflected from the substrate through a respective lens in the array and provides an output representative of the intensity of light reflected to it from the substrate through the respective lens.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: January 13, 2009
    Assignee: ASML Netherlands B.V.
    Inventors: Cheng-Qun Gui, Fransiscus Godefridus Casper Bijnen, Johan Christiaan Gerard Hoefnagels, Pieter Willem Herman de Jager, Joannes Theodoor de Smit
  • Patent number: 7473502
    Abstract: A method of determining and correcting for distortions introduced by an imaging tool. The method includes providing an imaging tool having a field of view (FOV), and creating a target pattern containing a regular array of symmetric sub-patterns having locations spanning the FOV. Using the imaging tool, the method then includes measuring relative position of the sub-pattern images at one or more target orientations, determining tool-induced sub-pattern position deviations from designed locations of the sub-patterns, and applying corrections to compensate for an orientation independent component of the sub-pattern position deviations. The target pattern may be mounted on a stage of the measurement tool, created on a mask used in the lithographic process, or created on a wafer being measured by the measuring tool.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: January 6, 2009
    Assignees: International Business Machines Corporation, Nanometrics Incorporated
    Inventors: Chistopher P. Ausschnitt, Lewis A. Binns, Jennifer L. Morningstar, Nigel Smith
  • Patent number: 7474401
    Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: January 6, 2009
    Assignees: International Business Machines Corporation, Accent Optical Technologies
    Inventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
  • Publication number: 20090004580
    Abstract: By irradiating a detection beam from an irradiation system of a detection device to a scale used for measuring the position of a wafer stage, and detecting the detection beam via the scale by a photodetection system, a surface state (an existence state of foreign substance) of the scale is detected. With this operation, detection of the surface state can be performed contactlessly with respect to the scale. Moreover, movement control of the wafer stage can be performed with high precision by taking the surface state into consideration.
    Type: Application
    Filed: May 28, 2008
    Publication date: January 1, 2009
    Applicant: NIKON CORPORATION
    Inventor: Yuho Kanaya
  • Patent number: 7469638
    Abstract: An electronic device includes an array. In one embodiment, a process for forming an electronic device includes the array, which includes electronic components, can include printing one or more layers as a series of segments onto a workpiece. In one embodiment, a process includes printing a layer onto the workpiece and at least one exposed portion of the chuck. In still another embodiment, a printing head is greater than 0.5 mm from the workpiece. In a further embodiment, “hybrid” printing can be used to help form a thicker layer having a relatively thinner width. In a further embodiment, processes can be used to reduce the likelihood of a stitching defect, nonuniformity of a layer across an array, or a combination thereof. A printing apparatus can be modified to achieve more flexibility in liquid compositions, temperatures or other conditions used in printing a layer.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: December 30, 2008
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Charles Douglas MacPherson, Dennis Damon Walker, Matthew Stainer, Christopher Todd Knudson, Gang Yu