Including Multiple Resist Image Formation Patents (Class 430/312)
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Patent number: 9360758Abstract: In accordance with an embodiment, a method of filtering a process fluid such as a negative tone developer is provided. The negative tone developer is introduced to a filter membrane that comprises a fluorine-based polymer. The negative tone developer is then filtered through the filter membrane. By using these materials and methods, polyethylene from the filter membrane will not contaminate the photoresist during development and reduce defects that arise from polyethylene contamination.Type: GrantFiled: August 5, 2014Date of Patent: June 7, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Hsin Lo, Ching-Yu Chang
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Patent number: 9341940Abstract: A reticle and a method of fabricating the reticle are provided. In various embodiments, the reticle includes a substrate, a patterned first attenuating layer, a patterned second attenuating layer, and a patterned third attenuating layer. The patterned first attenuating layer is disposed on the substrate. The patterned second attenuating layer is disposed on the patterned first attenuating layer. The patterned third attenuating layer is disposed on the patterned second attenuating layer. A first part of the patterned first attenuating layer, a first part of patterned second attenuating layer, and the patterned third attenuating layer are stacked on the substrate as a binary intensity mask portion.Type: GrantFiled: May 15, 2014Date of Patent: May 17, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Chang Hsueh, Chia-Jen Chen, Ta-Cheng Lien, Hsin-Chang Lee
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Patent number: 9311439Abstract: Provided are methods of forming patterns of wafers using self-aligned double patterning processes. The methods include preparing an initial layout having a first design pattern, a second design pattern, and a third design pattern disposed between the first design pattern and the second design pattern, extracting a first sub-layout including the first design pattern and a second sub-layout including the second design pattern from the initial layout using a computer, forming a first modified sub-layout including a first modified design pattern obtained by modifying the first design pattern of the first sub-layout using the computer, generating a modified layout including the first modified sub-layout and the second sub-layout using the computer, and performing a double patterning process using the modified layout.Type: GrantFiled: July 21, 2014Date of Patent: April 12, 2016Assignee: Samsung Electronics Co., Ltd.Inventor: Moon-Gyu Jeong
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Patent number: 9219178Abstract: A method of fabrication of a collimator structure on a detector that includes applying a first layer of resist to a semiconductor sensor, applying a second layer of resist over the first layer of resist and the semiconductor sensor to cover both the first layer of resist and the semiconductor sensor, exposing the second layer of resist to ultraviolet (UV) light with a photomask to transfer a pattern from the photomask to the second layer of resist, removing portions of the second layer of resist corresponding to the pattern from the photomask to produce openings in the second layer of resist, which expose upper portions of the semiconductor sensor, and depositing a layer of metal in the openings and on the second layer of resist to cover the openings, the first layer of resist, the second layer of resist, and the semiconductor sensor.Type: GrantFiled: March 21, 2014Date of Patent: December 22, 2015Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEDICAL SYSTEMS CORPORATIONInventors: Yuexing Zhang, Daniel Gagnon, Xiaolan Wang
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Patent number: 9197183Abstract: The invention relates to a method of fabricating a single-piece micromechanical component including at least two distinct functional levels. According to the invention, the method includes a LIGA process on a single level combined with the machining of the LIGA deposition directly on the substrate.Type: GrantFiled: February 10, 2014Date of Patent: November 24, 2015Assignee: Nivarox-FAR S.A.Inventors: Alexandre Fussinger, Marc Stranczl
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Patent number: 9177825Abstract: According to one embodiment, a pattern forming method includes forming, on an underlying region, a neutral film having an affinity for first and second polymers, forming a first pinning part having an affinity for the first polymer by irradiating a first region of the neutral film with an energy beam, forming, on the neutral film including the first pinning part, a block copolymer film containing the first and second polymers, and performing a predetermined treatment for the block copolymer film to perform a microphase separation.Type: GrantFiled: August 25, 2014Date of Patent: November 3, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Yuriko Seino
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Patent number: 9134610Abstract: An underlayer coating is used as an underlayer of photoresists in lithography process of the manufacture of semiconductor devices and has a high dry etching rate in comparison to the photoresists, does not intermix with the photoresists, and is capable of flattening the surface of a semiconductor substrate having holes of a high aspect ratio; and an underlayer coating forming composition can form the underlayer coating. The underlayer coating forming composition for forming by light irradiation an underlayer coating used as an underlayer of a photoresist in a lithography process of the manufacture of semiconductor devices, includes a polymerizable substance and a photopolymerization initiator.Type: GrantFiled: March 12, 2013Date of Patent: September 15, 2015Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.Inventors: Satoshi Takei, Tetsuya Shinjo, Motohiko Hidaka
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Patent number: 9097975Abstract: A method of manufacturing using a double patterning method is provided. The double patterning method uses a first developer and a second developer that are different. For example, the first developer may be a positive tone developer for a positive photoresist while the second developer may be a negative tone developer for the positive photoresist. Photoresists having a photoactive compound are also provided that may be useful in double patterning methods. The resulting double patterning results, wherein a dimension of a variable first dense pattern is larger than a dimension of a variable second dense pattern.Type: GrantFiled: September 12, 2014Date of Patent: August 4, 2015Assignee: Macronix International Co., Ltd.Inventor: Chin Cheng Yang
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Publication number: 20150140482Abstract: A pattern forming method includes: (a) forming a first film on a substrate using an actinic ray-sensitive or radiation-sensitive resin composition (I) containing a resin of which solubility in a developer containing an organic solvent decreases due to polarity increased by an action of an acid; (b) exposing the first film; (c) developing the exposed first film using a developer containing an organic solvent to form a first negative pattern; (e) forming a second film on the substrate using an actinic ray-sensitive or radiation-sensitive resin composition (II) containing a resin of which solubility in a developer containing an organic solvent decreases due to polarity increased by an action of an acid; (f) exposing the second film; and (g) developing the exposed second film using a developer containing an organic solvent to form a second negative pattern in this order.Type: ApplicationFiled: January 27, 2015Publication date: May 21, 2015Applicant: FUJIFILM CORPORATIONInventors: Tsukasa YAMANAKA, Naoya IGUCHI, Ryosuke UEBA, Kei YAMAMOTO
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Patent number: 9029067Abstract: A resist pattern-insolubilizing resin composition is used in a resist pattern-forming method. The resist pattern-insolubilizing resin composition includes solvent and a resin. The resin includes a first repeating unit that includes a hydroxyl group in its side chain and at least one of a second repeating unit derived from a monomer shown by a following formula (1-1) and a third repeating unit derived from a monomer shown by a following formula (1-2), wherein for example, R1 represents a hydrogen atom, A represents a methylene group, R2 represents a group shown by a following formula (2-1) or a group shown by a following formula (2-2), R3 represents a methylene group, R4 represents a hydrogen atom, and n is 0 or 1, wherein each of R34 represents at least one of a hydrogen atom and a linear or branched alkyl group having 1 to 10 carbon atoms.Type: GrantFiled: September 16, 2014Date of Patent: May 12, 2015Assignee: JSR CorporationInventors: Gouji Wakamatsu, Masafumi Hori, Kouichi Fujiwara, Makoto Sugiura
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Patent number: 9017928Abstract: A resin structure for the formation of a micro-structure is manufactured by (A) applying a composition comprising a polymer, a photoacid generator, an epoxy compound, and an organic solvent onto a substrate, (B) heating the composition to form a sacrificial film, (C) exposing imagewise the film to first high-energy radiation, (D) developing the film in an alkaline developer to form a sacrificial film pattern, (E) exposing the sacrificial film pattern to UV as second high-energy radiation, and (F) heating the substrate at 80-250° C. The exposure dose of first high-energy radiation in step (C) is up to 250 mJ/cm2. At the end of step (F), the sacrificial film has a sidewall angle of 80°-90° relative to the substrate.Type: GrantFiled: January 14, 2014Date of Patent: April 28, 2015Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Yoshinori Hirano, Masashi Iio, Hideyoshi Yanagisawa
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Patent number: 9005875Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.Type: GrantFiled: March 15, 2013Date of Patent: April 14, 2015Assignee: Intel CorporationInventors: Robert L. Bristol, Paul A. Nyhus, Charles H. Wallace
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Patent number: 8993217Abstract: Innovative techniques are disclosed for fabricating microelectronic devices using an alternating phase shift mask. Some embodiments of the invention encompass a double exposure technique that utilize high resolution line patterning such that two opaque lines intersect at an angle. After development, substantially circular images may be formed. In certain embodiments, high resolution disk imaging as small as 60 nm is possible.Type: GrantFiled: May 30, 2013Date of Patent: March 31, 2015Assignee: Western Digital (Fremont), LLCInventors: Ling Wang, Dujiang Wan, Miao Wang, Hai Sun
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Patent number: 8993218Abstract: One or more techniques or systems for controlling a profile for photo resist (PR) are provided herein. In some embodiments, a first shield layer is formed on a first PR layer and a second PR layer is formed on the first shield layer. A first window is formed within the second PR layer during a first exposure with a mask. A second window is formed within the first shield layer based on the first window. A third window is formed within the first PR layer during a second exposure without a mask. Because, the third window is formed while the first shield layer and the second PR layer are on the first PR layer, a profile associated with the first PR layer is controlled. Contamination during ion bombardment is mitigated due to the controlled profile.Type: GrantFiled: February 20, 2013Date of Patent: March 31, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Li Huai Yang, Chien-Mao Chen
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Publication number: 20150079424Abstract: A substrate for suspension comprises a metallic substrate, an insulating layer formed on the metallic substrate, a conductor layer formed on the insulating layer, and a cover layer covering the conductor layer. The insulating layer and the cover layer are formed from different materials, whose coefficients of hygroscopic expansion are in the range between 3×10?6/% RH and 30×10?6/% RH. The difference between the coefficients of hygroscopic expansion of the two materials is 5×10?6/% RH or less.Type: ApplicationFiled: November 24, 2014Publication date: March 19, 2015Inventors: Yoichi HITOMI, Shinji KUMON, Terutoshi MOMOSE, Katsuya SAKAYORI, Kiyohiro TAKACHI, Yoichi MIURA, Tsuyoshi YAMAZAKI
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Publication number: 20150053456Abstract: A printed circuit board and a manufacturing method thereof. The manufacturing method of the printed circuit board includes: coating a first solder resist on an upper surface of a substrate having a circuit pattern formed thereon; removing the first solder resist in the remaining portion except a first specific area by performing primary development after exposing the substrate coated with the first solder resist; coating a second solder resist, which has different properties from the first solder resist, on the upper surface of the substrate having the first solder resist remaining in the first specific area; and removing the second solder resist in the remaining portion except a second specific area by performing secondary development after exposing the substrate coated with the second solder resist.Type: ApplicationFiled: December 19, 2013Publication date: February 26, 2015Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: CHANG BO LEE, MYEONG HO HONG, DAE JO HONG, YOUNG KYU LIM
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Patent number: 8956886Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.Type: GrantFiled: March 11, 2014Date of Patent: February 17, 2015Assignee: Applied Materials, Inc.Inventors: Samer Banna, Olivier Joubert, Lei Lian, Maxime Darnon, Nicolas Posseme, Laurent Vallier
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Publication number: 20150041303Abstract: Disclosed are a novel ITO crossover integrated capacitive touch screen and a manufacturing method thereof. The novel ITO crossover integrated capacitive touch screen comprises a transparent substrate, and a silicon dioxide layer, a niobium pentoxide layer, a black resin layer, an ITO crossover electrode, a first insulation layer, an ITO electrode, a metal electrode, and a second insulation layer sequentially stacked on the transparent substrate. The silicon dioxide layer covers the glass completely, and the niobium pentoxide layer covers the silicon dioxide layer completely. The ITO electrode comprises a capacitive screen driver and a sensing electrode, and is provided with a patterned graphic structure. The capacitive screen driver and the sensing electrode are on the same layer, mutually independent, mutually insulated, and vertical in design.Type: ApplicationFiled: March 14, 2013Publication date: February 12, 2015Inventor: Xiaoxing Cao
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Patent number: 8945800Abstract: In a multiple patterning techniques, where two or more exposures are used to form a single layer of a device, the splitting of features in a single layer between the multiple exposures is carried out additionally with reference to features of another associated layer and the splitting of that layer into two or more sets of features for separate exposure. The multiple exposure process can be a process involving repeated litho-etch steps desirably, the alignment scheme utilized during exposure of the split layers is optimized with reference to the splitting approach.Type: GrantFiled: August 12, 2013Date of Patent: February 3, 2015Assignee: ASML Netherlands B.V.Inventors: Tsann-Bim Chiou, Mircea Dusa, Alek Chi-Heng Chen
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Patent number: 8921233Abstract: Some embodiments provide microelectronic fabrication methods in which a sacrificial pattern is formed on a substrate. A spacer formation layer is formed on the substrate, the spacer formation layer covering the sacrificial pattern. The spacer formation layer is etched to expose an upper surface of the sacrificial pattern and to leave at least one spacer on at least one sidewall of the sacrificial pattern. A first portion of the sacrificial pattern having a first width is removed while leaving intact a second portion of the sacrificial pattern having a second width greater than the first width to thereby form a composite mask pattern including the at least one spacer and a portion of the sacrificial layer. An underlying portion of the substrate is etched using the composite mask pattern as an etching mask.Type: GrantFiled: September 23, 2011Date of Patent: December 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-hwang Sim, Min-chul Kim
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Patent number: 8912097Abstract: A method of patterning a substrate comprises providing an array of resist features defined by a first pitch and a first gap width between adjacent resist features. Particles are introduced into the array of resist features, wherein the array of resist features becomes hardened. The introduction of particles may cause a reduction in critical dimension of the resist features. Sidewalls are provided on side portions of hardened resist features. Subsequent to the formation of the sidewalls, the hardened resist features are removed, leaving an array of isolated sidewalls disposed on the substrate. The sidewall array provides a mask for double patterning of features in the substrate layers disposed below the sidewalls, wherein an array of features formed in the substrate has a second pitch equal to half that of the first pitch.Type: GrantFiled: August 19, 2010Date of Patent: December 16, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Patrick M. Martin, Steven Carlson, Choong-Young Oh, Jung-Wook Park
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Patent number: 8895231Abstract: A pattern is formed by coating a first positive resist composition comprising a base resin, a photoacid generator, and a base generator having both a 9-fluorenylmethyloxycarbonyl-substituted amino group and a carboxyl group onto a substrate to form a first resist film, patternwise exposure, PEB, and development to form a first resist pattern, heating the first resist pattern for causing the base generator to generate a base for inactivating the pattern to acid, coating a second positive resist composition comprising an alcohol and an optional ether onto the first resist pattern-bearing substrate to form a second resist film, patternwise exposure, PEB, and development to form a second resist pattern.Type: GrantFiled: September 2, 2011Date of Patent: November 25, 2014Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Jun Hatakeyama, Kazuhiro Katayama
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Patent number: 8881353Abstract: Provided is a method of producing a piezoelectric/electrorestrictive film type device including a vibrating laminate obtained by laminating electrode films and piezoelectric/electrorestrictive films on a substrate containing a cavity. The method of producing the vibrating laminate includes: producing the substrate with a cavity, forming the first photoresist film on first principal surface of substrate, irradiating substrate from the second principal surface side of the substrate, transferring the plane shape of the cavity to the first photoresist film, developing and removing the first photoresist film formed in the region where the shape of cavity was formed, forming a lowermost electrode film by plating, and forming additional films other than the lowermost electrode film constituting the vibrating laminate.Type: GrantFiled: September 6, 2010Date of Patent: November 11, 2014Assignee: NGK Insulators, Ltd.Inventors: Hideki Shimizu, Mutsumi Kitagawa
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Patent number: 8877429Abstract: A resist pattern-insolubilizing resin composition is used in a resist pattern-forming method. The resist pattern-insolubilizing resin composition includes solvent and a resin. The resin includes a first repeating unit that includes a hydroxyl group in its side chain and at least one of a second repeating unit derived from a monomer shown by a following formula (1-1) and a third repeating unit derived from a monomer shown by a following formula (1-2), wherein for example, R1 represents a hydrogen atom, A represents a methylene group, R2 represents a group shown by a following formula (2-1) or a group shown by a following formula (2-2), R3 represents a methylene group, R4 represents a hydrogen atom, and n is 0 or 1, wherein each of R34 represents at least one of a hydrogen atom and a linear or branched alkyl group having 1 to 10 carbon atoms.Type: GrantFiled: January 12, 2011Date of Patent: November 4, 2014Assignee: JSR CorporationInventors: Gouji Wakamatsu, Masafumi Hori, Kouichi Fujiwara, Makoto Sugiura
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Patent number: 8859187Abstract: A novel method of forming a resist pattern in which thickness loss from the resist pattern is reduced, and a negative resist composition that can be used in this method of forming a resist pattern. The method of forming a resist pattern includes: forming a first resist film by applying a first resist composition to a support, forming a first resist pattern by selectively exposing the first resist film through a first mask pattern and then developing the first resist film, forming a second resist film by applying a negative resist composition containing an ether-based organic solvent (S?) having no hydroxyl groups onto the support having the first resist pattern formed thereon, and forming a resist pattern by selectively exposing the second resist film through a second mask pattern and then developing the second resist film.Type: GrantFiled: October 19, 2007Date of Patent: October 14, 2014Assignee: Tokyo Ohka Kogyo Co., Ltd.Inventors: Ken Tanaka, Sho Abe, Shigeru Yokoi
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Patent number: 8852491Abstract: In a method of manufacturing an electroforming mold, a first photoresist layer is formed on an upper surface of a bottom conductive film of a substrate, and the first photoresist layer is divided into a first soluble portion and a first insoluble portion. A conductive material is thermally deposited on an upper surface of the first photoresist layer within a predetermined temperature range, to thereby form an intermediate conductive film. An intermediate conductive film is patterned. A second photoresist layer is formed on an exposed upper surface of the first photoresist layer after the intermediate conductive film is removed, and on an upper surface of the intermediate conductive film remaining after patterning. The second photoresist layer is divided into a second soluble portion and a second insoluble portion. Next, the first and second photoresist layers are developed, and the first and second soluble portions are removed.Type: GrantFiled: May 20, 2013Date of Patent: October 7, 2014Assignee: Seiko Instruments Inc.Inventors: Takashi Niwa, Matsuo Kishi, Koichiro Jujo, Hiroyuki Hoshina
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Patent number: 8852830Abstract: A photomask for exposing a region on a substrate, with a mask pattern, including a first line pattern, a second line pattern, a first connection pattern for a peripheral portion of the region and a second connection pattern for the peripheral portion, wherein the first connection pattern is wider than the first line pattern and the second connection pattern is wider than the second line pattern, a distance from a virtual line between the first line pattern and the second line pattern to a center line of the first connection pattern is larger than a distance from the virtual line to a center line of the first line pattern and a distance from the virtual line to a center line of the second connection pattern is larger than a distance from the virtual line to a center line of the second line pattern.Type: GrantFiled: February 19, 2013Date of Patent: October 7, 2014Assignee: Canon Kabushiki KaishaInventors: Satoshi Hirayama, Atsushi Kanome
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Publication number: 20140272714Abstract: A method of lithography patterning includes forming a first resist pattern on a substrate, wherein the first resist pattern including a plurality of openings. A second resist pattern is formed on the substrate and within the plurality of openings of the first resist pattern, wherein the second resist pattern includes at least one opening therein on the substrate. The first resist pattern is removed to uncover the substrate underlying the first resist pattern.Type: ApplicationFiled: June 3, 2014Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: CHUN-KUANG CHEN, Hsiao-Wei Yeh, Chih-An Lin, Chien-Wei Wang, Feng-Cheng Hsu
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Patent number: 8835100Abstract: A method of manufacturing using a double patterning method is provided. The double patterning method uses a first developer and a second developer that are different. For example, the first developer may be a positive tone developer for a positive photoresist while the second developer may be a negative tone developer for the positive photoresist. Photoresists having a photoactive compound are also provided that may be useful in double patterning methods.Type: GrantFiled: September 14, 2012Date of Patent: September 16, 2014Assignee: Macronix International Co., Ltd.Inventor: Chin Cheng Yang
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Patent number: 8835083Abstract: A manufacturing method of a photomask by which a resist pattern corresponding to a pattern with designed values can be formed, a method for optical proximity correction, and a manufacturing method of a semiconductor device are provided. Proximity design features that are close to each other and estimated to violate a mask rule check are extracted. In the proximity design features, correction prohibited regions where optical proximity correction is not carried out are set based on the distance between the features obtained from the extracted proximity design features and the resolution of an exposure device. Optical proximity correction is carried out on the proximity design features with the correction prohibited regions excluded to obtain corrected proximity patterns. A predetermined mask material is patterned by carrying out electron beam lithography based on the corrected proximity pattern data.Type: GrantFiled: October 2, 2013Date of Patent: September 16, 2014Assignee: Renesas Electronics CorporationInventors: Ayumi Minamide, Akemi Moniwa, Akira Imai
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Patent number: 8822137Abstract: An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures.Type: GrantFiled: August 3, 2011Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Qinghuang Lin, Sanjay Mehta, Hosadurga Shobha
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Patent number: 8815473Abstract: Techniques for reducing the number of shots required by a radiation beam writing tool to write a pattern, such as fractured layout design, onto a substrate. One or more apertures are employed by a radiation beam writing tool to write a desired pattern onto a substrate using L-shaped images, T-shaped images, or some combination of both. By reducing the number of shots required to write a pattern onto a substrate, various implementations of the invention may reduce the write time and/or write complexity of the write process.Type: GrantFiled: October 12, 2010Date of Patent: August 26, 2014Inventors: Emile Y. Sahouria, Steffen F. Schulze
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Patent number: 8808971Abstract: A method for forming fine patterns of a semiconductor device employs a double patterning characteristic using a mask for forming a first pattern including a line pattern and a mask for separating the line pattern, and a reflow characteristic of a photoresist pattern.Type: GrantFiled: May 15, 2013Date of Patent: August 19, 2014Assignee: SK hynix Inc.Inventor: Jae Seung Choi
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Patent number: 8802566Abstract: A method for producing semiconductor components on a substrate including photolithographic patterning steps, in which method, on the substrate, a first layer to be patterned is applied and a second layer serving as a mask layer for the first layer to be patterned is applied, wherein a third layer serving as a mask for the second layer is applied, and wherein at least two photolithographic patterning processes are carried out successively for the second layer, wherein, during one of the patterning processes, after the production of a structure made from a photosensitive layer for the provision of a mask layer for a patterning process at the third layer, positive ramp angles ? are produced at the patterning edges of the third layer, as a result of which the structures remaining free, given a thickness h of the third layer, decrease in size by a value D=2*h/tan ?.Type: GrantFiled: August 24, 2012Date of Patent: August 12, 2014Assignee: Espros Photonics AGInventors: Martin Popp, Beat De Coi, Marco Annese
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Patent number: 8802574Abstract: One illustrative method disclosed herein involves creating an overall target pattern that includes an odd-jogged feature with a crossover region that connects first and second line portions, wherein the crossover region has a first dimension in a first direction that is greater than a second dimension that is transverse to the first direction, decomposing the overall target pattern into a first sub-target pattern and a second sub-target pattern, wherein each of the sub-target patterns comprise a line portion and a first portion of the crossover region, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, respectively.Type: GrantFiled: March 13, 2012Date of Patent: August 12, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Lei Yuan, Jongwook Kye
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Publication number: 20140205952Abstract: Methods of forming a pattern in a semiconductor device structure include deprotecting an outer portion of a first photosensitive resist material, forming a second photosensitive resist material, exposing portions of the first and second photosensitive resist materials to radiation, and removing the deprotected outer portion of the first photosensitive resist material and the exposed portions of the first and second photosensitive resist materials. Additional methods include forming a first resist material over a substrate to include a first portion and a relatively thicker second portion, deprotecting substantially the entire first portion and an outer portion of the second portion while leaving an inner portion of the second portion protected, and forming a second resist material over the substrate. A portion of the second resist material is exposed to radiation, and deprotected and exposed portions of the first and second resist materials are removed.Type: ApplicationFiled: January 22, 2013Publication date: July 24, 2014Applicant: Micron Technology, Inc.Inventors: Scott Light, Yuan He, Michael A. Many, Michael Hyatt
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Publication number: 20140205953Abstract: A method for forming a semiconductor device comprises the following steps: first, a substrate is provided, a first photo-etching process is carried out with a first photomask to form at least one device structure and a plurality of compensation structures, wherein the first photomask comprises at least one device pattern and a plurality of dummy patterns. A photoresist layer is then formed on the device structure and each compensation structures; a second photo-etching process is then carried out with a second photomask to remove each compensation structure.Type: ApplicationFiled: January 22, 2013Publication date: July 24, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Po-Chao Tsao, Chia-Jui Liang, En-Chiuan Liou
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Publication number: 20140205934Abstract: A reticle for multiple patterning a layer of an integrated circuit die includes a first portion with a first layout pattern for multiple patterning the layer of the integrated circuit die, and a second portion with a second layout pattern for multiple patterning the layer of the integrated circuit die. The first layout pattern is different from the second layout pattern.Type: ApplicationFiled: January 21, 2013Publication date: July 24, 2014Applicant: XILINX, INC.Inventor: Xilinx, Inc.
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Publication number: 20140186595Abstract: The present invention relates to a method of fabricating a display device using a maskless exposure apparatus, and the display device, and more particularly, to a method of fabricating a display device by using a maskless exposure apparatus, which is capable of preventing a stain from being viewed, and the display device.Type: ApplicationFiled: April 11, 2013Publication date: July 3, 2014Applicant: Samsung Display Co., LtdInventors: SANG HYUN YUN, CHA-DONG KIM, JUNG-IN PARK, JAE HYUK CHANG, HI KUK LEE
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Patent number: 8765612Abstract: A double patterning process is described. A substrate having a first area and a second area is provided. A target layer is formed over the substrate. A patterned first photoresist layer is formed over the target layer, wherein the patterned first photoresist layer has openings and has a first thickness in the first area, and at least a portion of the patterned first photoresist layer in the second area has a second thickness less than the first thickness. A second photoresist layer is then formed covering the patterned first photoresist layer and filling in the openings.Type: GrantFiled: September 14, 2012Date of Patent: July 1, 2014Assignee: Nanya Technology CorporationInventors: Jenn-Wei Lee, Hung-Jen Liu
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Publication number: 20140178803Abstract: A composite mask suitable for multiple-patterning lithographic processes and a multiple-patterning photolithographic process utilizing the mask are disclosed. An exemplary embodiment includes receiving a mask having a plurality of sub-reticles and a substrate having one or more regions. A first sub-reticle of the plurality of sub-reticles is aligned with a first region of the one or more regions. A movement pattern is designated relative to the substrate. A first photolithographic process is performed including exposing the substrate using the mask to form a first exposed area on the substrate. An alignment of the mask relative to the substrate is shifted according to a first direction determined by the movement pattern. A second photolithographic process is performed including exposing the substrate using the mask to form a second exposed area on the substrate such that the second exposed area overlaps the first.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chue San Yoo, Yung-Cheng Chen, Li-Wei Kung, Chang-Jyh Hsieh
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Patent number: 8741548Abstract: A pattern is formed by applying a first positive resist composition onto a substrate, heat treatment, exposure, heat treatment and development to form a first resist pattern; causing the first resist pattern to crosslink and cure by irradiation of high-energy radiation of up to 180 nm wavelength or EB; further applying a second positive resist composition onto the substrate, heat treatment, exposure, heat treatment and development to form a second resist pattern. The double patterning process reduces the pitch between patterns to one half.Type: GrantFiled: August 19, 2008Date of Patent: June 3, 2014Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Jun Hatakeyama, Takao Yoshihara, Katsuya Takemura, Yoshio Kawai
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Patent number: 8728722Abstract: A method for producing a device in one or more layers of patternable material disposed over a substrate uses multiple exposure tools having different resolution limits and maximum expose field sizes. An abutting field pattern is exposed and stitched in one layer of patternable material using one exposure tool and a first mask. A periphery pattern is then exposed in the same layer or in a different layer of patternable material using a second exposure tool and a second mask. The maximum expose field of the first exposure tool is smaller than a size of the device while the maximum expose field of the second exposure tool is at least as large as, or larger, the size of the device so that the combination of the stitched abutting field pattern and the periphery pattern forms a complete pattern in the patternable material.Type: GrantFiled: August 2, 2011Date of Patent: May 20, 2014Assignee: Truesense Imaging, Inc.Inventors: Robert P. Fabinski, Eric J. Meisenzahl, James E. Doran, Joseph R. Summa
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Patent number: 8728713Abstract: A method for producing a measurement structure for measuring alignment of patterns formed in one or more layers of patternable material uses multiple exposure tools having different resolution limits and maximum expose field sizes. The measurement structure includes multiple complementary and coincident parts. An abutting field pattern is exposed and stitched in a layer of patternable material using a first exposure tool and a first mask. The abutting field pattern includes a first portion of the multiple complementary parts. A periphery pattern is exposed in the same layer or in a different layer of patternable material using a second exposure tool and a second mask. The periphery pattern includes a second portion of the multiple complementary parts. A maximum expose field of the first exposure tool is smaller than the maximum expose field of the second exposure tool.Type: GrantFiled: August 2, 2011Date of Patent: May 20, 2014Assignee: Truesense Imaging, Inc.Inventors: Robert P. Fabinski, Eric J. Meisenzahl, James E. Doran
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Patent number: 8728710Abstract: Disclosed is a method of making polysiloxane and polysilsesquioxane based hardmask respond to radiations with positive tone and negative tone simultaneously. Unradiated films are insoluble in developers, showing positivity tone. Radiated films are insoluble in developers as well, showing negative tone. Only half-way radiated films are soluble in developers. The dual-tone photo-imageable hardmask produces splitted patterns. Compositions of dual-tone photo-imageable hardmask based on the chemistry of polysiloxane and polysilsesquioxanes are disclosed as well. Further disclosed are processes of using photo-imageable hardmasks to create precursor structures on semiconductor substrates with or without an intermediate layer.Type: GrantFiled: March 30, 2010Date of Patent: May 20, 2014Inventor: Sam Xunyun Sun
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Publication number: 20140134543Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.Type: ApplicationFiled: November 14, 2012Publication date: May 15, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventor: Yu-Cheng Tung
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Publication number: 20140131305Abstract: A method for forming wires with a narrow spacing is provided. The method includes the steps of: sequentially forming a first metal layer and a protective layer on a substrate; using a first photomask to pattern the first metal layer and the protective layer, so as to form a first metal line and a patterned protective layer thereon; forming a second metal layer on the substrate and the patterned protective layer; using a second photomask to pattern the second metal layer, so as to form a second metal line adjacent to the first metal line; and removing the patterned protective layer on the first metal line. According to the method, the wires can be located at the same layer with a narrow spacing, thereby avoiding a problem that the wires are easily broken.Type: ApplicationFiled: January 9, 2013Publication date: May 15, 2014Applicant: CHUNGHWA PICTURE TUBES, LTD.Inventor: Han-tung HSU
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Patent number: 8722541Abstract: A method of fabricating a semiconductor device is disclosed. The exemplary method includes providing a substrate including a device layer and a sacrificial layer formed over the device layer and patterning the sacrificial layer thereby defining a cut pattern. The cut pattern of the sacrificial layer having an initial width. The method further includes depositing a mask layer over the device layer and over the cut pattern of the sacrificial layer. The method further includes patterning the mask layer thereby defining a line pattern including first and second portions separated by the cut pattern of the sacrificial layer and selectively removing the cut pattern of the sacrificial layer thereby forming a gap that separates the first and second portions of the line pattern of the mask layer. The method further includes patterning the device layer using the first and second portions of the line pattern of the mask layer.Type: GrantFiled: March 15, 2012Date of Patent: May 13, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chih-Han Lin
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Patent number: 8722313Abstract: A method of manufacturing a touch screen panel includes a first process, a second process, and a third process. Each of a plurality of first electrode serials includes a plurality of first electrode patterns which are separated from each other, neighboring first electrode patterns are electrically connected to each other via a first connection pattern, and a first insulation pattern electrically insulates the first electrode serial from the second electrode serial at an intersection of the first electrode serial and the second electrode serial.Type: GrantFiled: December 3, 2010Date of Patent: May 13, 2014Assignee: LG Display Co., Ltd.Inventor: Seungmok Shin
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Publication number: 20140125885Abstract: Disclosed herein are a touch panel and a method for manufacturing the same, the touch panel including: a transparent substrate; a black matrix pattern provided on an upper surface of the transparent substrate, the black matrix pattern having a plurality of openings; first electrode patterns provided on the black matrix pattern; and second electrode patterns provided on a lower surface of the transparent substrate, so that the touch panel includes the first electrode patterns formed of a silver salt, over the black matrix pattern having the plurality of openings, and thus can prevent a moiré phenomenon due to a metal material and improve visibility.Type: ApplicationFiled: November 7, 2013Publication date: May 8, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jung Eun Noh, Seung Heon Han, Hee Soo Kim, Jung Tae Park, Sung Yeol Park