Abstract: Compositions characterized by the presence of an aqueous base-soluble polymer having aromatic moieties and aliphatic alcohol moieties have been found which are especially useful as developable bottom antireflective coatings in 193 nm lithographic processes. The compositions enable improved lithographic processes which are especially useful in the context of subsequent ion implantation or other similar processes where avoidance of aggressive antireflective coating removal techniques is desired.

Abstract: A layout method for a bridging electrode capable of shielding a bright spot includes the steps of: providing a substrate; forming a transparent electroconductive layer, having neighboring pattern blocks, on the substrate; forming an alignment film layer, having bridging grooves for crossing between the pattern blocks, over the substrate; forming an electroconductive layer, having wires respectively correspondingly disposed over the bridging grooves, over the substrate; forming an electroconductive correspondence layer on one side of the electroconductive layer to shield the wires; and forming a protection layer over the substrate to enhance optical transmission and protect the substrate, the transparent electroconductive layer, the alignment film layer and the electroconductive layer. Meanwhile, the invention also provides a structure of the bridging electrode capable of shielding the bright spot and corresponding to the layout method.

Abstract: A manufacturing method for a piezoelectric/electrostrictive film type element and a film constituting a laminated vibrator made of laminations of an electrode film and a piezoelectric/electrostrictive film in a plane position. The piezoelectric/electrostrictive film type element includes a substrate, a lower electrode film provided on the substrate, and a laminated vibrator made of laminations of a piezoelectric/electrostrictive film and an upper electrode film. The lower electrode film is formed by a photolithography method with the substrate, where a cavity is filled with a light shielding agent, as a mask. Thereafter, the piezoelectric/electrostrictive film is formed by electrophoresis of powder of a piezoelectric/electrostrictive material toward the lower electrode film, and the upper electrode film is formed by the photolithography method with the piezoelectric/electrostrictive film as a mask.

Abstract: A method of forming a pattern including: forming an underlayer film on a support using an underlayer film-forming material, forming a hard mask on the underlayer film using a silicon-based hard mask-forming material, forming a first resist film by applying a chemically amplified positive resist composition to the hard mask, forming a first resist pattern by selectively exposing the first resist film through a first mask pattern and then performing developing, forming a first pattern by etching the hard mask using the first resist pattern as a mask, forming a second resist film by applying a chemically amplified positive silicon-based resist composition to the first pattern and the underlayer film, forming a second resist pattern by selectively exposing the second resist film through a second mask pattern and then performing developing, and forming a second pattern by etching the underlayer film using the first pattern and the second resist pattern as a mask.

Abstract: A method for forming a pattern contains (1) a step of forming an underlayer film containing (A) a radiation-sensitive acid generator capable of generating an acid upon exposure to radiation rays or (B) a radiation-sensitive base generator capable of generating a base upon exposure to radiation rays on a substrate; (2) a step of irradiating the underlayer film with radiation rays through a mask with a predetermined pattern to obtain an exposed underlayer film portion having been selectively exposed through the predetermined pattern; (3) a step of forming (C) an organic thin film on the underlayer film so as to attain chemical bonding of the exposed underlayer film portion with the organic thin-film formed on the exposed underlayer film portion; and (4) a step of removing the organic thin film formed on areas of the underlayer film other than the exposed underlayer film portion.

Abstract: Nozzle members, such as for a micro-fluid ejection head, micro-fluid ejection heads, and a method for making the same. One such nozzle member includes a negative photoresist composition derived from a first di-functional epoxy compound, a relatively high molecular weight polyhydroxy ether, a photoacid generator devoid of aryl sulfonium salts, an adhesion enhancer, and an aliphatic ketone solvent. The nozzle member has a thickness ranging from about 10 microns to about 30 microns.

Abstract: A three dimensional scaffold having a three dimensional structure is easily fabricated by employing a lithography process used in a semiconductor manufacturing process. A method of fabricating the same is also disclosed have a conformational structure. In the method of fabricating a three dimensional scaffold having the conformational structure according to the present invention, a first pattern is first formed on a substrate by using a first photoresist through a lithography process, and a temporary photoresist is coated on a whole surface of the substrate. Next, a temporary pattern exposing the upper part of the first pattern to the surface is formed by using the lithography process, and a second photoresist contacting the first pattern via the temporary pattern is coated on the whole surface of the substrate.

Abstract: A method of forming fine patterns of a semiconductor device includes forming a plurality of first mask patterns on a substrate such that the plurality of first mask patterns are separated from one another by a space located therebetween, in a direction parallel to a main surface of the substrate, forming a plurality of capping films formed of a first material having a first solubility in a solvent on sidewalls and a top surface of the plurality of first mask patterns. The method further includes forming a second mask layer formed of a second material having a second solubility in the solvent, which is less than the first solubility, so as to fill the space located between the plurality of first mask patterns, and forming a plurality of second mask patterns corresponding to residual portions of the second mask layer which remain in the space located between the plurality of first mask patterns, after removing the plurality of capping films and a portion of the second mask layer using the solvent.

Abstract: The method of forming an etching mask includes: forming a mask layer on an object layer that is to be etched, to form an etching mask used in etching the object layer; forming a first mask layer on the mask layer, the first mask layer having a first pattern that is to be transferred onto the mask layer; forming a second mask layer on the first mask layer, the second mask layer having a second pattern that is to be transferred onto the mask layer; obtaining a third mask layer having the first pattern and the second pattern, by transferring the second pattern of the second mask layer onto the first mask layer; and forming the etching mask used in the etching of the object layer, by etching the mask layer using the third mask layer.

Abstract: Disclosed is a patterning method including: forming a first film on a substrate; forming a multi-layered film including a resist film on the first film; forming a patterned resist film having a preset pattern by patterning the resist film by photolithography; forming a silicon oxide film different from the first film on the patterned resist film and the first film by alternately supplying a first gas containing organic silicon and a second gas containing an activated oxygen species to the substrate; etching the silicon oxide film to thereby form a sidewall spacer on a sidewall of the patterned resist film; removing the patterned resist film; and processing the first film by using the sidewall spacer as a mask.

Abstract: A method forms a first patterned mask (comprising rectangular features and/or rounded openings) on a planar surface and forms a second patterned mask on the first patterned mask and the planar surface. The second patterned mask covers protected portions of the first patterned mask and the second patterned mask reveals exposed portions of the first patterned mask. The method treats the exposed portions of the first patterned mask with a chemical treatment that reduces the size of the exposed portions to create an altered first patterned mask.

Abstract: Disclosed are an exposure mask, a photolithography method, a method of manufacturing a substrate and a display panel which can reduce the number of exposure masks required. The photolithography method uses an exposure mask 1a having a semi-transmissive pattern 12a, which blocks the light energy of the first wavelength band, and a semi-transmissive pattern 13a, which blocks the light energy of the second wavelength band. The photolithography method includes the steps of: forming a first photoresist material film 27; conducting an exposure process on the first photoresist material film 27 using the exposure mask 1a and the light energy of the first wavelength band; conducting a development process on the photoresist material film 27; forming a second photoresist film 28; conducting an exposure process on the second photoresist film 28 using the exposure mask 1a and the light energy of the second wavelength band; and conducting a development process on the second photoresist film 28.

Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a first resist pattern made of a first resist material on a workpiece material; irradiating an energy beam onto the first resist pattern, the energy beam exposing the first resist material to light; performing a treatment for improving resistance the first resist pattern after irradiation of the energy beam; forming a coating film on the workpiece material so as to cover the first resist pattern; and forming a second resist pattern made of a second resist material on the coating film after the treatment.

Abstract: A method of forming a mask for use in fabricating an integrated circuit includes forming first non-removable portions of a photoresist material through a mask having a plurality of apertures, shifting the mask, forming second non-removable second portions of the photoresist material overlapping the first portions, and removing removable portions of the photoresist material arranged between the first and second portions. The formed photoresist mask may be used to form vias in an integrated circuit. The pattern of vias produced have the capability to exceed the current imaging resolution of a single exposure treatment.

Abstract: A method for producing a device in one or more layers of patternable material disposed over a substrate uses multiple exposure tools having different resolution limits and maximum expose field sizes. An abutting field pattern is exposed and stitched in one layer of patternable material using one exposure tool and a first mask. A periphery pattern is then exposed in the same layer or in a different layer of patternable material using a second exposure tool and a second mask. The maximum expose field of the first exposure tool is smaller than a size of the device while the maximum expose field of the second exposure tool is at least as large as, or larger, the size of the device so that the combination of the stitched abutting field pattern and the periphery pattern forms a complete pattern in the patternable material.

Abstract: A method for producing a measurement structure for measuring alignment of patterns formed in one or more layers of patternable material uses multiple exposure tools having different resolution limits and maximum expose field sizes. The measurement structure includes multiple complementary and coincident parts. An abutting field pattern is exposed and stitched in a layer of patternable material using a first exposure tool and a first mask. The abutting field pattern includes a first portion of the multiple complementary parts. A periphery pattern is exposed in the same layer or in a different layer of patternable material using a second exposure tool and a second mask. The periphery pattern includes a second portion of the multiple complementary parts. A maximum expose field of the first exposure tool is smaller than the maximum expose field of the second exposure tool.

Abstract: Disclosed herein is a method for fabricating a probe needle tip of a probe card, in which, in order to prevent a poor grinding effect caused by irregular removal or flexibility of the photoresists laminated to be high in the course of polishing a first metal loaded into the opening of the photoresists laminated into a multilayer configuration upon formation of the probe needle tip of the probe card, a second metal is laminated on any one of one or more stacked photoresist layers, thus firmly holding the photoresist layers on/beneath the metal.

Abstract: Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance.

Abstract: A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.

Abstract: In a multiple-exposure lithographic process a developed resist pattern derived from a first exposure is present within a second resist layer that is exposed in a second exposure of the multiple-exposure lithographic process. The second mask pattern used in the second exposure process includes at least one localized adjustment to at least one feature thereof to compensate for scattering effects of the developed resist pattern that is present when the second exposure is performed.

Abstract: Disclosed is a method for manufacturing a semiconductor device. The method comprises: forming a resist layer over a substrate; exposing the resist layer to light thereby to form a first exposed pattern and a second exposed pattern on the resist layer, the second exposed pattern being used for forming one or more trenches; contacting the resist layer with a developing solution thereby to form a patterned resist having an opening corresponding to the first exposed pattern and to form one or more trenches corresponding to the second exposed pattern on a surface layer of the patterned resist; and conducting a bake process on the patterned resist.

Abstract: A new lithographic process comprises reducing the linewidth of an image while maintaining the lithographic process window, and using this process to fabricate pitch split structures comprising nm order (e.g., about 22 nm) node semiconductor devices. The process comprises applying a lithographic resist layer on a surface of a substrate and patterning and developing the lithographic resist layer to form a nm order node image having an initial line width. Overcoating the nm order node image with an acidic polymer produces an acidic polymer coated image. Heating the acidic polymer coated image gives a heat treated coating on the image, the heating being conducted at a temperature and for a time sufficient to reduce the initial linewidth to a subsequent narrowed linewidth. Developing the heated treated coating removes it from the image resulting in a free-standing trimmed lithographic feature on the substrate. Optionally repeating the foregoing steps further reduces the linewidth of the narrowed line.

Abstract: In a method of forming a hard mask pattern in a semiconductor device, only processes for forming patterns having a row directional line shape and a column directional line shape on a plane are performed so that the hard mask patterns can be formed to define densely disposed active regions. A pitch of the hard mask patterns is less than a resolution limit of an exposure apparatus.

Abstract: This invention provides methods of creating via or trench structures on a developer-soluble hardmask layer using a multiple exposure-development process. The hardmask layer is patterned while the imaging layer is developed. After the imaging layer is stripped using organic solvents, the same hardmask can be further patterned using subsequent exposure-development processes. Eventually, the pattern can be transferred to the substrate using an etching process.

Abstract: Provided is a photomask that includes a substrate having a first region and a second region, a first pattern disposed in the first region of the substrate, and a second pattern disposed in the second region of the substrate. The first and second patterns are a decomposition of a design pattern to be transferred onto a wafer in a lithography process.

Abstract: Methods of forming features such as word lines of memory circuitry are disclosed. One such method includes forming an initial pitch multiplied feature pattern extending from a target area into only one of a first or second periphery area received on opposing sides of the target area. Thereafter, a subsequent feature pattern is formed which extends from the target array area into the other of the first or second periphery area. The initial and subsequent feature patterns may be used in forming features in an underlying material which extend from the target area to the first and second periphery areas. Other embodiments are disclosed.

Abstract: The invention concerns a process for the production of a multi-layer body, wherein the multi-layer body includes at least two functional layers on a top side of a carrier substrate, which are structured in register relationship with each other, by a procedure whereby an underside of the carrier substrate is prepared in such a way that in a first region there results a transparency for a first exposure radiation and in at least one second region there results a transparency for at least one second exposure radiation different therefrom in register relationship with the first region, the underside is successively exposed with the first and the at least one second exposure radiation and the first exposure radiation is used for structuring a first functional layer and the at least one second exposure radiation is used for structuring at least one second functional layer on the top side of the carrier substrate.

Abstract: A method of improving damascene wire uniformity without reducing performance. The method includes simultaneously forming a multiplicity of damascene wires and a multiplicity of metal dummy shapes in a dielectric layer of a wiring level of an integrated circuit chip, the metal dummy shapes being dispersed between damascene wires of the multiplicity of damascene wires; and removing or modifying those metal dummy shapes of the multiplicity of metal dummy shapes within exclusion regions around selected damascene wires of the multiplicity of damascene wires. Also a method of fabricating a photomask and a photomask for use in improving damascene wire uniformity without reducing performance.

Abstract: The present invention provides a resist pattern thickening material, which can utilize ArF excimer laser light; which, when applied over a resist pattern such as an ArF resist having a line pattern or the like, can thicken the resist pattern regardless of the size of the resist pattern; which has excellent etching resistance; and which is suited for forming a fine space pattern or the like, exceeding the exposure limits. The present invention also provides a process for forming a resist pattern and a method for manufacturing a semiconductor device, wherein the resist pattern thickening material of the present invention is suitably utilized.

Abstract: A method and system for patterning a substrate using a dual-tone development process is described. The method and system comprise using a resist material having a polymer backbone with a plurality of protecting groups attached thereto to improve process latitude and critical dimension uniformity for the dual-tone development process.

Abstract: A semiconductor lithography process. A photoresist film is coated on a substrate. The photoresist film is subjected to a flood exposure to blanket expose the photoresist film across the substrate to a first radiation with a relatively lower dosage. The photoresist film is then subjected to a main exposure using a photomask to expose the photoresist film in a step and scan manner to a second radiation with a relatively higher dosage. After baking, the photoresist film is developed.

Abstract: A novel method for forming a pattern capable of decreasing the number of steps in a double patterning process, and a material for forming a coating film suitably used in the method for forming a pattern are provided. First resist film (2) is formed by applying a first chemically amplified resist composition on support (1), and thus formed film is selectively exposed, and developed to form multiple first resist patterns (3). Next, on the surface of the first resist patterns (3) are formed multiple coating patterns (5) by forming coating films (4) constituted with a water soluble resin film, respectively. Furthermore, a second chemically amplified resist composition is applied on the support (1) having the coating pattern (5) formed thereon to form second resist film (6), which is selectively exposed and developed to form multiple second resist patterns (7). Accordingly, a pattern including the coating patterns (5) and the second resist patterns (7) is formed on the support (1).

Abstract: A method of manufacturing a touch screen panel includes a first process, a second process, and a third process. Each of a plurality of first electrode serials includes a plurality of first electrode patterns which are separated from each other, neighboring first electrode patterns are electrically connected to each other via a first connection pattern, and a first insulation pattern electrically insulates the first electrode serial from the second electrode serial at an intersection of the first electrode serial and the second electrode serial.

Abstract: The invention can provide a method of processing a substrate using Double-Patterned-Shadow (D-P-S) processing sequences that can include (D-P-S) creation procedures, (D-P-S) evaluation procedures, and (D-P-S) transfer sequences. The (D-P-S) creation procedures can include deposition procedures, activation procedures, de-protecting procedures, sidewall angle (SWA) correction procedure, and Double Patterned (DP) developing procedures.

Abstract: A pattern formation method suitable for forming micro-patterns using electron beams (EB), X-rays, or extreme ultraviolet radiation (EUV) is provided.

Abstract: A pattern for a gate line is formed using a first photoresist pattern and a first BARC layer. A pad and patterns for a select line, which has a width that is larger than that of the gate line, are formed using a second photoresist pattern and a second BARC layer. The gate line, the pad and the select line can be formed at a same time.

Abstract: A method is disclosed for manufacturing a semiconductor device. The method includes: forming a substrate including a cell region and an outside region, wherein the outside region is adjacent to the cell region; forming a line-shaped pattern over the substrate using a first exposure mask so that the line-shaped spacer pattern extends from the cell region to the outside region; and patterning the line-shaped pattern in the cell region into a bar pattern while removing the line-shaped pattern in the outside region using a second exposure mask, wherein the line-shaped pattern can be formed using a spacer patterning technology (SPT) or a double pattern technology (DPT).

Abstract: Multi-tone resists can enhance the resolution limit of a lithographic process by advantageously using the changeable solubility of a resist composition as a function of lithographic radiation dosage. By imaging a multi-tone resist with different doses of lithographic radiation in a selected pattern, the pattern can be imparted to the resist upon subsequent development of the resist. In some aspects, a resist composition is utilized having an aliphatic polymer (e.g., a copolymer with fluoropolymer units and/or methacrylate units) with acid labile groups and a plurality of crosslinkable groups that can be crosslinked to other portions of the aliphatic polymer. Other components such as base generators and/or crosslinking agents can also be included. Such compositions can be useful in extending the resolution of UV lithographic radiation processes (e.g., wavelengths less than 200 nm). Other aspects of such compositions and methods are also discussed.

Abstract: A substrate treatment method including a first treatment process (S13 to S16) for exposing, heating, and developing a substrate on which a first resist is formed, thereby forming a first resist pattern, and a second treatment process (S17 to S20) for forming a second resist film on the substrate on which the first resist pattern is formed, exposing, heating, and developing the substrate on which the second resist film is formed, thereby forming a second resist pattern. Also, the substrate treatment method compensates a first treatment condition in a first treatment process (S22 to S25) based on a measured value of a line width of the second resist pattern and a second treatment condition in a second treatment process (S26 to S29) based on a measured value of a line width of the first resist pattern.

Abstract: A method is provided that enables the formation of multiple level plated products with large plating depth. A negative photoresist composition comprising (a) an alkali-soluble resin, (b) an acid generator, and (c) other components is used, and a plated product is formed by (A) a step of forming a layer of this negative photoresist composition, and then either heating or not heating, before conducting exposure; (B) a step of repeating the step (A) so that the step is performed a total of 2 or more times, thereby superimposing layers of the negative photoresist, and subsequently developing all of these layers simultaneously to form a multilayer resist pattern; and (C) a step of conducting plating treatment within this multilayer resist pattern.

Abstract: Disclosed is a developing method that performs a developing for forming a second resist pattern after forming and exposing a resist film on a surface of a substrate on which a first resist pattern is formed. The method includes a first process for developing the substrate for a first time period t1 in the state where the substrate stops, and a second process for developing the substrate for a second time period while rotating the substrate. The time ratio of first time period and second time period is adjusted so that a critical dimension of the first resist pattern is equal to a first predetermined value, and a total time of first time period and second time period is adjusted so that a critical dimension of the second resist pattern is equal to a second predetermined value.

Abstract: The present invention relates to a method of forming a micro pattern of a semiconductor device. According to an aspect of the present invention, a first photoresist layer and a second photoresist layer with different exposure types are formed over a semiconductor substrate on which an etch target layer is formed, performing an exposure process on the second photoresist layer and the first photoresist layer. Second photoresist patterns are formed by developing the second photoresist layer. First photoresist patterns are formed by etching the first photoresist layer using an etch process employing the second photoresist patterns as an etch mask. Auxiliary patterns are formed by developing the first photoresist patterns. The etch target layer is etched by employing the auxiliary patterns.

Abstract: The present invention provides a method for miniaturizing a pattern without seriously increasing the production cost or impairing the production efficiency. This invention also provides a fine resist pattern and a resist substrate-treating solution used for forming the fine pattern. The pattern formation method comprises a treatment step. In the treatment step, a resist pattern after development is treated with a resist substrate-treating solution containing an amino group-containing, preferably, a tertiary polyamine-containing water-soluble polymer, so as to reduce the effective size of the resist pattern formed by the development. The present invention also relates to a resist pattern formed by that method, and further relates to a treating solution used in the method.

Abstract: A method for forming a contact hole of a semiconductor device, includes forming a hard mask over an etch target layer, forming a first line pattern over the hard mask, forming a second line pattern over the hard mask and the first line pattern in a direction crossing the first line pattern, forming a mesh-type hard mask pattern by etching the hard mask using the first and second line patterns as etch barriers, and forming a contact hole by etching the etch target layer using the mesh-type hard mask pattern as an etch barrier.

Abstract: Provided is a manufacturing method of a semiconductor device, which is capable of realizing fine-pitch patterns and thus improving stabilization of patterning precision. The manufacturing method of the semiconductor device comprises forming a first photoresist pattern in a predetermined region on a substrate, depositing a thin film on the surface of the first photoresist pattern, and forming a second photoresist pattern in a region where the first photoresist pattern is not formed.

Abstract: A composition for removing a photoresist includes a) an amine compound having a cyclic amine and/or a diamine, b) a glycol ether compound, c) a corrosion inhibitor and d) a polar solvent. The composition further includes a stripping promoter. Further disclosed is a method of manufacturing an array substrate using the composition for removing a photoresist.

Abstract: A method (300) of texturing silicon surfaces (116) such to reduce reflectivity of a silicon wafer (110) for use in solar cells. The method (300) includes filling (330, 340) a vessel (122) with a volume of an etching solution (124) so as to cover the silicon surface 116) of a wafer or substrate (112). The etching solution (124) is made up of a catalytic nanomaterial (140) and an oxidant-etchant solution (146). The catalytic nanomaterial (140) may include gold or silver nanoparticles or noble metal nanoparticles, each of which may be a colloidal solution. The oxidant-etchant solution (146) includes an etching agent (142), such as hydrofluoric acid, and an oxidizing agent (144), such as hydrogen peroxide. Etching (350) is performed for a period of time including agitating or stirring the etching solution (124). The etch time may be selected such that the etched silicon surface (116) has a reflectivity of less than about 15 percent such as 1 to 10 percent in a 350 to 1000 nanometer wavelength range.

Abstract: An improved method of etching a structure and a structure etched by the method is disclosed. The bottom side of a leadframe of an IC-package is an example of a structure, which advantageously may be etched with the disclosed method. The method includes the steps of providing an etch mask to the substrate to be etched. The etch mask comprising at least two sub-mask: a first sub-mask covering the area which substantially should remain after the etching process, and a second sub-mask covering an area to be removed in the etching process. The second sub-mask is a sacrificial mask in the form of a grid. The presence of the second sub-mask increases the etching speed in the area covered by it.

Abstract: There are provided a method of forming a fine pattern employing self-aligned double patterning. The method includes providing a substrate. First mask patterns are formed on the substrate. A reactive layer is formed on the substrate having the first mask patterns. The reactive layer adjacent to the first mask patterns is reacted using a chemical attachment process, thereby forming sacrificial layers along outer walls of the first mask patterns. The reactive layer that is not reacted is removed to expose the sacrificial layers. Second mask patterns are formed between the sacrificial layers adjacent to sidewalls of the first mask patterns facing each other. The sacrificial layers are removed to expose the first and second mask patterns and the substrate exposed between the first and second mask patterns. The substrate is etched using the first and second mask patterns as an etching mask.

Abstract: Double patterning using a single reticle. A blading technique may be used to allow a single reticle to be used for double patterning. The reticle is placed into a lithographic apparatus and a first portion of the pattern is exposed onto a first photoresist overlaying a target region, while blading the second portion of the pattern. Then, a second portion of the pattern is exposed onto a second photoresist, while blading the first portion. Alternatively, each portion of the pattern may be exposed to the photoresist simultaneously, but to different target regions. Then shot coordinates are adjusted and the portions are exposed to a photoresist again to allow creation of the composite pattern in at least one of the target regions. During the double patterning process, the reticle may be kept in the lithographic apparatus.