Including Multiple Resist Image Formation Patents (Class 430/312)
  • Patent number: 10366889
    Abstract: A method of forming a semiconductor device includes the following steps. First of all, a material layer is formed on a substrate, and a sidewall image transferring process is performed to form plural first mask patterns on the material layer, with the first mask patterns parallel extended along a first direction. Next, a pattern splitting process is performed to remove a portion of the first mask patterns to form plural second openings, with the second openings parallel extended along a second direction, across the first mask patterns. Then, the material layer is patterned by using rest portions of the first mask patterns as a mask to form plural patterns arranged in an array.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Ching Chang
  • Patent number: 10361282
    Abstract: The present disclosure is directed to formation of a low-k spacer. For example, the present disclosure includes an exemplary method of forming the low-k spacer. The method includes depositing the low-k spacer and subsequently treating the low-k spacer with a plasma and/or a thermal anneal. The low-k spacer can be deposited on a structure protruding from the substrate. The plasma and/or thermal anneal treatment on the low-k spacer can reduce the etch rates of the spacer so that the spacer is etched less in subsequent etching or cleaning processes.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiu-Yu Kang, Hong-Wei Chen
  • Patent number: 10354873
    Abstract: Provided is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the DCS plasma treatment process, the atomic layer conformal deposition process, and the spacer etch mandrel pull process in order to meet the target final sidewall angle and other integration objecti
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: July 16, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Akiteru Ko, Angelique Raley, Sophie Thibaut, Satoru Nakamura, Nihar Mohanty
  • Patent number: 10312108
    Abstract: Methods for forming a semiconductor structure are provided. The method for forming a semiconductor structure includes forming a material layer over a substrate and forming a resist layer over the material layer. The method for forming a semiconductor structure further includes exposing the resist layer to form an exposed portion of the resist layer and forming a treating material layer over the exposed portion and an unexposed portion of the resist layer. In addition, a top surface of the exposed portion of the resist layer reacts with the treating material layer. The method for forming a semiconductor structure further includes removing the treating material layer and removing the unexposed portion of the resist layer to form an opening in the resist layer after the treating material is removed.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Po Yang, Chien-Wei Wang, Wei-Han Lai, Chin-Hsiang Lin
  • Patent number: 10256096
    Abstract: A semiconductor device and a method of forming the same are provided. An embodiment comprises a target layer and masking layers over the target layer. First openings are formed in the uppermost layer of the masking layers. Spacers are formed along sidewalls of the first openings, remaining first openings having a first pattern. Second openings are formed in the uppermost layer of the masking layers, the second openings having a second pattern. The first pattern and the second pattern are partially transferred to the target layer.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: April 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Patent number: 10204911
    Abstract: A method for fabricating a capacitor includes providing a substrate and a first etching stop layer on the substrate; forming a plurality of first spacers on the first etching stop layer; forming an organic layer and a second etching stop layer sequentially on the first spacers, the organic layer covering the first spacers; forming a plurality of second spacers on the second etching stop layer, each second spacer crossing the first spacers; transferring a pattern of the second spacers to the organic layer to form an organic pattern; performing an etching process using the organic pattern and the first spacers as a mask to form an etching stop pattern and remove the second etching stop layer; transferring the etching stop pattern to the substrate to form a plurality of through holes.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: February 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10175575
    Abstract: A pattern-forming method includes forming a base pattern including a first polymer on a front face side. A composition is applied on at least a lateral face of the base pattern. The composition includes at least one polymer that is capable of interacting with the first polymer. The composition is heated such that a portion of the at least one polymer interacts with the first polymer and that a coating film is formed on the lateral face of the base pattern. Another portion of the at least one polymer not having interacted with the first polymer is removed to form a resist pattern. The base pattern in a planar view has a shape with a long axis and a short axis, and a ratio of lengths of the long axis to the short axis is no less than 1.5 and no greater than 10.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: January 8, 2019
    Assignee: JSR CORPORATION
    Inventor: Hitoshi Osaki
  • Patent number: 10147805
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure over a semiconductor substrate. The semiconductor device structure also includes a second fin structure over the semiconductor substrate. The second fin structure has a lower height than that of the first fin structure. The second fin structure includes a first sidewall and a second sidewall, and the first sidewall and the second sidewall surround a recess over the second fin structure.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: December 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Lung Chen, Kang-Min Kuo, Wen-Hsin Chan
  • Patent number: 9921474
    Abstract: A pattern-forming method includes forming a prepattern that is insoluble or hardly soluble in an organic solvent. A resin layer is provided on at least a lateral face of the prepattern. The prepattern and the resin layer are heated such that an adjacent portion of the resin layer to the prepattern is made insoluble or hardly soluble in the organic solvent, without being accompanied by an increase of a molecular weight of the prepattern and the resin layer. A portion of the resin layer other than the adjacent portion of the resin layer is removed. The resin layer is formed from a first composition including a first polymer and an organic solvent. Solubility of the first polymer in the organic solvent does not substantially change due to an action of an acid. A weight average molecular weight of the first polymer is 15,000-150,000.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: March 20, 2018
    Assignee: JSR CORPORATION
    Inventor: Kanako Fukami
  • Patent number: 9823530
    Abstract: An electro-optical apparatus includes a semiconductor layer which is provided on a first substrate, a gate electrode which is provided on the semiconductor layer, a first light-shielding member which is provided between the semiconductor layer and the first substrate, a second light-shielding member which is provided in an extension direction of the first substrate in the semiconductor layer, and a third light-shielding member which is provided on an opposite side to the first substrate in the semiconductor layer, in which the second light-shielding member is embedded within a groove which is formed between the first light-shielding member and the third light-shielding member, and the third light-shielding member is electrically connected to the gate electrode and the first light-shielding member via the second light-shielding member.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: November 21, 2017
    Assignee: Seiko Epson Corporation
    Inventor: Yohei Sugimoto
  • Patent number: 9798227
    Abstract: A photomask layout includes: a substrate region; a lower stepped region at a region of the substrate region; and a pattern region at least partially crossing the lower stepped region and including at least one notch portion at an area overlapping the lower stepped region. A method of forming a pattern is also provided.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 24, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Man-Jong Yu
  • Patent number: 9679803
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a semiconductor structure including a substrate, a dielectric layer formed over the substrate, and a hard mask region formed over the dielectric layer; forming a first photoresist layer over the hard mask region; performing a first lithography exposure using a photomask to form a first latent pattern; forming a second photoresist layer over the hard mask region; and performing a second lithography exposure using the photomask to form a second latent pattern. The photomask includes a first mask feature and a second mask feature. The first latent pattern corresponds to the first mask feature, and the second latent pattern corresponds to the first mask feature and the second mask feature.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Chih-Tsung Shih, Yen-Cheng Lu
  • Patent number: 9671641
    Abstract: A color filter substrate used in a display and the method thereby, and the photo mask of the color filter substrate are disclosed. The color filter substrate comprises a main body and a plurality color resist patterns on the main body. The adjacent color resist patterns partially overlap wherein in the overlapping region, the thickness of bottom color resist pattern is gradually thinning in its edge direction. Through the above way, the horn section in the overlapping region of the adjacent RGB color resist patterns of the color filter substrate is reduced. The performance of the liquid crystals is improved. Moreover, the OC flat layer does not need to be built on RGB the color resist pattern. The production cost of the liquid crystal display device is reduced and the productivity is improved.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 6, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Feng Zhao
  • Patent number: 9583343
    Abstract: A method of forming a non-continuous line pattern includes forming a DSA material layer on a substrate, performing a phase separation of the DSA material layer to form an ordered periodic pattern including a plurality of first polymer structures and the second polymer structures arranged alternately, forming a first mask to cover a first portion of the ordered periodic pattern, performing a first etching process to remove a portion of the first polymer structures exposed by the first mask, removing the first mask, forming a second mask to cover a second portion of the ordered periodic pattern, with an interval to the first portion of the ordered periodic pattern, performing a second etching process to remove a portion of the second polymer structures exposed by the second mask, and removing the second mask. The remaining first polymer structures and the remaining second polymer structures are not connected to each other.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: February 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Te Chen, En-Chiuan Liou, Chia-Hsun Tseng, Shin-Feng Su, Yu-Ting Hung, Meng-Lin Tsai
  • Patent number: 9519211
    Abstract: The present invention provides a halftone mask comprising an assist pattern and a manufacturing method of the halftone mask, which uses an ArF excimer laser as an exposing source, is used for a projection exposure by an off axis illumination, does not resolve the assist pattern while keeping the focal depth magnification effect as the assist pattern, and may form a transferred image having high contrast of a main pattern.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: December 13, 2016
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Takaharu Nagai, Hiroshi Mohri, Yasutaka Morikawa, Katsuya Hayano
  • Patent number: 9502365
    Abstract: An integrated circuit and method with a delamination free opening formed through multiple levels of polymer dielectric. The opening has a vertical sidewall and no interface between adjacent levels of polymer dielectric is exposed on the vertical sidewall.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: November 22, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Licheng Marshal Han, Michael Andrew Serafin, Byron Williams, Sandra Rodriguez Varela, Salvatore Pavone
  • Patent number: 9490136
    Abstract: A method includes forming a hard mask (HM) stack over a material layer, which has a first, second, third and fourth HM layers. The method also includes forming a first trench in the fourth HM layer, forming a first spacer in the first trench, forming a second trench in the fourth HM layer, removing at least a portion of the first spacer to form a cut by using the third HM layer as an etch-stop layer, removing a portion of the third HM layer and the second HM layer exposed by the first trench, second trench, and cut to form an extended first trench, extended second trench, and extended cut, respectively. The method also includes forming second spacers in the extended first trench, the extended second trench, and the extended cut and removing another portion of the second HM layer to form a third trench.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Chang, Chia-Tien Wu, Yung-Hsu Wu
  • Patent number: 9472653
    Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: October 18, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Hyuk Kim, Kang-Ill Seo, Hyun-Jae Kang, Deok-Han Bae
  • Patent number: 9360758
    Abstract: In accordance with an embodiment, a method of filtering a process fluid such as a negative tone developer is provided. The negative tone developer is introduced to a filter membrane that comprises a fluorine-based polymer. The negative tone developer is then filtered through the filter membrane. By using these materials and methods, polyethylene from the filter membrane will not contaminate the photoresist during development and reduce defects that arise from polyethylene contamination.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Hsin Lo, Ching-Yu Chang
  • Patent number: 9341940
    Abstract: A reticle and a method of fabricating the reticle are provided. In various embodiments, the reticle includes a substrate, a patterned first attenuating layer, a patterned second attenuating layer, and a patterned third attenuating layer. The patterned first attenuating layer is disposed on the substrate. The patterned second attenuating layer is disposed on the patterned first attenuating layer. The patterned third attenuating layer is disposed on the patterned second attenuating layer. A first part of the patterned first attenuating layer, a first part of patterned second attenuating layer, and the patterned third attenuating layer are stacked on the substrate as a binary intensity mask portion.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 17, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chang Hsueh, Chia-Jen Chen, Ta-Cheng Lien, Hsin-Chang Lee
  • Patent number: 9311439
    Abstract: Provided are methods of forming patterns of wafers using self-aligned double patterning processes. The methods include preparing an initial layout having a first design pattern, a second design pattern, and a third design pattern disposed between the first design pattern and the second design pattern, extracting a first sub-layout including the first design pattern and a second sub-layout including the second design pattern from the initial layout using a computer, forming a first modified sub-layout including a first modified design pattern obtained by modifying the first design pattern of the first sub-layout using the computer, generating a modified layout including the first modified sub-layout and the second sub-layout using the computer, and performing a double patterning process using the modified layout.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Moon-Gyu Jeong
  • Patent number: 9219178
    Abstract: A method of fabrication of a collimator structure on a detector that includes applying a first layer of resist to a semiconductor sensor, applying a second layer of resist over the first layer of resist and the semiconductor sensor to cover both the first layer of resist and the semiconductor sensor, exposing the second layer of resist to ultraviolet (UV) light with a photomask to transfer a pattern from the photomask to the second layer of resist, removing portions of the second layer of resist corresponding to the pattern from the photomask to produce openings in the second layer of resist, which expose upper portions of the semiconductor sensor, and depositing a layer of metal in the openings and on the second layer of resist to cover the openings, the first layer of resist, the second layer of resist, and the semiconductor sensor.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: December 22, 2015
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEDICAL SYSTEMS CORPORATION
    Inventors: Yuexing Zhang, Daniel Gagnon, Xiaolan Wang
  • Patent number: 9197183
    Abstract: The invention relates to a method of fabricating a single-piece micromechanical component including at least two distinct functional levels. According to the invention, the method includes a LIGA process on a single level combined with the machining of the LIGA deposition directly on the substrate.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: November 24, 2015
    Assignee: Nivarox-FAR S.A.
    Inventors: Alexandre Fussinger, Marc Stranczl
  • Patent number: 9177825
    Abstract: According to one embodiment, a pattern forming method includes forming, on an underlying region, a neutral film having an affinity for first and second polymers, forming a first pinning part having an affinity for the first polymer by irradiating a first region of the neutral film with an energy beam, forming, on the neutral film including the first pinning part, a block copolymer film containing the first and second polymers, and performing a predetermined treatment for the block copolymer film to perform a microphase separation.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: November 3, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yuriko Seino
  • Patent number: 9134610
    Abstract: An underlayer coating is used as an underlayer of photoresists in lithography process of the manufacture of semiconductor devices and has a high dry etching rate in comparison to the photoresists, does not intermix with the photoresists, and is capable of flattening the surface of a semiconductor substrate having holes of a high aspect ratio; and an underlayer coating forming composition can form the underlayer coating. The underlayer coating forming composition for forming by light irradiation an underlayer coating used as an underlayer of a photoresist in a lithography process of the manufacture of semiconductor devices, includes a polymerizable substance and a photopolymerization initiator.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: September 15, 2015
    Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Satoshi Takei, Tetsuya Shinjo, Motohiko Hidaka
  • Patent number: 9097975
    Abstract: A method of manufacturing using a double patterning method is provided. The double patterning method uses a first developer and a second developer that are different. For example, the first developer may be a positive tone developer for a positive photoresist while the second developer may be a negative tone developer for the positive photoresist. Photoresists having a photoactive compound are also provided that may be useful in double patterning methods. The resulting double patterning results, wherein a dimension of a variable first dense pattern is larger than a dimension of a variable second dense pattern.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: August 4, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Chin Cheng Yang
  • Publication number: 20150140482
    Abstract: A pattern forming method includes: (a) forming a first film on a substrate using an actinic ray-sensitive or radiation-sensitive resin composition (I) containing a resin of which solubility in a developer containing an organic solvent decreases due to polarity increased by an action of an acid; (b) exposing the first film; (c) developing the exposed first film using a developer containing an organic solvent to form a first negative pattern; (e) forming a second film on the substrate using an actinic ray-sensitive or radiation-sensitive resin composition (II) containing a resin of which solubility in a developer containing an organic solvent decreases due to polarity increased by an action of an acid; (f) exposing the second film; and (g) developing the exposed second film using a developer containing an organic solvent to form a second negative pattern in this order.
    Type: Application
    Filed: January 27, 2015
    Publication date: May 21, 2015
    Applicant: FUJIFILM CORPORATION
    Inventors: Tsukasa YAMANAKA, Naoya IGUCHI, Ryosuke UEBA, Kei YAMAMOTO
  • Patent number: 9029067
    Abstract: A resist pattern-insolubilizing resin composition is used in a resist pattern-forming method. The resist pattern-insolubilizing resin composition includes solvent and a resin. The resin includes a first repeating unit that includes a hydroxyl group in its side chain and at least one of a second repeating unit derived from a monomer shown by a following formula (1-1) and a third repeating unit derived from a monomer shown by a following formula (1-2), wherein for example, R1 represents a hydrogen atom, A represents a methylene group, R2 represents a group shown by a following formula (2-1) or a group shown by a following formula (2-2), R3 represents a methylene group, R4 represents a hydrogen atom, and n is 0 or 1, wherein each of R34 represents at least one of a hydrogen atom and a linear or branched alkyl group having 1 to 10 carbon atoms.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: May 12, 2015
    Assignee: JSR Corporation
    Inventors: Gouji Wakamatsu, Masafumi Hori, Kouichi Fujiwara, Makoto Sugiura
  • Patent number: 9017928
    Abstract: A resin structure for the formation of a micro-structure is manufactured by (A) applying a composition comprising a polymer, a photoacid generator, an epoxy compound, and an organic solvent onto a substrate, (B) heating the composition to form a sacrificial film, (C) exposing imagewise the film to first high-energy radiation, (D) developing the film in an alkaline developer to form a sacrificial film pattern, (E) exposing the sacrificial film pattern to UV as second high-energy radiation, and (F) heating the substrate at 80-250° C. The exposure dose of first high-energy radiation in step (C) is up to 250 mJ/cm2. At the end of step (F), the sacrificial film has a sidewall angle of 80°-90° relative to the substrate.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: April 28, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Yoshinori Hirano, Masashi Iio, Hideyoshi Yanagisawa
  • Patent number: 9005875
    Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Paul A. Nyhus, Charles H. Wallace
  • Patent number: 8993218
    Abstract: One or more techniques or systems for controlling a profile for photo resist (PR) are provided herein. In some embodiments, a first shield layer is formed on a first PR layer and a second PR layer is formed on the first shield layer. A first window is formed within the second PR layer during a first exposure with a mask. A second window is formed within the first shield layer based on the first window. A third window is formed within the first PR layer during a second exposure without a mask. Because, the third window is formed while the first shield layer and the second PR layer are on the first PR layer, a profile associated with the first PR layer is controlled. Contamination during ion bombardment is mitigated due to the controlled profile.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Li Huai Yang, Chien-Mao Chen
  • Patent number: 8993217
    Abstract: Innovative techniques are disclosed for fabricating microelectronic devices using an alternating phase shift mask. Some embodiments of the invention encompass a double exposure technique that utilize high resolution line patterning such that two opaque lines intersect at an angle. After development, substantially circular images may be formed. In certain embodiments, high resolution disk imaging as small as 60 nm is possible.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: March 31, 2015
    Assignee: Western Digital (Fremont), LLC
    Inventors: Ling Wang, Dujiang Wan, Miao Wang, Hai Sun
  • Publication number: 20150079424
    Abstract: A substrate for suspension comprises a metallic substrate, an insulating layer formed on the metallic substrate, a conductor layer formed on the insulating layer, and a cover layer covering the conductor layer. The insulating layer and the cover layer are formed from different materials, whose coefficients of hygroscopic expansion are in the range between 3×10?6/% RH and 30×10?6/% RH. The difference between the coefficients of hygroscopic expansion of the two materials is 5×10?6/% RH or less.
    Type: Application
    Filed: November 24, 2014
    Publication date: March 19, 2015
    Inventors: Yoichi HITOMI, Shinji KUMON, Terutoshi MOMOSE, Katsuya SAKAYORI, Kiyohiro TAKACHI, Yoichi MIURA, Tsuyoshi YAMAZAKI
  • Publication number: 20150053456
    Abstract: A printed circuit board and a manufacturing method thereof. The manufacturing method of the printed circuit board includes: coating a first solder resist on an upper surface of a substrate having a circuit pattern formed thereon; removing the first solder resist in the remaining portion except a first specific area by performing primary development after exposing the substrate coated with the first solder resist; coating a second solder resist, which has different properties from the first solder resist, on the upper surface of the substrate having the first solder resist remaining in the first specific area; and removing the second solder resist in the remaining portion except a second specific area by performing secondary development after exposing the substrate coated with the second solder resist.
    Type: Application
    Filed: December 19, 2013
    Publication date: February 26, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: CHANG BO LEE, MYEONG HO HONG, DAE JO HONG, YOUNG KYU LIM
  • Patent number: 8956886
    Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: February 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Samer Banna, Olivier Joubert, Lei Lian, Maxime Darnon, Nicolas Posseme, Laurent Vallier
  • Publication number: 20150041303
    Abstract: Disclosed are a novel ITO crossover integrated capacitive touch screen and a manufacturing method thereof. The novel ITO crossover integrated capacitive touch screen comprises a transparent substrate, and a silicon dioxide layer, a niobium pentoxide layer, a black resin layer, an ITO crossover electrode, a first insulation layer, an ITO electrode, a metal electrode, and a second insulation layer sequentially stacked on the transparent substrate. The silicon dioxide layer covers the glass completely, and the niobium pentoxide layer covers the silicon dioxide layer completely. The ITO electrode comprises a capacitive screen driver and a sensing electrode, and is provided with a patterned graphic structure. The capacitive screen driver and the sensing electrode are on the same layer, mutually independent, mutually insulated, and vertical in design.
    Type: Application
    Filed: March 14, 2013
    Publication date: February 12, 2015
    Inventor: Xiaoxing Cao
  • Patent number: 8945800
    Abstract: In a multiple patterning techniques, where two or more exposures are used to form a single layer of a device, the splitting of features in a single layer between the multiple exposures is carried out additionally with reference to features of another associated layer and the splitting of that layer into two or more sets of features for separate exposure. The multiple exposure process can be a process involving repeated litho-etch steps desirably, the alignment scheme utilized during exposure of the split layers is optimized with reference to the splitting approach.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: February 3, 2015
    Assignee: ASML Netherlands B.V.
    Inventors: Tsann-Bim Chiou, Mircea Dusa, Alek Chi-Heng Chen
  • Patent number: 8921233
    Abstract: Some embodiments provide microelectronic fabrication methods in which a sacrificial pattern is formed on a substrate. A spacer formation layer is formed on the substrate, the spacer formation layer covering the sacrificial pattern. The spacer formation layer is etched to expose an upper surface of the sacrificial pattern and to leave at least one spacer on at least one sidewall of the sacrificial pattern. A first portion of the sacrificial pattern having a first width is removed while leaving intact a second portion of the sacrificial pattern having a second width greater than the first width to thereby form a composite mask pattern including the at least one spacer and a portion of the sacrificial layer. An underlying portion of the substrate is etched using the composite mask pattern as an etching mask.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hwang Sim, Min-chul Kim
  • Patent number: 8912097
    Abstract: A method of patterning a substrate comprises providing an array of resist features defined by a first pitch and a first gap width between adjacent resist features. Particles are introduced into the array of resist features, wherein the array of resist features becomes hardened. The introduction of particles may cause a reduction in critical dimension of the resist features. Sidewalls are provided on side portions of hardened resist features. Subsequent to the formation of the sidewalls, the hardened resist features are removed, leaving an array of isolated sidewalls disposed on the substrate. The sidewall array provides a mask for double patterning of features in the substrate layers disposed below the sidewalls, wherein an array of features formed in the substrate has a second pitch equal to half that of the first pitch.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: December 16, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Patrick M. Martin, Steven Carlson, Choong-Young Oh, Jung-Wook Park
  • Patent number: 8895231
    Abstract: A pattern is formed by coating a first positive resist composition comprising a base resin, a photoacid generator, and a base generator having both a 9-fluorenylmethyloxycarbonyl-substituted amino group and a carboxyl group onto a substrate to form a first resist film, patternwise exposure, PEB, and development to form a first resist pattern, heating the first resist pattern for causing the base generator to generate a base for inactivating the pattern to acid, coating a second positive resist composition comprising an alcohol and an optional ether onto the first resist pattern-bearing substrate to form a second resist film, patternwise exposure, PEB, and development to form a second resist pattern.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: November 25, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Jun Hatakeyama, Kazuhiro Katayama
  • Patent number: 8881353
    Abstract: Provided is a method of producing a piezoelectric/electrorestrictive film type device including a vibrating laminate obtained by laminating electrode films and piezoelectric/electrorestrictive films on a substrate containing a cavity. The method of producing the vibrating laminate includes: producing the substrate with a cavity, forming the first photoresist film on first principal surface of substrate, irradiating substrate from the second principal surface side of the substrate, transferring the plane shape of the cavity to the first photoresist film, developing and removing the first photoresist film formed in the region where the shape of cavity was formed, forming a lowermost electrode film by plating, and forming additional films other than the lowermost electrode film constituting the vibrating laminate.
    Type: Grant
    Filed: September 6, 2010
    Date of Patent: November 11, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Hideki Shimizu, Mutsumi Kitagawa
  • Patent number: 8877429
    Abstract: A resist pattern-insolubilizing resin composition is used in a resist pattern-forming method. The resist pattern-insolubilizing resin composition includes solvent and a resin. The resin includes a first repeating unit that includes a hydroxyl group in its side chain and at least one of a second repeating unit derived from a monomer shown by a following formula (1-1) and a third repeating unit derived from a monomer shown by a following formula (1-2), wherein for example, R1 represents a hydrogen atom, A represents a methylene group, R2 represents a group shown by a following formula (2-1) or a group shown by a following formula (2-2), R3 represents a methylene group, R4 represents a hydrogen atom, and n is 0 or 1, wherein each of R34 represents at least one of a hydrogen atom and a linear or branched alkyl group having 1 to 10 carbon atoms.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: November 4, 2014
    Assignee: JSR Corporation
    Inventors: Gouji Wakamatsu, Masafumi Hori, Kouichi Fujiwara, Makoto Sugiura
  • Patent number: 8859187
    Abstract: A novel method of forming a resist pattern in which thickness loss from the resist pattern is reduced, and a negative resist composition that can be used in this method of forming a resist pattern. The method of forming a resist pattern includes: forming a first resist film by applying a first resist composition to a support, forming a first resist pattern by selectively exposing the first resist film through a first mask pattern and then developing the first resist film, forming a second resist film by applying a negative resist composition containing an ether-based organic solvent (S?) having no hydroxyl groups onto the support having the first resist pattern formed thereon, and forming a resist pattern by selectively exposing the second resist film through a second mask pattern and then developing the second resist film.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: October 14, 2014
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Ken Tanaka, Sho Abe, Shigeru Yokoi
  • Patent number: 8852491
    Abstract: In a method of manufacturing an electroforming mold, a first photoresist layer is formed on an upper surface of a bottom conductive film of a substrate, and the first photoresist layer is divided into a first soluble portion and a first insoluble portion. A conductive material is thermally deposited on an upper surface of the first photoresist layer within a predetermined temperature range, to thereby form an intermediate conductive film. An intermediate conductive film is patterned. A second photoresist layer is formed on an exposed upper surface of the first photoresist layer after the intermediate conductive film is removed, and on an upper surface of the intermediate conductive film remaining after patterning. The second photoresist layer is divided into a second soluble portion and a second insoluble portion. Next, the first and second photoresist layers are developed, and the first and second soluble portions are removed.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: October 7, 2014
    Assignee: Seiko Instruments Inc.
    Inventors: Takashi Niwa, Matsuo Kishi, Koichiro Jujo, Hiroyuki Hoshina
  • Patent number: 8852830
    Abstract: A photomask for exposing a region on a substrate, with a mask pattern, including a first line pattern, a second line pattern, a first connection pattern for a peripheral portion of the region and a second connection pattern for the peripheral portion, wherein the first connection pattern is wider than the first line pattern and the second connection pattern is wider than the second line pattern, a distance from a virtual line between the first line pattern and the second line pattern to a center line of the first connection pattern is larger than a distance from the virtual line to a center line of the first line pattern and a distance from the virtual line to a center line of the second connection pattern is larger than a distance from the virtual line to a center line of the second line pattern.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: October 7, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoshi Hirayama, Atsushi Kanome
  • Publication number: 20140272714
    Abstract: A method of lithography patterning includes forming a first resist pattern on a substrate, wherein the first resist pattern including a plurality of openings. A second resist pattern is formed on the substrate and within the plurality of openings of the first resist pattern, wherein the second resist pattern includes at least one opening therein on the substrate. The first resist pattern is removed to uncover the substrate underlying the first resist pattern.
    Type: Application
    Filed: June 3, 2014
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: CHUN-KUANG CHEN, Hsiao-Wei Yeh, Chih-An Lin, Chien-Wei Wang, Feng-Cheng Hsu
  • Patent number: 8835100
    Abstract: A method of manufacturing using a double patterning method is provided. The double patterning method uses a first developer and a second developer that are different. For example, the first developer may be a positive tone developer for a positive photoresist while the second developer may be a negative tone developer for the positive photoresist. Photoresists having a photoactive compound are also provided that may be useful in double patterning methods.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 16, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Chin Cheng Yang
  • Patent number: 8835083
    Abstract: A manufacturing method of a photomask by which a resist pattern corresponding to a pattern with designed values can be formed, a method for optical proximity correction, and a manufacturing method of a semiconductor device are provided. Proximity design features that are close to each other and estimated to violate a mask rule check are extracted. In the proximity design features, correction prohibited regions where optical proximity correction is not carried out are set based on the distance between the features obtained from the extracted proximity design features and the resolution of an exposure device. Optical proximity correction is carried out on the proximity design features with the correction prohibited regions excluded to obtain corrected proximity patterns. A predetermined mask material is patterned by carrying out electron beam lithography based on the corrected proximity pattern data.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: September 16, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Ayumi Minamide, Akemi Moniwa, Akira Imai
  • Patent number: 8822137
    Abstract: An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qinghuang Lin, Sanjay Mehta, Hosadurga Shobha
  • Patent number: 8815473
    Abstract: Techniques for reducing the number of shots required by a radiation beam writing tool to write a pattern, such as fractured layout design, onto a substrate. One or more apertures are employed by a radiation beam writing tool to write a desired pattern onto a substrate using L-shaped images, T-shaped images, or some combination of both. By reducing the number of shots required to write a pattern onto a substrate, various implementations of the invention may reduce the write time and/or write complexity of the write process.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: August 26, 2014
    Inventors: Emile Y. Sahouria, Steffen F. Schulze