Abstract: Embodiments of the present disclosure provide a quantum dot light emitting device, a preparation method thereof and a quantum dot display panel, the method includes: forming a first function layer; forming a first sacrificial layer and a first photoresist layer; patterning the first photoresist layer; patterning the first sacrificial layer, the first function layer includes a first part and a second part, and the first sacrificial layer pattern and the first photoresist pattern are stacked on the first part, the second part is exposed by the first sacrificial layer pattern and the first photoresist pattern; forming a first quantum dot material layer; stripping the first sacrificial layer pattern to remove the first sacrificial layer pattern, the first photoresist pattern and the first quantum dot material layer on the first sacrificial layer pattern, retaining the first quantum dot material layer on the second part of the first function layer.

Abstract: A display device includes a substrate including pixels; a buffer layer disposed on the substrate; an etch stopper layer disposed between the substrate and the buffer layer; and at least one penetrating-hole penetrating the substrate, the buffer layer, and the etch stopper layer, wherein the etch stopper layer includes amorphous carbon.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

Abstract: A method for structuring a substrate is specified, in particular structuring by means of selective etching in the semiconductor and IC substrate industry, in which the following steps are carried out: providing a substrate, applying a titanium seed layer, full-area coating with a photoresist layer, lithographic structuring of the photoresist layer, in order to expose regions of the titanium seed layer, selectively depositing copper as conductor tracks in those areas in which the titanium seed layer is exposed, removing the structured photoresist, and etching the titanium seed layer in the areas previously covered by the structured photoresist, wherein phosphoric acid is used to etch the titanium seed layer and, in addition, exposure to UV light is carried out during the etching of the titanium.

Abstract: Embodiments are directed to the formation of buckling beam probe arrays having MEMS probes that are engaged with guide plates during formation or after formation of the probes while the probes are held in the array configuration in which they were formed. In other embodiments, probes may be formed in, or laterally aligned with, guide plate through holes. Guide plate engagement may occur by longitudinally locating guide plates on probes that are partially formed or fully formed with exposed ends, by forming probes within guide plate through holes, by forming guide plates around probes, or forming guide plates in lateral alignment with arrayed probes and then longitudinally engaging the probes and the through holes of the guide plates. Final arrays may include probes and a substrate to which the probes are bonded along with one or more guide plates while in other embodiments final arrays may include probes held by a plurality of guide plates (e.g.

Abstract: A method for planarizing a substrate includes: receiving a substrate having microfabricated structures that differ in height across the working surface of the substrate that define a non-planar topography, depositing a first layer that includes a solubility-shifting agent on the working surface of the substrate by spin-on deposition in a non-planar fashion, exposing the first layer to a first pattern of actinic radiation based on the topography, developing the first layer using a predetermined solvent, and depositing a second layer over the working surface of the substrate that has a greater planarity as compared to the first layer prior to developing the first layer. The first pattern of radiation changes a solubility of the first layer such that upper regions of the non-planar topography of the first layer are soluble to the predetermined solvent.

Abstract: A method of manufacturing a fine pattern using the following steps of: (1) coating a resist composition containing a novolak resin having an alkali dissolution rate of 100 to 3,000 ? on a substrate to form a resist composition layer; (2) subjecting said resist composition layer to exposure; (3) developing said resist composition layer to form a resist pattern; (4) subjecting said resist pattern to flood exposure; (5) coating a fine pattern forming composition on the surface of said resist pattern to form a fine pattern forming composition layer; (6) heating said resist pattern and said fine pattern forming composition layer to cure the regions of said fine pattern forming composition layer in the vicinity of said resist pattern and to form an insolubilized layer; and (7) removing uncured regions of said fine pattern forming composition layer.

Abstract: A method for forming a semiconductor structure includes forming a hard mask layer over a target layer. The method also includes forming first mandrels over the hard mask layer. The method also includes forming a first opening in the first mandrels. The method also includes depositing a spacer layer over the hard mask layer and the first mandrels. The method also includes depositing a second mandrel material over the spacer layer. The method also includes planarizing the second mandrel material. The method also includes forming a second opening in the second mandrel material. The method also includes patterning and etching the second mandrel material to form second mandrels. The method also includes etching the spacer layer. The method also includes etching the hard mask layer and the target layer.

Abstract: The present disclosure provides a touch display device including: a plurality of emitting elements; an adhesive layer over the emitting elements; a first touch electrode and a second touch electrode over the adhesive layer and in an active area; a pad electrode over the adhesive layer and in a touch pad region; and a protection layer over the first touch electrode, the second touch electrode and the pad electrode, wherein the first and second touch electrode are insulated by an insulating layer, and the protection layer includes at least one contact hole corresponding to the pad electrode, and wherein the pad electrode includes a plurality of electrode layers, and one of the plurality of electrode layers extends from the first touch electrode or the second touch electrode.

Abstract: The present invention relates to a structure for a quantum dot barrier rib and a process for preparing the same. The structure for a quantum dot barrier rib of the present invention comprises a cured film having a uniform film thickness and an appropriate range of film thickness. Here, the reflectance RSCI measured by the SCI (specular component included) method and the reflectance RSCE measured by the SCE (specular component excluded) method are reduced, and the ratio between them (RSCE/RSCI) is appropriately adjusted, so that it is possible to satisfy such characteristics as high light-shielding property and low reflectance at the same time while the resolution and pattern characteristics are maintained to be excellent. In addition, when the structure for a quantum dot barrier rib is prepared, it is possible to form a multilayer pattern having a uniform film thickness suitable for the quantum dot barrier ribs in a single development process. Thus, it can be advantageously used for a quantum dot display.

Abstract: A method of manufacturing a semiconductor device includes: forming one or more transistor cells in a first region of a semiconductor substrate, the semiconductor substrate having a second region that is devoid of transistor cells; forming a first dielectric material over the first and second regions; forming a second dielectric material over the first dielectric material; forming a pn diode in the first dielectric material over the second region; etching first contact grooves into a p-type region of the pn diode, second contact grooves into an n-type region of the pn diode, and third contact grooves into the first region of the semiconductor substrate at the same time using a common contact formation process; and filling the first contact grooves, the second contact grooves and the third contact grooves with an electrically conductive material.

Abstract: A method of manufacturing a conductive wire structure including following steps is provided. A conductive layer is formed on a substrate. A rectangular ring spacer is formed on the conductive layer by a self-aligned double patterning process. A patterned photoresist layer is formed. The patterned photoresist layer exposes a first portion and a second portion of the rectangular ring spacer. The first and second portions are located at two corners on a diagonal of the rectangular ring spacer. The first and second portions are removed by using the patterned photoresist layer as a mask to form a first spacer and a second spacer. The first spacer and the second spacer are L-shaped. The patterned photoresist layer is removed. A pattern of the first spacer and a pattern of the second spacer are transferred to the conductive layer to form an L-shaped first conductive wire and an L-shaped second conductive wire.

Abstract: Provided is a display device and an electronic apparatus that prevent the occurrence of failure in the connection between a mounting substrate and an electronic component. The display device includes an interconnection layer provided on a support substrate, a plurality of insulating layers provided above the interconnection layer, an opening provided in parts of the insulating layers, and a metal layer electrically connected to the interconnection layer and filling the opening up to a height below a layer surface of the insulating layer.

Abstract: A reflection mode photomask includes a substrate. The reflection mode photomask further includes a reflective multilayer over the substrate. The reflection mode photomask further includes a plurality of absorber stacks over the reflective multilayer, wherein each absorber stack of the plurality of absorber stacks has an etch stop layer, an absorber layer and an ARC layer, wherein a ratio of a thickness of the ARC layer to that of the etch stop layer is in a range from about 1:1 to about 1:2.5, and a sidewall roughness of each absorber stack of the plurality of absorber stacks is smaller than 3 nanometers (nm).

Abstract: In a decorative sheet, a base material has a concave portion on a front face. The concave portion includes a bottom surface. The bottom surface includes a first surface, a second surface and a third surface. A depth dimension of the first surface is a first value. The depth dimension is a dimension from the front face of the base material along a thickness direction of the base material. The depth dimension of the second surface is a second value which is smaller than the first value. The third surface is a surface which is connected with the first surface at a back side of the thickness direction, and is connected with the second surface at a front side of the thickness direction.

Abstract: Embodiments of the present disclosure relate to methods for positioning masks in a propagation direction of a light source. The masks correspond to a pattern to be written into a photoresist layer of a substrate. The masks are positioned by stitching a first mask and a second mask. The first mask includes a set of first features having first feature extensions extending therefrom at first feature interfaces. The second mask includes a set of second features having second feature extensions extending therefrom at second feature interfaces. Each first feature extension stitches with each corresponding second feature extension to form each stitched portion of a first stitched portion of the first pair of masks. The stitched portion of the first pair of masks defines a portion of the pattern to be written into the photoresist layer.

Abstract: A manufacturing method of a proton battery and a proton battery module are provided. The manufacturing method of the proton battery includes the steps of providing a positive electrode, a negative electrode, and a polymer exchange membrane, and assembling the positive electrode, the negative electrode, and the polymer exchange membrane, in which the polymer exchange membrane is interposed between the positive electrode and the negative electrode. The step of providing the negative electrode at least includes forming a carbon layer on a substrate, and performing a polarization process on the carbon layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure, and forming a mask layer covering the dummy fin structure. The method also includes removing a portion of the mask layer and a top portion of the dummy fin structure by a first etching operation to form an etched mask layer, wherein the dummy fin structure has a protruding portion protruding from a top surface of the etched mask layer after the first etching operation.

Abstract: A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.

Abstract: An extreme ultraviolet lithography system (10) that creates a new pattern (330) having a plurality of densely packed parallel lines (332) on a workpiece (22), the system (10) includes a patterning element (16); an EUV illumination system (12) that directs an extreme ultraviolet beam (13B) at the patterning element (16); a projection optical assembly (18) that directs the extreme ultraviolet beam diffracted off of the patterning element (16) at the workpiece (22) to create a first stripe (364) of generally parallel lines (332) during a first scan (365); and a control system (24). The workpiece (22) includes an existing pattern (233) that is distorted. The control system (24) selectively adjusts a control parameter during the first scan (365) so that the first stripe (364) is distorted to more accurately overlay the portion of existing pattern (233) positioned under the first stripe (364).

Abstract: Techniques for fabricating a metallic interconnect include forming a first metallization layer that includes a first dielectric layer, a first metallic layer formed in the first dielectric layer and a first capping layer formed on the first dielectric layer and the first metallic layer and forming a second metallization layer that includes a second dielectric layer, a second metallic layer formed in the second dielectric layer and a second capping layer formed on the second dielectric layer and the second metallic layer. A channel is etched in the second capping layer, second dielectric layer, and first capping layer that exposes a portion of the first metallic layer and a portion of the second metallic layer. A metallic interconnect structure is formed in the channel in contact with the exposed portion of the first metallic layer and the exposed portion of the second metallic layer.

Abstract: A multi-layer circuit structure is disposed on the delivery loading plate through the bottom-layer circuit structure, the delivery loading plate exposes the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board.

Abstract: Embodiments described herein provide a method of large area lithography. One embodiment of the method includes projecting at least one incident beam to a mask in a propagation direction of the at least one incident beam. The mask having at least one period of a dispersive element that diffracts the incident beam into order mode beams having one or more diffraction orders with a highest order N greater than 1. The one or more diffraction orders provide an intensity pattern in a medium between the mask and a substrate having a photoresist layer disposed thereon. The intensity pattern includes a plurality of intensity peaks defined by sub-periodic patterns of the at least one period. The intensity peaks write a plurality of portions in the photoresist layer such that a number of the portions in the photoresist layer corresponding to the at least one period is greater than N.

Abstract: A silsesquioxane-containing composition comprising a silsesquioxane resin and an oxaamine of formula (II) (see description), products prepared therefrom, photoresist compositions comprising the silsesquioxane-containing composition and a photoacid generator, products prepared therefrom, methods of making and using same, and manufactured articles and semiconductor devices containing same.

Abstract: A method for making an ultra-thin dielectric printed circuit board (PCB) is provided. A first side of a first conductive layer is removably coupled to a disposable base. A first ultra-thin dielectric layer and a second conductive layer are laminated to a second side of the first conductive layer, where the first ultra-thin dielectric layer is positioned between the first and second conductive layers, and the first ultra-thin dielectric layer is thinner than at least one of the first conductive layer and the second conductive layer. The second conductive layer may then be patterned to form electrical paths. The patterned second conductive layer is then filled with a dielectric filler. One or more conductive layers and one or more ultra-thin dielectric layers may then be coupled to the second conductive layer. The disposable base may then be detached from the first conductive layer.

Abstract: A printed circuit board according to one embodiment of the present invention is a printed circuit board including a plate-shaped or a sheet-shaped insulating material having a penetrating hole, and a metal plating layer layered on both surfaces of the insulating material and an inner peripheral surface of the insulating material, wherein an inner diameter of the penetrating hole monotonically decreases from a top surface of the insulating material toward a back surface, and wherein the inner diameter of the penetrating hole at a center in a thickness direction of the insulating material is smaller than an average of an opening diameter on the top side and an opening diameter on the back side.

Abstract: A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.

Abstract: In one example in accordance with the present disclosure a three-dimensional illumination chart is described. The chart includes a substrate divided into a number of portions. Each portion includes a raised relief pattern disposed thereon having a relief angle relative to a reference line. Each relief angle of the raised relief patterns of the number of portions is different from other relief angles of other raised relief patterns of other of the number of portions.

Abstract: Thermally cross-linkable photo-hydrolyzable inkjet printable polymers are used to print microfluidic channels layer-by-layer on a substrate. In one embodiment, for each layer, an inkjet head deposits droplets of a mixture of hydrophobic polymer and cross-linking agent in a pattern lying outside a two-dimensional layout of the channels, and another inkjet head deposits droplets of a mixture of poly(tetrahydropyranyl methacrylate) PTHPMA (or another hydrophobic polymer which hydrolyzes to form a hydrophilic material), cross-linking agent, and a photoacid generator (PAG) in a pattern lying inside the two-dimensional layout of the channels. After all layers are printed, flood exposure of the entire substrate to UV radiation releases acid from the PAG which hydrolyzes PTHPMA to form hydrophilic poly(methacrylic acid) PMAA, thereby rendering the PTHPMA regions hydrophilic. The layers of these now-hydrophilic patterned regions together define the microfluidic channels. The cross-linking agent (e.g.

Abstract: A method for producing a pattern of features on a substrate may involve performing two exposure steps on a resist layer applied to the substrate, followed by a single etching step. In the two exposures, the same pattern of mask features is used, but with possibly differing dimensions and with the pattern applied in the second exposure being shifted in position relative to the pattern in the first exposure. The shift, lithographic parameters, and/or possibly differing dimensions are configured such that a number of resist areas exposed in the second exposure overlap one or more resist areas exposed in the first exposure. When the pattern of mask features is a regular 2-dimensional array, the method produces of an array of holes or pillars that is denser than the original array. Varying the mask patterns can produce different etched structure shapes, such as a zig-zag pattern.

Abstract: A method includes forming a polymer layer on a patterned photo resist. The polymer layer extends into an opening in the patterned photo resist. The polymer layer is etched to expose the patterned photo resist. The polymer layer and a top Bottom Anti-Reflective Coating (BARC) are etched to pattern the top BARC, in which the patterned photo resist is used as an etching mask. The top BARC is used as an etching mask to etching an underlying layer.

Abstract: A light homogenization method for multi-source large-scale surface exposure 3D printing, comprising the following steps: projecting pure-color images of a first color and a second color having identical attributes capturing an image of an overlapping portion and calculating height and width information of the overlapping portion; splitting a pre-processed slice and respectively recording width and height information of two slices resulting from the splitting and generating two grayscale images having identical attributes thereto; counting power values of identical positions of slices in different grayscale values, performing a further calculation to obtain a projection mapping function, using the projection mapping function as a basis for performing optimization on grayscale interpolation of the generated images; and fusing the processed grayscale images and the originally split two slices to obtain a surface exposure 3D printing slice having a uniform brightness in final shaping.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure over a semiconductor substrate, and forming a mask layer covering the dummy fin structure. The method further includes irradiating the mask layer, so that the mask layer is divided into an unirradiated portion and an irradiated portion, and the irradiated portion is over the dummy fin structure. The method also includes removing a top portion of the irradiated portion and a top portion of the dummy fin structure by a first etching operation, such that the dummy fin structure has a convex top surface after the first etching operation. The method includes removing a middle portion of the dummy fin structure by a second etching operation, such that the dummy fin structure has a concave top surface after the second etching operation.

Abstract: An organic thin film structure is formed on a surface of a glass substrate. At least two color resist blocks are formed by patterning. A recess is formed between the two adjacent color resist blocks. Each of the color resist blocks has a lower color resist layer and an upper color resist layer formed on a surface of the lower color resist layer. A boundary of the upper color resist layer and a boundary the lower color resist layer are connected, and an angle between the boundaries and the surface of the glass substrate ranges from 10° to 60°.

Abstract: A touch screen panel and a method of manufacturing the same. The touch screen panel includes: a plurality of touch electrodes disposed in a touch area of a substrate, the touch electrodes configured to sense a touch; and a connecting wire connected with the touch electrode and having a pad connected to one end. The connecting wire includes a first wire layer made of a metal nano wire disposed on the substrate, a second wire layer made of a first transparent conductive material, a third wire layer disposed on an upper surface of the second pad and made of a second transparent conductive material, and a fourth wire layer made of aluminum (Al) disposed on the third pad.

Abstract: A method of forming a semiconductor device includes the following steps. First of all, a material layer is formed on a substrate, and a sidewall image transferring process is performed to form plural first mask patterns on the material layer, with the first mask patterns parallel extended along a first direction. Next, a pattern splitting process is performed to remove a portion of the first mask patterns to form plural second openings, with the second openings parallel extended along a second direction, across the first mask patterns. Then, the material layer is patterned by using rest portions of the first mask patterns as a mask to form plural patterns arranged in an array.

Abstract: The present disclosure is directed to formation of a low-k spacer. For example, the present disclosure includes an exemplary method of forming the low-k spacer. The method includes depositing the low-k spacer and subsequently treating the low-k spacer with a plasma and/or a thermal anneal. The low-k spacer can be deposited on a structure protruding from the substrate. The plasma and/or thermal anneal treatment on the low-k spacer can reduce the etch rates of the spacer so that the spacer is etched less in subsequent etching or cleaning processes.

Abstract: Provided is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the DCS plasma treatment process, the atomic layer conformal deposition process, and the spacer etch mandrel pull process in order to meet the target final sidewall angle and other integration objecti

Abstract: Methods for forming a semiconductor structure are provided. The method for forming a semiconductor structure includes forming a material layer over a substrate and forming a resist layer over the material layer. The method for forming a semiconductor structure further includes exposing the resist layer to form an exposed portion of the resist layer and forming a treating material layer over the exposed portion and an unexposed portion of the resist layer. In addition, a top surface of the exposed portion of the resist layer reacts with the treating material layer. The method for forming a semiconductor structure further includes removing the treating material layer and removing the unexposed portion of the resist layer to form an opening in the resist layer after the treating material is removed.

Abstract: A semiconductor device and a method of forming the same are provided. An embodiment comprises a target layer and masking layers over the target layer. First openings are formed in the uppermost layer of the masking layers. Spacers are formed along sidewalls of the first openings, remaining first openings having a first pattern. Second openings are formed in the uppermost layer of the masking layers, the second openings having a second pattern. The first pattern and the second pattern are partially transferred to the target layer.

Abstract: A method for fabricating a capacitor includes providing a substrate and a first etching stop layer on the substrate; forming a plurality of first spacers on the first etching stop layer; forming an organic layer and a second etching stop layer sequentially on the first spacers, the organic layer covering the first spacers; forming a plurality of second spacers on the second etching stop layer, each second spacer crossing the first spacers; transferring a pattern of the second spacers to the organic layer to form an organic pattern; performing an etching process using the organic pattern and the first spacers as a mask to form an etching stop pattern and remove the second etching stop layer; transferring the etching stop pattern to the substrate to form a plurality of through holes.

Abstract: A pattern-forming method includes forming a base pattern including a first polymer on a front face side. A composition is applied on at least a lateral face of the base pattern. The composition includes at least one polymer that is capable of interacting with the first polymer. The composition is heated such that a portion of the at least one polymer interacts with the first polymer and that a coating film is formed on the lateral face of the base pattern. Another portion of the at least one polymer not having interacted with the first polymer is removed to form a resist pattern. The base pattern in a planar view has a shape with a long axis and a short axis, and a ratio of lengths of the long axis to the short axis is no less than 1.5 and no greater than 10.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure over a semiconductor substrate. The semiconductor device structure also includes a second fin structure over the semiconductor substrate. The second fin structure has a lower height than that of the first fin structure. The second fin structure includes a first sidewall and a second sidewall, and the first sidewall and the second sidewall surround a recess over the second fin structure.

Abstract: A pattern-forming method includes forming a prepattern that is insoluble or hardly soluble in an organic solvent. A resin layer is provided on at least a lateral face of the prepattern. The prepattern and the resin layer are heated such that an adjacent portion of the resin layer to the prepattern is made insoluble or hardly soluble in the organic solvent, without being accompanied by an increase of a molecular weight of the prepattern and the resin layer. A portion of the resin layer other than the adjacent portion of the resin layer is removed. The resin layer is formed from a first composition including a first polymer and an organic solvent. Solubility of the first polymer in the organic solvent does not substantially change due to an action of an acid. A weight average molecular weight of the first polymer is 15,000-150,000.

Abstract: An electro-optical apparatus includes a semiconductor layer which is provided on a first substrate, a gate electrode which is provided on the semiconductor layer, a first light-shielding member which is provided between the semiconductor layer and the first substrate, a second light-shielding member which is provided in an extension direction of the first substrate in the semiconductor layer, and a third light-shielding member which is provided on an opposite side to the first substrate in the semiconductor layer, in which the second light-shielding member is embedded within a groove which is formed between the first light-shielding member and the third light-shielding member, and the third light-shielding member is electrically connected to the gate electrode and the first light-shielding member via the second light-shielding member.

Abstract: A photomask layout includes: a substrate region; a lower stepped region at a region of the substrate region; and a pattern region at least partially crossing the lower stepped region and including at least one notch portion at an area overlapping the lower stepped region. A method of forming a pattern is also provided.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a semiconductor structure including a substrate, a dielectric layer formed over the substrate, and a hard mask region formed over the dielectric layer; forming a first photoresist layer over the hard mask region; performing a first lithography exposure using a photomask to form a first latent pattern; forming a second photoresist layer over the hard mask region; and performing a second lithography exposure using the photomask to form a second latent pattern. The photomask includes a first mask feature and a second mask feature. The first latent pattern corresponds to the first mask feature, and the second latent pattern corresponds to the first mask feature and the second mask feature.

Abstract: A color filter substrate used in a display and the method thereby, and the photo mask of the color filter substrate are disclosed. The color filter substrate comprises a main body and a plurality color resist patterns on the main body. The adjacent color resist patterns partially overlap wherein in the overlapping region, the thickness of bottom color resist pattern is gradually thinning in its edge direction. Through the above way, the horn section in the overlapping region of the adjacent RGB color resist patterns of the color filter substrate is reduced. The performance of the liquid crystals is improved. Moreover, the OC flat layer does not need to be built on RGB the color resist pattern. The production cost of the liquid crystal display device is reduced and the productivity is improved.

Abstract: A method of forming a non-continuous line pattern includes forming a DSA material layer on a substrate, performing a phase separation of the DSA material layer to form an ordered periodic pattern including a plurality of first polymer structures and the second polymer structures arranged alternately, forming a first mask to cover a first portion of the ordered periodic pattern, performing a first etching process to remove a portion of the first polymer structures exposed by the first mask, removing the first mask, forming a second mask to cover a second portion of the ordered periodic pattern, with an interval to the first portion of the ordered periodic pattern, performing a second etching process to remove a portion of the second polymer structures exposed by the second mask, and removing the second mask. The remaining first polymer structures and the remaining second polymer structures are not connected to each other.

Abstract: The present invention provides a halftone mask comprising an assist pattern and a manufacturing method of the halftone mask, which uses an ArF excimer laser as an exposing source, is used for a projection exposure by an off axis illumination, does not resolve the assist pattern while keeping the focal depth magnification effect as the assist pattern, and may form a transferred image having high contrast of a main pattern.