Including Multiple Resist Image Formation Patents (Class 430/312)
  • Patent number: 11335569
    Abstract: A method of manufacturing a conductive wire structure including following steps is provided. A conductive layer is formed on a substrate. A rectangular ring spacer is formed on the conductive layer by a self-aligned double patterning process. A patterned photoresist layer is formed. The patterned photoresist layer exposes a first portion and a second portion of the rectangular ring spacer. The first and second portions are located at two corners on a diagonal of the rectangular ring spacer. The first and second portions are removed by using the patterned photoresist layer as a mask to form a first spacer and a second spacer. The first spacer and the second spacer are L-shaped. The patterned photoresist layer is removed. A pattern of the first spacer and a pattern of the second spacer are transferred to the conductive layer to form an L-shaped first conductive wire and an L-shaped second conductive wire.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: May 17, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Huang-Nan Chen
  • Patent number: 11309338
    Abstract: Provided is a display device and an electronic apparatus that prevent the occurrence of failure in the connection between a mounting substrate and an electronic component. The display device includes an interconnection layer provided on a support substrate, a plurality of insulating layers provided above the interconnection layer, an opening provided in parts of the insulating layers, and a metal layer electrically connected to the interconnection layer and filling the opening up to a height below a layer surface of the insulating layer.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: April 19, 2022
    Assignee: SONY CORPORATION
    Inventors: Toshihiko Watanabe, Akiyoshi Aoyagi, Hirokazu Nakayama
  • Patent number: 11270884
    Abstract: A reflection mode photomask includes a substrate. The reflection mode photomask further includes a reflective multilayer over the substrate. The reflection mode photomask further includes a plurality of absorber stacks over the reflective multilayer, wherein each absorber stack of the plurality of absorber stacks has an etch stop layer, an absorber layer and an ARC layer, wherein a ratio of a thickness of the ARC layer to that of the etch stop layer is in a range from about 1:1 to about 1:2.5, and a sidewall roughness of each absorber stack of the plurality of absorber stacks is smaller than 3 nanometers (nm).
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Lang Chen, Chih-Chiang Tu
  • Patent number: 11254246
    Abstract: In a decorative sheet, a base material has a concave portion on a front face. The concave portion includes a bottom surface. The bottom surface includes a first surface, a second surface and a third surface. A depth dimension of the first surface is a first value. The depth dimension is a dimension from the front face of the base material along a thickness direction of the base material. The depth dimension of the second surface is a second value which is smaller than the first value. The third surface is a surface which is connected with the first surface at a back side of the thickness direction, and is connected with the second surface at a front side of the thickness direction.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: February 22, 2022
    Inventors: Shigeru Nakajima, Nobuyuki Aoki
  • Patent number: 11237485
    Abstract: Embodiments of the present disclosure relate to methods for positioning masks in a propagation direction of a light source. The masks correspond to a pattern to be written into a photoresist layer of a substrate. The masks are positioned by stitching a first mask and a second mask. The first mask includes a set of first features having first feature extensions extending therefrom at first feature interfaces. The second mask includes a set of second features having second feature extensions extending therefrom at second feature interfaces. Each first feature extension stitches with each corresponding second feature extension to form each stitched portion of a first stitched portion of the first pair of masks. The stitched portion of the first pair of masks defines a portion of the pattern to be written into the photoresist layer.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: February 1, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Yongan Xu, Christopher Dennis Bencher, Robert Jan Visser, Ludovic Godet
  • Patent number: 11205813
    Abstract: A manufacturing method of a proton battery and a proton battery module are provided. The manufacturing method of the proton battery includes the steps of providing a positive electrode, a negative electrode, and a polymer exchange membrane, and assembling the positive electrode, the negative electrode, and the polymer exchange membrane, in which the polymer exchange membrane is interposed between the positive electrode and the negative electrode. The step of providing the negative electrode at least includes forming a carbon layer on a substrate, and performing a polarization process on the carbon layer.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: December 21, 2021
    Assignees: YUAN ZE UNIVERSITY, HOMYTECH GLOBAL CO., LTD.
    Inventors: Chi-Yuan Lee, Chia-Hung Chen, John-Shong Cheong
  • Patent number: 11081571
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure, and forming a mask layer covering the dummy fin structure. The method also includes removing a portion of the mask layer and a top portion of the dummy fin structure by a first etching operation to form an etched mask layer, wherein the dummy fin structure has a protruding portion protruding from a top surface of the etched mask layer after the first etching operation.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung Chen, Kang-Min Kuo, Wen-Hsin Chan
  • Patent number: 11069528
    Abstract: A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Chang, Jung-Hau Shiu, Jen Hung Wang, Tze-Liang Lee
  • Patent number: 11067900
    Abstract: An extreme ultraviolet lithography system (10) that creates a new pattern (330) having a plurality of densely packed parallel lines (332) on a workpiece (22), the system (10) includes a patterning element (16); an EUV illumination system (12) that directs an extreme ultraviolet beam (13B) at the patterning element (16); a projection optical assembly (18) that directs the extreme ultraviolet beam diffracted off of the patterning element (16) at the workpiece (22) to create a first stripe (364) of generally parallel lines (332) during a first scan (365); and a control system (24). The workpiece (22) includes an existing pattern (233) that is distorted. The control system (24) selectively adjusts a control parameter during the first scan (365) so that the first stripe (364) is distorted to more accurately overlay the portion of existing pattern (233) positioned under the first stripe (364).
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: July 20, 2021
    Inventor: Michael B. Binnard
  • Patent number: 11056426
    Abstract: Techniques for fabricating a metallic interconnect include forming a first metallization layer that includes a first dielectric layer, a first metallic layer formed in the first dielectric layer and a first capping layer formed on the first dielectric layer and the first metallic layer and forming a second metallization layer that includes a second dielectric layer, a second metallic layer formed in the second dielectric layer and a second capping layer formed on the second dielectric layer and the second metallic layer. A channel is etched in the second capping layer, second dielectric layer, and first capping layer that exposes a portion of the first metallic layer and a portion of the second metallic layer. A metallic interconnect structure is formed in the channel in contact with the exposed portion of the first metallic layer and the exposed portion of the second metallic layer.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Hosadurga Shobha, Hsueh-Chung Chen, Chih-Chao Yang
  • Patent number: 11042098
    Abstract: Embodiments described herein provide a method of large area lithography. One embodiment of the method includes projecting at least one incident beam to a mask in a propagation direction of the at least one incident beam. The mask having at least one period of a dispersive element that diffracts the incident beam into order mode beams having one or more diffraction orders with a highest order N greater than 1. The one or more diffraction orders provide an intensity pattern in a medium between the mask and a substrate having a photoresist layer disposed thereon. The intensity pattern includes a plurality of intensity peaks defined by sub-periodic patterns of the at least one period. The intensity peaks write a plurality of portions in the photoresist layer such that a number of the portions in the photoresist layer corresponding to the at least one period is greater than N.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 22, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Arvinder Chadha
  • Patent number: 11044806
    Abstract: A multi-layer circuit structure is disposed on the delivery loading plate through the bottom-layer circuit structure, the delivery loading plate exposes the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 22, 2021
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Chin-Kuan Liu, Chao-Lung Wang, Shuo-Hsun Chang, Yu-Te Lu, Chin-Hsi Chang
  • Patent number: 10993333
    Abstract: A method for making an ultra-thin dielectric printed circuit board (PCB) is provided. A first side of a first conductive layer is removably coupled to a disposable base. A first ultra-thin dielectric layer and a second conductive layer are laminated to a second side of the first conductive layer, where the first ultra-thin dielectric layer is positioned between the first and second conductive layers, and the first ultra-thin dielectric layer is thinner than at least one of the first conductive layer and the second conductive layer. The second conductive layer may then be patterned to form electrical paths. The patterned second conductive layer is then filled with a dielectric filler. One or more conductive layers and one or more ultra-thin dielectric layers may then be coupled to the second conductive layer. The disposable base may then be detached from the first conductive layer.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: April 27, 2021
    Assignee: SANMINA CORPORATION
    Inventors: Shinichi Iketani, Toshiya Suzuki
  • Patent number: 10990012
    Abstract: A silsesquioxane-containing composition comprising a silsesquioxane resin and an oxaamine of formula (II) (see description), products prepared therefrom, photoresist compositions comprising the silsesquioxane-containing composition and a photoacid generator, products prepared therefrom, methods of making and using same, and manufactured articles and semiconductor devices containing same.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 27, 2021
    Assignee: Dow Silicones Corporation
    Inventors: Peng-Fei Fu, Wonbum Jang
  • Patent number: 10978631
    Abstract: A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Devendra K. Sadana, Ning Li, Stephen W. Bedell
  • Patent number: 10980114
    Abstract: A printed circuit board according to one embodiment of the present invention is a printed circuit board including a plate-shaped or a sheet-shaped insulating material having a penetrating hole, and a metal plating layer layered on both surfaces of the insulating material and an inner peripheral surface of the insulating material, wherein an inner diameter of the penetrating hole monotonically decreases from a top surface of the insulating material toward a back surface, and wherein the inner diameter of the penetrating hole at a center in a thickness direction of the insulating material is smaller than an average of an opening diameter on the top side and an opening diameter on the back side.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: April 13, 2021
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Eiko Imazaki, Koji Nitta, Kousuke Miura, Shoichiro Sakai, Kenji Takahashi, Masahiro Matsumoto, Hirohisa Saito
  • Patent number: 10891782
    Abstract: In one example in accordance with the present disclosure a three-dimensional illumination chart is described. The chart includes a substrate divided into a number of portions. Each portion includes a raised relief pattern disposed thereon having a relief angle relative to a reference line. Each relief angle of the raised relief patterns of the number of portions is different from other relief angles of other raised relief patterns of other of the number of portions.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: January 12, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Nathan Moroney, Ingeborg Tastl, Melanie M. Gottwals
  • Patent number: 10828883
    Abstract: Thermally cross-linkable photo-hydrolyzable inkjet printable polymers are used to print microfluidic channels layer-by-layer on a substrate. In one embodiment, for each layer, an inkjet head deposits droplets of a mixture of hydrophobic polymer and cross-linking agent in a pattern lying outside a two-dimensional layout of the channels, and another inkjet head deposits droplets of a mixture of poly(tetrahydropyranyl methacrylate) PTHPMA (or another hydrophobic polymer which hydrolyzes to form a hydrophilic material), cross-linking agent, and a photoacid generator (PAG) in a pattern lying inside the two-dimensional layout of the channels. After all layers are printed, flood exposure of the entire substrate to UV radiation releases acid from the PAG which hydrolyzes PTHPMA to form hydrophilic poly(methacrylic acid) PMAA, thereby rendering the PTHPMA regions hydrophilic. The layers of these now-hydrophilic patterned regions together define the microfluidic channels. The cross-linking agent (e.g.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dylan J. Boday, Joseph Kuczynski, Robert E. Meyer, III
  • Patent number: 10818504
    Abstract: A method for producing a pattern of features on a substrate may involve performing two exposure steps on a resist layer applied to the substrate, followed by a single etching step. In the two exposures, the same pattern of mask features is used, but with possibly differing dimensions and with the pattern applied in the second exposure being shifted in position relative to the pattern in the first exposure. The shift, lithographic parameters, and/or possibly differing dimensions are configured such that a number of resist areas exposed in the second exposure overlap one or more resist areas exposed in the first exposure. When the pattern of mask features is a regular 2-dimensional array, the method produces of an array of holes or pillars that is denser than the original array. Varying the mask patterns can produce different etched structure shapes, such as a zig-zag pattern.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 27, 2020
    Assignee: IMEC VZW
    Inventors: Waikin Li, Danilo De Simone, Sandip Halder, Frederic Lazzarino
  • Patent number: 10811270
    Abstract: A method includes forming a polymer layer on a patterned photo resist. The polymer layer extends into an opening in the patterned photo resist. The polymer layer is etched to expose the patterned photo resist. The polymer layer and a top Bottom Anti-Reflective Coating (BARC) are etched to pattern the top BARC, in which the patterned photo resist is used as an etching mask. The top BARC is used as an etching mask to etching an underlying layer.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsuan Chen, Yuan-Sheng Huang
  • Patent number: 10759110
    Abstract: A light homogenization method for multi-source large-scale surface exposure 3D printing, comprising the following steps: projecting pure-color images of a first color and a second color having identical attributes capturing an image of an overlapping portion and calculating height and width information of the overlapping portion; splitting a pre-processed slice and respectively recording width and height information of two slices resulting from the splitting and generating two grayscale images having identical attributes thereto; counting power values of identical positions of slices in different grayscale values, performing a further calculation to obtain a projection mapping function, using the projection mapping function as a basis for performing optimization on grayscale interpolation of the generated images; and fusing the processed grayscale images and the originally split two slices to obtain a surface exposure 3D printing slice having a uniform brightness in final shaping.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: September 1, 2020
    Assignee: Beijing University of Technology
    Inventors: Lifang Wu, Lidong Zhao, Jiankang Qiu, Xiaohua Guo, Meng Jian, Ziming Zhang
  • Patent number: 10727321
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure over a semiconductor substrate, and forming a mask layer covering the dummy fin structure. The method further includes irradiating the mask layer, so that the mask layer is divided into an unirradiated portion and an irradiated portion, and the irradiated portion is over the dummy fin structure. The method also includes removing a top portion of the irradiated portion and a top portion of the dummy fin structure by a first etching operation, such that the dummy fin structure has a convex top surface after the first etching operation. The method includes removing a middle portion of the dummy fin structure by a second etching operation, such that the dummy fin structure has a concave top surface after the second etching operation.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung Chen, Kang-Min Kuo, Wen-Hsin Chan
  • Patent number: 10677971
    Abstract: An organic thin film structure is formed on a surface of a glass substrate. At least two color resist blocks are formed by patterning. A recess is formed between the two adjacent color resist blocks. Each of the color resist blocks has a lower color resist layer and an upper color resist layer formed on a surface of the lower color resist layer. A boundary of the upper color resist layer and a boundary the lower color resist layer are connected, and an angle between the boundaries and the surface of the glass substrate ranges from 10° to 60°.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: June 9, 2020
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Wu Cao
  • Patent number: 10466845
    Abstract: A touch screen panel and a method of manufacturing the same. The touch screen panel includes: a plurality of touch electrodes disposed in a touch area of a substrate, the touch electrodes configured to sense a touch; and a connecting wire connected with the touch electrode and having a pad connected to one end. The connecting wire includes a first wire layer made of a metal nano wire disposed on the substrate, a second wire layer made of a first transparent conductive material, a third wire layer disposed on an upper surface of the second pad and made of a second transparent conductive material, and a fourth wire layer made of aluminum (Al) disposed on the third pad.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: November 5, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Shin Il Choi, Ji Hun Kim, Bong-Kyun Kim
  • Patent number: 10366889
    Abstract: A method of forming a semiconductor device includes the following steps. First of all, a material layer is formed on a substrate, and a sidewall image transferring process is performed to form plural first mask patterns on the material layer, with the first mask patterns parallel extended along a first direction. Next, a pattern splitting process is performed to remove a portion of the first mask patterns to form plural second openings, with the second openings parallel extended along a second direction, across the first mask patterns. Then, the material layer is patterned by using rest portions of the first mask patterns as a mask to form plural patterns arranged in an array.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Ching Chang
  • Patent number: 10361282
    Abstract: The present disclosure is directed to formation of a low-k spacer. For example, the present disclosure includes an exemplary method of forming the low-k spacer. The method includes depositing the low-k spacer and subsequently treating the low-k spacer with a plasma and/or a thermal anneal. The low-k spacer can be deposited on a structure protruding from the substrate. The plasma and/or thermal anneal treatment on the low-k spacer can reduce the etch rates of the spacer so that the spacer is etched less in subsequent etching or cleaning processes.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiu-Yu Kang, Hong-Wei Chen
  • Patent number: 10354873
    Abstract: Provided is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the DCS plasma treatment process, the atomic layer conformal deposition process, and the spacer etch mandrel pull process in order to meet the target final sidewall angle and other integration objecti
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: July 16, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Akiteru Ko, Angelique Raley, Sophie Thibaut, Satoru Nakamura, Nihar Mohanty
  • Patent number: 10312108
    Abstract: Methods for forming a semiconductor structure are provided. The method for forming a semiconductor structure includes forming a material layer over a substrate and forming a resist layer over the material layer. The method for forming a semiconductor structure further includes exposing the resist layer to form an exposed portion of the resist layer and forming a treating material layer over the exposed portion and an unexposed portion of the resist layer. In addition, a top surface of the exposed portion of the resist layer reacts with the treating material layer. The method for forming a semiconductor structure further includes removing the treating material layer and removing the unexposed portion of the resist layer to form an opening in the resist layer after the treating material is removed.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Po Yang, Chien-Wei Wang, Wei-Han Lai, Chin-Hsiang Lin
  • Patent number: 10256096
    Abstract: A semiconductor device and a method of forming the same are provided. An embodiment comprises a target layer and masking layers over the target layer. First openings are formed in the uppermost layer of the masking layers. Spacers are formed along sidewalls of the first openings, remaining first openings having a first pattern. Second openings are formed in the uppermost layer of the masking layers, the second openings having a second pattern. The first pattern and the second pattern are partially transferred to the target layer.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: April 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Patent number: 10204911
    Abstract: A method for fabricating a capacitor includes providing a substrate and a first etching stop layer on the substrate; forming a plurality of first spacers on the first etching stop layer; forming an organic layer and a second etching stop layer sequentially on the first spacers, the organic layer covering the first spacers; forming a plurality of second spacers on the second etching stop layer, each second spacer crossing the first spacers; transferring a pattern of the second spacers to the organic layer to form an organic pattern; performing an etching process using the organic pattern and the first spacers as a mask to form an etching stop pattern and remove the second etching stop layer; transferring the etching stop pattern to the substrate to form a plurality of through holes.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: February 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10175575
    Abstract: A pattern-forming method includes forming a base pattern including a first polymer on a front face side. A composition is applied on at least a lateral face of the base pattern. The composition includes at least one polymer that is capable of interacting with the first polymer. The composition is heated such that a portion of the at least one polymer interacts with the first polymer and that a coating film is formed on the lateral face of the base pattern. Another portion of the at least one polymer not having interacted with the first polymer is removed to form a resist pattern. The base pattern in a planar view has a shape with a long axis and a short axis, and a ratio of lengths of the long axis to the short axis is no less than 1.5 and no greater than 10.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: January 8, 2019
    Assignee: JSR CORPORATION
    Inventor: Hitoshi Osaki
  • Patent number: 10147805
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure over a semiconductor substrate. The semiconductor device structure also includes a second fin structure over the semiconductor substrate. The second fin structure has a lower height than that of the first fin structure. The second fin structure includes a first sidewall and a second sidewall, and the first sidewall and the second sidewall surround a recess over the second fin structure.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: December 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Lung Chen, Kang-Min Kuo, Wen-Hsin Chan
  • Patent number: 9921474
    Abstract: A pattern-forming method includes forming a prepattern that is insoluble or hardly soluble in an organic solvent. A resin layer is provided on at least a lateral face of the prepattern. The prepattern and the resin layer are heated such that an adjacent portion of the resin layer to the prepattern is made insoluble or hardly soluble in the organic solvent, without being accompanied by an increase of a molecular weight of the prepattern and the resin layer. A portion of the resin layer other than the adjacent portion of the resin layer is removed. The resin layer is formed from a first composition including a first polymer and an organic solvent. Solubility of the first polymer in the organic solvent does not substantially change due to an action of an acid. A weight average molecular weight of the first polymer is 15,000-150,000.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: March 20, 2018
    Assignee: JSR CORPORATION
    Inventor: Kanako Fukami
  • Patent number: 9823530
    Abstract: An electro-optical apparatus includes a semiconductor layer which is provided on a first substrate, a gate electrode which is provided on the semiconductor layer, a first light-shielding member which is provided between the semiconductor layer and the first substrate, a second light-shielding member which is provided in an extension direction of the first substrate in the semiconductor layer, and a third light-shielding member which is provided on an opposite side to the first substrate in the semiconductor layer, in which the second light-shielding member is embedded within a groove which is formed between the first light-shielding member and the third light-shielding member, and the third light-shielding member is electrically connected to the gate electrode and the first light-shielding member via the second light-shielding member.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: November 21, 2017
    Assignee: Seiko Epson Corporation
    Inventor: Yohei Sugimoto
  • Patent number: 9798227
    Abstract: A photomask layout includes: a substrate region; a lower stepped region at a region of the substrate region; and a pattern region at least partially crossing the lower stepped region and including at least one notch portion at an area overlapping the lower stepped region. A method of forming a pattern is also provided.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 24, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Man-Jong Yu
  • Patent number: 9679803
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a semiconductor structure including a substrate, a dielectric layer formed over the substrate, and a hard mask region formed over the dielectric layer; forming a first photoresist layer over the hard mask region; performing a first lithography exposure using a photomask to form a first latent pattern; forming a second photoresist layer over the hard mask region; and performing a second lithography exposure using the photomask to form a second latent pattern. The photomask includes a first mask feature and a second mask feature. The first latent pattern corresponds to the first mask feature, and the second latent pattern corresponds to the first mask feature and the second mask feature.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Chih-Tsung Shih, Yen-Cheng Lu
  • Patent number: 9671641
    Abstract: A color filter substrate used in a display and the method thereby, and the photo mask of the color filter substrate are disclosed. The color filter substrate comprises a main body and a plurality color resist patterns on the main body. The adjacent color resist patterns partially overlap wherein in the overlapping region, the thickness of bottom color resist pattern is gradually thinning in its edge direction. Through the above way, the horn section in the overlapping region of the adjacent RGB color resist patterns of the color filter substrate is reduced. The performance of the liquid crystals is improved. Moreover, the OC flat layer does not need to be built on RGB the color resist pattern. The production cost of the liquid crystal display device is reduced and the productivity is improved.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 6, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Feng Zhao
  • Patent number: 9583343
    Abstract: A method of forming a non-continuous line pattern includes forming a DSA material layer on a substrate, performing a phase separation of the DSA material layer to form an ordered periodic pattern including a plurality of first polymer structures and the second polymer structures arranged alternately, forming a first mask to cover a first portion of the ordered periodic pattern, performing a first etching process to remove a portion of the first polymer structures exposed by the first mask, removing the first mask, forming a second mask to cover a second portion of the ordered periodic pattern, with an interval to the first portion of the ordered periodic pattern, performing a second etching process to remove a portion of the second polymer structures exposed by the second mask, and removing the second mask. The remaining first polymer structures and the remaining second polymer structures are not connected to each other.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: February 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Te Chen, En-Chiuan Liou, Chia-Hsun Tseng, Shin-Feng Su, Yu-Ting Hung, Meng-Lin Tsai
  • Patent number: 9519211
    Abstract: The present invention provides a halftone mask comprising an assist pattern and a manufacturing method of the halftone mask, which uses an ArF excimer laser as an exposing source, is used for a projection exposure by an off axis illumination, does not resolve the assist pattern while keeping the focal depth magnification effect as the assist pattern, and may form a transferred image having high contrast of a main pattern.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: December 13, 2016
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Takaharu Nagai, Hiroshi Mohri, Yasutaka Morikawa, Katsuya Hayano
  • Patent number: 9502365
    Abstract: An integrated circuit and method with a delamination free opening formed through multiple levels of polymer dielectric. The opening has a vertical sidewall and no interface between adjacent levels of polymer dielectric is exposed on the vertical sidewall.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: November 22, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Licheng Marshal Han, Michael Andrew Serafin, Byron Williams, Sandra Rodriguez Varela, Salvatore Pavone
  • Patent number: 9490136
    Abstract: A method includes forming a hard mask (HM) stack over a material layer, which has a first, second, third and fourth HM layers. The method also includes forming a first trench in the fourth HM layer, forming a first spacer in the first trench, forming a second trench in the fourth HM layer, removing at least a portion of the first spacer to form a cut by using the third HM layer as an etch-stop layer, removing a portion of the third HM layer and the second HM layer exposed by the first trench, second trench, and cut to form an extended first trench, extended second trench, and extended cut, respectively. The method also includes forming second spacers in the extended first trench, the extended second trench, and the extended cut and removing another portion of the second HM layer to form a third trench.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Chang, Chia-Tien Wu, Yung-Hsu Wu
  • Patent number: 9472653
    Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: October 18, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Hyuk Kim, Kang-Ill Seo, Hyun-Jae Kang, Deok-Han Bae
  • Patent number: 9360758
    Abstract: In accordance with an embodiment, a method of filtering a process fluid such as a negative tone developer is provided. The negative tone developer is introduced to a filter membrane that comprises a fluorine-based polymer. The negative tone developer is then filtered through the filter membrane. By using these materials and methods, polyethylene from the filter membrane will not contaminate the photoresist during development and reduce defects that arise from polyethylene contamination.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Hsin Lo, Ching-Yu Chang
  • Patent number: 9341940
    Abstract: A reticle and a method of fabricating the reticle are provided. In various embodiments, the reticle includes a substrate, a patterned first attenuating layer, a patterned second attenuating layer, and a patterned third attenuating layer. The patterned first attenuating layer is disposed on the substrate. The patterned second attenuating layer is disposed on the patterned first attenuating layer. The patterned third attenuating layer is disposed on the patterned second attenuating layer. A first part of the patterned first attenuating layer, a first part of patterned second attenuating layer, and the patterned third attenuating layer are stacked on the substrate as a binary intensity mask portion.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 17, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chang Hsueh, Chia-Jen Chen, Ta-Cheng Lien, Hsin-Chang Lee
  • Patent number: 9311439
    Abstract: Provided are methods of forming patterns of wafers using self-aligned double patterning processes. The methods include preparing an initial layout having a first design pattern, a second design pattern, and a third design pattern disposed between the first design pattern and the second design pattern, extracting a first sub-layout including the first design pattern and a second sub-layout including the second design pattern from the initial layout using a computer, forming a first modified sub-layout including a first modified design pattern obtained by modifying the first design pattern of the first sub-layout using the computer, generating a modified layout including the first modified sub-layout and the second sub-layout using the computer, and performing a double patterning process using the modified layout.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Moon-Gyu Jeong
  • Patent number: 9219178
    Abstract: A method of fabrication of a collimator structure on a detector that includes applying a first layer of resist to a semiconductor sensor, applying a second layer of resist over the first layer of resist and the semiconductor sensor to cover both the first layer of resist and the semiconductor sensor, exposing the second layer of resist to ultraviolet (UV) light with a photomask to transfer a pattern from the photomask to the second layer of resist, removing portions of the second layer of resist corresponding to the pattern from the photomask to produce openings in the second layer of resist, which expose upper portions of the semiconductor sensor, and depositing a layer of metal in the openings and on the second layer of resist to cover the openings, the first layer of resist, the second layer of resist, and the semiconductor sensor.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: December 22, 2015
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEDICAL SYSTEMS CORPORATION
    Inventors: Yuexing Zhang, Daniel Gagnon, Xiaolan Wang
  • Patent number: 9197183
    Abstract: The invention relates to a method of fabricating a single-piece micromechanical component including at least two distinct functional levels. According to the invention, the method includes a LIGA process on a single level combined with the machining of the LIGA deposition directly on the substrate.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: November 24, 2015
    Assignee: Nivarox-FAR S.A.
    Inventors: Alexandre Fussinger, Marc Stranczl
  • Patent number: 9177825
    Abstract: According to one embodiment, a pattern forming method includes forming, on an underlying region, a neutral film having an affinity for first and second polymers, forming a first pinning part having an affinity for the first polymer by irradiating a first region of the neutral film with an energy beam, forming, on the neutral film including the first pinning part, a block copolymer film containing the first and second polymers, and performing a predetermined treatment for the block copolymer film to perform a microphase separation.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: November 3, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yuriko Seino
  • Patent number: 9134610
    Abstract: An underlayer coating is used as an underlayer of photoresists in lithography process of the manufacture of semiconductor devices and has a high dry etching rate in comparison to the photoresists, does not intermix with the photoresists, and is capable of flattening the surface of a semiconductor substrate having holes of a high aspect ratio; and an underlayer coating forming composition can form the underlayer coating. The underlayer coating forming composition for forming by light irradiation an underlayer coating used as an underlayer of a photoresist in a lithography process of the manufacture of semiconductor devices, includes a polymerizable substance and a photopolymerization initiator.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: September 15, 2015
    Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Satoshi Takei, Tetsuya Shinjo, Motohiko Hidaka
  • Patent number: 9097975
    Abstract: A method of manufacturing using a double patterning method is provided. The double patterning method uses a first developer and a second developer that are different. For example, the first developer may be a positive tone developer for a positive photoresist while the second developer may be a negative tone developer for the positive photoresist. Photoresists having a photoactive compound are also provided that may be useful in double patterning methods. The resulting double patterning results, wherein a dimension of a variable first dense pattern is larger than a dimension of a variable second dense pattern.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: August 4, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Chin Cheng Yang