Abstract: A method for manufacturing a cone board including: preparing a core insulation layer including one or more resins selected from the group consisting of epoxy resins and bismaleimide triazine resins; and forming a first nickel layer on at least one surface of the core insulation layer by electroless plating

Abstract: The present invention relates to a flash memory card that is a structure using a rigid flexible board (RFB) to connect a flash memory card unit and a universal serial bus (USB) unit. A communication interface in compliance with the specification of the flash memory card is disposed at one end of the flash memory card, and a USB communication interface is disposed at another end, and a rigid flexible board is provided for connecting the electric signals between the two communication interfaces and the bending characteristic is used to maintain the height difference between the planes of the two communication interface, so that the flash memory card can concurrently have the USB communication interface and enhance the applicability of the flash memory card.

Abstract: Methods of fabricating a metal contact structure for a laser diodes are provided, wherein the method comprises providing a UV transparent semiconductor substrate, a UV transparent semiconductor epilayer defining a ridge disposed between etched epilayer edges, the epilayer being disposed over the UV transparent semiconductor substrate, and a UV opaque metal layer disposed over the epilayer ridge, applying at least one photoresist layer (positive photoresist, image reversal photoresist, or negative photoresist) over the opaque metal layer and epilayer edges, and selectively developing regions of the photoresist layer via backside exposure to UV light with the opaque metal layer used as a photolithographic mask.

Abstract: This is structure and method for providing a textured surfaced that can be used in a plurality of systems including ink jet printing. In ink jet printing, the textured surface of this invention controls ink drawback and significantly improves image quality. The textured surface has an average roughness, Ra, of about 0.2 to 1.5 microns, a texture density of about 104-107 pits per cm2, a texture size of about 0.5-5 microns, and a texture depth of about 0.5-10 microns.

Abstract: A single exposure method and a double exposure method for reducing mask error factor and for enhancing lithographic printing-process resolution is presented. The invention comprises decomposing a desired pattern of dense lines and spaces in two sub patterns of semi dense spaces that are printed in interlaced position with respect to each other, using positive tone resist. Each of the exposures is executed after applying a relative space-width widening to the spaces of two corresponding mask patterns of semi dense spaces. A factor representative for the space-width widening has a value between 1 and 3, thereby reducing mask error factor and line edge roughness.

Abstract: In a process for forming a solder mask, a photoimageable ink is coated on a carrier film to form a photoimageable ink layer on the carrier film. The photoimageable ink layer is dried to form a photoimageable resist layer, thereby forming at least one photoimageable resist layer bearing film. The photoimageable resist layer bearing film is laminated on at least one side of a substrate so as to bring the upper surface of the photoimageable resist layer into contact with the substrate. The photoimageable resist layer is exposed to light imagewise through the carrier film. The carrier film is removed from the photoimageable resist layer to form an exposed resist layer. The exposed resist layer is developed to form a developed resist layer. The developed resist layer is cured to form a solder mask on the substrate.

Abstract: A single exposure method and a double exposure method for reducing mask error factor and for enhancing lithographic printing-process resolution is presented. The invention comprises decomposing a desired pattern of dense lines and spaces in two sub patterns of semi-dense spaces that are printed in interlaced position with respect to each other, using positive tone resist. Each of the exposures is executed after applying a relative space-width widening to the spaces of two corresponding patterning device patterns of semi-dense spaces. A factor representative for the space-width widening has a value between 1 and 3, thereby reducing mask error factor and line edge roughness.

Abstract: A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dimensional stacked semiconductor devices and/or structures. More specifically, a method is provided for patterning deep vias with an aspect ratio up to 10 into a Si substrate with smooth via sidewalls and sufficient slope to enable metallization.

Abstract: A method for forming an organic mask, includes: permeating an organic solvent into an organic pattern formed on a base film and containing at least one kind of organic material, by contacting the organic pattern with the organic solvent; and thereby, partially or entirely decreasing original adhesion strength between the base film and the organic pattern. A heat treatment may be conducted after contacting to adjust the adhesion strength. Using the organic pattern as a mask, isotropic etching is conducted. As a result, a desired taper angle of the etched base film can be achieved with high accuracy. The taper angle of the etched base film is adjustable by controlling the adhesion strength through the heat treatment.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device that includes performing an O2 plasma treatment step after forming a Si-containing anti-reflection film.

Abstract: The invention relates to a method (1) of manufacturing a silicon-metal composite micromechanical component (51) combining DRIE and LIGA processes. The invention also relates to a micromechanical component (51) including a layer wherein one part (53) is made of silicon and another part (41) of metal so as to form a composite micromechanical component (51). The invention concerns the field of timepiece movements.

Abstract: A waveguide of a multi-layer metal structure and a manufacturing method thereof are provided, the method including applying a plurality of metal layers on a substrate and a plurality of insulating layers respectively between the respective metal layers. Accordingly, it is possible to minimize conductive loss by dispersing current uniformly through wide regions between a signal line and ground lines.

Abstract: A method for manufacturing a semiconductor device using a photoresist polymer comprising a fluorine component, a photoresist composition containing the photoresist polymer and an organic solvent to reduce surface tension, by forming a photoresist film uniformly on the whole surface of an underlying layer pattern to allow a subsequent ion-implanting process to be stably performed.

Abstract: A method for forming a film pattern by disposing a functional fluid on a substrate, includes: forming a partition wall that includes a first opening that corresponds to a first film pattern and a second opening that corresponds to a second film pattern; and disposing a droplet of the functional fluid into the first opening, so that the functional fluid is disposed into the second opening by a self-flow of the functional fluid; wherein: the first film pattern is linear; the second film pattern is narrower than the first film pattern, and is connected to the first film pattern at a rear edge thereof; and a front edge of the second film pattern has a missing part in which a corner of a rectangular contour is missing.

Abstract: A method of forming a contact hole includes forming a plurality of lower patterns on a substrate. An insulation layer is formed on the lower patterns. A self-assemble induction layer is formed on the insulation layer. A recess is formed in the self-assemble induction layer in alignment with the lower patterns. A block copolymer layer is formed in the recess to form a polymer domain at a distance from a sidewall of the recess and a polymer matrix surrounding the polymer domain. The polymer domain is removed. The self-assemble induction layer is etched using the polymer matrix as a mask to form an opening through the self-assemble induction layer to expose the insulation layer. The insulation layer exposed by the opening is etched using the self-assemble induction layer as a mask so as to form a contact hole.

Abstract: A semiconductor device includes a support body, a first substrate provided on a surface at one side of the support body, a second substrate provided on a surface at the other side of the support body, and a semiconductor chip provided on the first substrate exposed to an opening part piercing the support body and the second substrate. The first substrate includes a first dielectric layer and a wiring layer, a plurality of first electrodes connected to the semiconductor chip which first electrodes are provided on a first surface of the first substrate exposed to an inside of the opening part, and the second substrate includes a second dielectric layer made of a material substantially the same as the first dielectric layer.

Abstract: Polymers, methods of use thereof, and methods of decomposition thereof, are provided. One exemplary polymer, among others, includes, a photodefinable polymer having a sacrificial polymer and a photoinitiator.

Abstract: A method for forming a fine pattern of a semiconductor device includes forming a first photoresist pattern over a semiconductor substrate including an underlying layer. A cross-linking layer is formed on the sidewall of the first photoresist pattern. The first photoresist pattern is removed to form a fine pattern including a silicon polymer. A second photoresist pattern is formed that is coupled to the fine pattern. The underlying layer is etched using the fine pattern and the second photoresist pattern as an etching mask. As a result, the fine pattern has a smaller size than a minimum pitch.

Abstract: Methods for fabricating of high aspect ratio probes and deforming micropillars and nanopillars are described. Use of polymers in deforming nanopillars and micropillars is also described.

Abstract: An electro-optical printed circuit board contains electrical conductor tracks on the one hand and optical waveguide structures on the other hand. The optical waveguide structures comprise a bottom layer, a core layer and a cladding layer. Visible areas are applied to the printed circuit board, and the core layer is applied later both to the bottom layer as well as the visible areas and structured both on the bottom layer as well as the visible areas. This structure is then transferred to the visible areas, e.g. by etching. Reference marks are thus produced which contain the information on the actual position of the optical waveguide structures.

Abstract: The present invention relates to a process for forming an reverse tone image on a device comprising; a) forming an optional absorbing organic underlayer on a substrate; b) forming a coating of a photoresist over the underlayer; c) forming a photoresist pattern; d) forming a polysilazane coating over the photoresist pattern from a polysilazane coating composition, where the polysilazane coating is thicker than the photoresist pattern, and further where the polysilazane coating composition comprises a silicon/nitrogen polymer and an organic coating solvent; e) etching the polysilazane coating to remove the polysilazane coating at least up to a level of the top of the photoresist such that the photoresist pattern is revealed; and, f) dry etching to remove the photoresist and the underlayer which is beneath the photoresist, thereby forming an opening beneath where the photoresist pattern was present.

Abstract: A method of fabricating integrated circuits is described. A multi-material hard mask is formed on an underlying layer to be patterned. In a first patterning process, portions of the first material of the hard mask are etched, the first patterning process being selective to etch the first material over the second material. In a second patterning process, portions of the second material of the hard mask are etched, the second patterning process being selective to etch the second material over the first material. The first and second patterning processes forming a desired pattern in the hard mask which is then transferred to the underlying layer.

Abstract: The invention includes methods of fabricating integrated circuitry and semiconductor processing polymer residue removing solutions. In one implementation, a method of fabricating integrated circuitry includes forming a conductive metal line over a semiconductor substrate. The conductive line is exposed to a solution comprising an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. In one implementation, a method of fabricating integrated circuitry includes forming an insulating layer over a semiconductor substrate. A contact opening is at least partially formed into the insulating layer. The contact opening is exposed to a solution comprising an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. In one implementation, a semiconductor processing polymer residue removing solution comprises an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. Other aspects and implementations are contemplated.

Abstract: A process for etching a metal or alloy surface which comprises applying an etch-resist ink by ink jet printing to selected areas of the metal or alloy, solidifying the etch-resist ink without the use of actinic light and/or particle beam radiation and then removing the exposed metal or alloy by a chemical etching process wherein the etch-resist ink comprises the components: A) 60 to 100 parts carrier vehicle comprising one or more components which contain at least one metal chelating group; D) 0 to 40 parts colorant; and E) 0 to 5 parts surfactant; wherein the ink has a viscosity of not greater than 30 cPs (mPa·s) at the firing temperature, all parts are by weight and the total number of parts A)+B)+C)=100.

Abstract: A composition for the organic hard mask includes a polyamic acid compound, and a method for forming a pattern is used in a manufacturing process of semiconductor devices by coating the composition for organic hard mask film on an underlying layer, and depositing a second hard mask film with a silicon nitride SiON film thereon to form a double hard mask film having an excellent etching selectivity, thereby obtaining a uniform pattern.

Abstract: This process for producing a resist pattern includes: the step of laminating (a) a support having an upper surface on which copper exists, (b) an inorganic substance layer consisting of an inorganic substance supplied from an inorganic substance source, and (c) a photoresist layer consisting of a chemically amplified type positive photoresist composition, to obtain a photoresist laminate, the step of selectively irradiating active light or radioactive rays to said photoresist laminate, and the step of developing said (c) photoresist layer together with said (b) inorganic substance layer to form a resist pattern.

Abstract: A method of forming a pattern on a photosensitive resin film in lithography, a method of forming a pattern for a semiconductor device, and a method of manufacturing a semiconductor device using the patterned film are disclosed. In an aspect of the invention, there is provided a method of forming a pattern on a photosensitive resin film, comprising forming a processing-object film above a semiconductor substrate, forming a first patterned photosensitive resin layer on the processing-object film, implanting ions into the first patterned photosensitive resin layer, the sum (Rp+3dRp) of a projected range (Rp) for the ions in the first photosensitive resin layer and three times a standard deviation (dRp) of the projected range being greater than a thickness of the first patterned photosensitive resin layer, and forming a second patterned photosensitive resin layer on the ion-implanted first patterned photosensitive resin layer.

Abstract: Polymers, methods of use thereof, and methods of decomposition thereof, are provided. One exemplary polymer, among others, includes, a photodefinable polymer having a sacrificial polymer and a photoinitiator.

Abstract: The photosensitive resin composition of the invention comprises (A) a photopolymerizing compound with two or more ethylenic unsaturated bonds in the molecule and (B) a photopolymerization initiator which initiates photopolymerization reaction of the (A) photopolymerizing compound, the photosensitive resin composition being characterized in that the molecule of the (A) photopolymerizing compound further contains a characteristic group with a bond which breaks when the (A) photopolymerizing compound is heated under temperature conditions of 130-250° C.

Abstract: A first circuit element, which is reflective, is formed. A first layer, which is attenuating, is formed. above the first circuit element. A second layer, which is transparent, is formed above the first layer to fill an aperture in the first layer. An overlying lithography resist layer is then exposed to a radiation flux level below a development threshold but high enough that a sum of the radiation flux level and a reflected secondary radiation flux level exceeds the development threshold. The lithography resist layer is developed so as to obtain a mask having an opening through which the first and second layers are removed to form a second aperture which is filled to form a second circuit element.

Abstract: A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode.

Abstract: A method and system for providing a PMR pole in a magnetic recording transducer including an intermediate layer are disclosed. The method and system include providing a mask on the intermediate layer. The mask includes a line having at least one side. A hard mask layer is provided on the mask. At least a portion of the hard mask layer resides on the side(s) of the line. At least part of the hard mask layer on the side(s) of the line is removed. Thus, at least a portion of the line is exposed. The line is then removed, providing an aperture in the hard mask corresponding to the line. The method also includes forming a trench in the intermediate layer under the aperture. The trench top is wider than its bottom. The method further includes providing a PMR pole, at least a portion of which resides in the trench.

Abstract: A system and a method for self-aligned dual patterning are described. The system includes a platform for supporting a plurality of process chambers. An etch process chamber coupled to the platform. An ultra-violet radiation photo-resist curing process chamber is also coupled to the platform.

Abstract: A method of making a device includes forming an underlying mask layer over an underlying layer, forming a first mask layer over the underlying mask layer, patterning the first mask layer to form first mask features, undercutting the underlying mask layer to form underlying mask features using the first mask features as a mask, removing the first mask features, and patterning the underlying layer using at least the underlying mask features as a mask.

Abstract: There is disclosed a thermosetting metal oxide-containing film-forming composition for forming a metal oxide-containing film to be formed in a multilayer resist process used in lithography, the thermosetting metal oxide-containing film-forming composition comprising, at least: (A) a metal oxide-containing compound obtained by hydrolytic condensation of a hydrolyzable silicon compound and a hydrolyzable metal compound; (B) a thermal crosslinking accelerator; (C) a monovalent, divalent, or higher organic acid having 1 to 30 carbon atoms; (D) a trivalent or higher alcohol; and (E) an organic solvent.

Abstract: A device manufacturing method includes a transfer of a pattern from a patterning device onto a substrate. The device manufacturing method further includes transferring a pattern of a main mark to a base layer for forming an alignment mark; depositing a pattern receiving layer on the base layer; in a first lithographic process, aligning, by using the main mark, a first mask that includes a first pattern and a local mark pattern, and transferring the first pattern and the local mark pattern to the pattern receiving layer; aligning, by using the local mark pattern, a second mask including a second pattern relative to the pattern receiving layer; and in a second lithographic process, transferring the second pattern to the pattern receiving layer; the first and second patterns being configured to form an assembled pattern.

Abstract: Processes for fabricating a contact grid for a photovoltaic cell generally includes providing a photovoltaic cell having an antireflective coating disposed on a sun facing side, the photovoltaic cell comprising a silicon substrate having a p-n junction; soft stamping a pattern of a UV sensitive photoresist and/or polymer onto the antireflective coating; exposing the UV sensitive photoresist and/or polymer to ultraviolet radiation to cure the UV sensitive photoresist and/or polymer; etching the pattern to form openings in the antireflective coating that define the contact grid; stripping the UV sensitive photoresist and/or polymer; and depositing a conductive metal into the openings defined by the pattern. The metal based paste can be aluminum based, which can be annealed at a relatively low temperature.

Abstract: Provided are contact photomasks and methods using such photomasks for fabricating semiconductor devices and forming contact plugs on portions of active regions exposed between gate lines. The elongated active regions are arrayed in a series of parallel groups with each group being, in turn, aligned along their longitudinal axes to form an acute angle with the gate lines. The contact photomask includes a plurality of openings arranged in parallel lines that are aligned at an angle offset from previously formed gate lines and which may be parallel to the active regions or may be aligned at an angle offset from the axes of both the groups of active regions and the gate lines. Processes for forming contact plugs using such photomasks may provide increased processing margin and extend the utility of conventional exposure equipment for semiconductor devices exhibiting increased integration density and/or built to more demanding design rules.

Abstract: A method for fabricating a semiconductor device includes forming a mask pattern over a substrate; etching a certain portion of the substrate using the mask pattern as an etch mask to form a first recess having sidewalls; forming a polymer-based layer over the sidewalls of the first recess and a top surface of the mask pattern; etching the substrate beneath the first recess using the mask pattern and the polymer-based layer as an etch mask to form a second recess wider and more rounded than the first recess, the second recess and the first recess constituting a bulb-shaped recess; and forming a gate pattern over the bulb-shaped recess.

Abstract: Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region.

Abstract: A method for forming an opening is disclosed. First, a semiconductor substrate is provided, in which the semiconductor substrate includes at least one metal interconnects therein. A stacked film is formed on the semiconductor substrate, in which the stacked film includes at least one dielectric layer and one hard mask. The hard mask is used to form an opening in the stacked film without exposing the metal interconnects, and the hard mask is removed thereafter. A barrier layer is later deposited on the semiconductor substrate to cover a portion of the dielectric layer and the surface of the metal interconnects.

Abstract: A method for manufacturing a semiconductor device includes calculating a correction amount for correcting a dimension error generated in a pattern, by using an area and a total length of sides of a perimeter of the pattern included in each grid region of a plurality of mesh-like grid regions made by virtually dividing a pattern creation region of an exposure mask, exposing the pattern whose dimension has been corrected by the correction amount onto a substrate on which a resist film is coated, developing the resist film after the exposing, and processing the substrate by using a resist pattern after the developing.

Abstract: A method for smoothing a printed circuit board (PCB), comprising: providing a PCB having a first smooth outer surface and an opposite second outer surface, the second outer surface including a smooth region and a plurality of dimples; applying a liquid photoresist layer onto the second outer surface of the PCB to fill the dimples; solidifying the liquid photoresist in the dimples to obtain a solidified photoresist layer; polishing the solidified photoresist layer until a surface thereof being coplanar with the smooth region; and polishing the entire second outer surface until the solidified photoresist layer is removed, thereby obtaining a plain outer surface parallel to the first smooth outer surface.

Abstract: Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction.

Abstract: A method of producing an address plate comprising the steps of; coating a layer of conducting inorganic material onto a substrate, coating a layer of photoresist above this layer of conductive material and curing this layer, exposing, through a mask, the desired pattern of the conductors onto the layer of photoresist, developing the photoresist and etching the layer of the conductive material and coating the resulting etched layer with a layer of dielectric material. A further layer of photoresist is then applied, the thickness of this layer being equal to the desired height of a relief pattern, curing the further layer of photoresist, exposing, through a second mask, the desired structure of the relief pattern onto the layer of photoresist, developing the photoresist and allowing the layer to dry. This results in spacers raised above the layer of dielectric material.

Abstract: An overlay accuracy measurement vernier and a method of forming the same. According to one embodiment, the method of forming the overlay accuracy measurement vernier includes the steps of forming a first vernier pattern in a predetermined region on a semiconductor substrate; etching the semiconductor substrate using the first vernier pattern as a mask, forming a trench of a first depth; forming a second vernier pattern having a width wider than that of the first vernier pattern, the second vernier pattern including the first vernier pattern; performing an etch process using the second vernier pattern as a mask, thus forming a trench of a second depth, which has a step of a predetermined width; stripping the first and second vernier patterns and then forming an insulating film to bury the trench; and, etching the insulating film so that the semiconductor substrate of the vernier region is exposed.

Abstract: A method for forming fine patterns of a semiconductor device employs a double patterning characteristic using a mask for forming a first pattern including a line pattern and a mask for separating the line pattern, and a reflow characteristic of a photoresist pattern.

Abstract: A photoresist composition, e.g., a positive acting resist, for use in the formation of circuit patterns and the like on printed circuit boards and the like circuitized substrates, the photoresist composition including a quantity of silver therein in a sufficient amount to substantially prevent bacteria formation within said composition. A method of making the composition is also provided.

Abstract: A stencil mask includes a membrane forming thin layer having membrane areas and a border area that limits the membrane areas. The membrane areas have a plurality of pattern areas which include an aperture through which particle beams can permeate and non-pattern areas interposed between the pattern areas. A main strut supports the membrane areas and is formed on the border area of the membrane forming thin layer. An auxiliary strut is formed in the non-pattern areas inside the membrane pattern area such that the auxiliary strut divides the membrane areas into plural divided membrane areas. The auxiliary strut supports the divided membrane areas.

Abstract: In the method for manufacturing a semiconductor device, a resist film is formed on a substrate and is processed to be provided with openings to form a first resist pattern. Additive-containing layers containing an additive that changes a state of the resist film to a soluble state for a developer are formed so as to cover the first resist pattern. A first resin film having a nature of changing to a soluble state for the developer by containing the additive is formed in the openings of the first resist pattern. The additive is diffused into the first resist pattern and the first resin film to form first and second additive-diffusing portions which can be solved in the developer. The first and second additive-diffusing portions are removed by the developer to form second resist pattern made of remaining portions in the first resist pattern and the first resin film.