Abstract: A method of forming a field emission device for a flat panel display includes operating a projection exposure apparatus. This comprises placing three layers of exposure sensitive material on a device in succession, with steps of exposure and removal of material between deposition of subsequent layers of exposure sensitive material. Furthermore, a field emission device is formed by exposing a third layer of exposure sensitive material, wherein a tip on the field emission device or plurality of tips on the field emission devices can be obtained with differing sharpness characteristics by varying the depth and diameter of holes in a mask used during exposure of exposure sensitive material.

Abstract: Features of two or more distinct sizes designed to optimize performance of an integrated circuit device are formed by transferring a pattern from a resist patterned with features of a single minimum feature size for which a resist exposure tool is optimized to a layer of preferably soluble material such as germanium oxide. Portions of this pattern are then enlarged using a block-out mask and the resulting pattern transferred to a further underlying layer preferably using an anisotropic reactive ion etch. The soluble material can then be removed leaving a robust mask with differing feature sizes for further processing. Preferably, Damascene conductive lines and vias are formed by providing an insulator as the further underlying material and filling the openings with metal or other conductive material.

Abstract: A method for forming a plurality of solder bumps comprising providing a pair of metallic supports. An initial solder layer is respectively disposed on each of the metallic supports which may be a metal-filled blind via. One or two additional solder layers are disposed on one of the initial solder layers. A multilayered packaging assembly includes the solder layer(s) on a plurality of substrates which are coupled together.

Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

Abstract: A process for forming a nanocrystal nanostructure is repeated for growing the nanostructure disposed on an electron beam resist layer that is disposed on a substrate for forming an electron beam shadowmask from the nanostructure on the electron beam resist layer prior to electron beam exposure for patterning the electron beam resist layer in advance of subsequent processing steps. The nanocrystals are semiconductor materials and metals such as silver. The nanostructure enable the creation of ultra-fine nanometer sized electron beam patterned structures for use in the manufacture of submicron devices such as submicron-sized semiconductors and microelectromechanical devices.

Abstract: A trench isolation method of a semiconductor integrated circuit is provided. In the trench isolation method, a mask pattern which defines a first opening and a second opening wider than the first opening is formed on a semiconductor substrate. A first spacer for filling the first opening and a second spacer are formed at the sidewalls of the second opening. A sacrificial material layer pattern having an etching rate substantially equal to that of the semiconductor substrate is formed in the second opening surrounded by the second spacer. The semiconductor substrate under the first and second spacers is exposed by selectively removing the first and second spacers. A deep trench region and a shallow trench region are formed in the exposed semiconductor substrate and under the sacrificial material layer, respectively, by etching the exposed semiconductor substrate and the sacrificial material layer pattern. An isolation layer filling the deep trench region and the shallow trench region is formed.

Abstract: A method for forming a protection device with slope laterals is provided. Firstly, providing a semiconductor substrate having a plurality of alternative first sacrificial layers and second sacrificial layers formed thereon. A first etching step is performed to remove one portion of each of the first sacrificial layers and thereby expose one portion of each lateral of each of the second sacrificial layers. Subsequently, performing a second etching step to remove one portion of the lateral of the second sacrificial layer. Then, repeatedly and alternately performing the first etching step and the second etching step until completely removing the first sacrificial layers and then obtaining a plurality of protection devices formed of the second sacrificial layers each of which having slope laterals.

Abstract: A method for manufacturing a polysilicon type thin film transistor comprises the steps of forming a polysilicon layer on a substrate, forming a gate insulating layer on the polysilicon layer, forming a gate layer on the gate insulating layer, forming a gate pattern by patterning, implanting impurities in the substrate over which the gate pattern is formed, forming a cover layer over the substrate in which impurities are implanted, and thermally annealing the substrate over which the cover layer is formed. In the invention, the thermal annealing carried out instead of a costly laser annealing after the impurity implantation.

Abstract: Methods for forming multilayer circuit structures are disclosed. In some embodiments, conductive layers, dielectric layers and conductive posts can be formed on both sides of a circuitized core structure. The conductive posts are disposed in the dielectric layers and can be stacked to form a generally vertical conduction pathway which passes at least partially through a multilayer circuit structure. The formed multilayer circuit structures can occupy less space than corresponding multilayer circuit structures with stacked via structures.

Abstract: The present invention lengthens gate conductors used in memory chips to limit leakage current, while still allowing the overall size of cells to remain the same. The channel length for each gate is increased by decreasing the size of spaces between gates. Decreases in space size occurs by using photolithographic image enhancement techniques. These techniques allow the space between gate conductors to be smaller while the gate size increases. In addition, a groove may be added that additionally lengthens the effective channel length and provides an additional electrical shield to limit leakage current. These techniques lead to the same density memory cells for a given process with less leakage. Finally, if grooved gate structures are used, having a longer gate conductor allows a three sigma process to be used, which increases yields.

Abstract: In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a photoresist over a first portion of the conductive film wherein a second portion of the conductive film is exposed, the photoresist having at least one sidewall over the conductive film; depositing a sidewall film over the conductive film and the photoresist, the sidewall film having a vertical portion adjacent the sidewall of the photoresist and a horizontal portion in areas not adjacent the sidewall of the photoresist; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; removing the photoresist exposing a fourth portion of the conductive film; and etching the third portion and the fourth portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewa

Abstract: A dual damascene semiconductor device (38) includes a first insulation layer (12) with a first electrical contact (14). A second insulation layer (20), having an outer surface (40), is formed over the first insulation layer and a trench (26) is preferably formed in the outer surface of the second insulation layer. The second insulation layer is a continuous, nonlayered layer of material. A second electrical contact (36) is embedded within the second insulation layer, typically within the trench. An electrical connection (34) passes through a via (hole) (32) formed in the second insulation layer to electrically connect the first and second electrical contacts. An etching-stop layer (18) may be used between the first and second insulation layers. The metal connection and electrical contacts may be made of copper. This invention applied the top surface image method to the via photo step.

Abstract: An interdigital electrode of a SAW device is protected by a protective layer during a photo-lithography etching process which is used to apply a bonding pad. As the bonding pad can be formed by the photo-lithography etching process, it is possible to obtain regularly shaped bonding pads without damaging the characteristics of the SAW device.

Abstract: In one embodiment, the present invention relates to a method of forming a sub-lithographic via or contact, involving the steps of providing a substrate comprising a conductor having a width of about 0.25 &mgr;m or less over a portion of the substrate and an insulating film over the conductor and the substrate; etching a preliminary via in the insulating film over the conductor, the preliminary via defined by sidewalls in the insulating film; depositing a CVD layer over the substrate, the insulating film, and the conductor, the CVD layer having a vertical portion adjacent the sidewalls of the insulating film and a horizontal portion in areas not adjacent the sidewalls of the insulating film; removing the horizontal portion of the CVD layer thereby forming the sub-lithographic via over the conductor, and depositing a conductive material into the sub-lithographic via to form a sub-lithographic contact, the sub-lithographic via and/or sub-lithographic contact having a width of less than about 0.25 &mgr;m.

Abstract: A fabrication method for reducing the critical dimension of the conductive line and the space is described in which a conductive layer and a mask layer are sequentially formed on a substrate. A taper etching is conducted to form a plurality of first openings with the cross-sections of the openings being tapered off from top to bottom and exposing the surface of the conductive layer. A planarized sacrificial layer at a similar height as the mask layer is formed covering the exposed surface of the conductive layer. A second taper etching is further conducted on the exposed mask layer to form a plurality of second openings with the cross-sections of the openings being tapered off from top to bottom. The sacrificial layer is then removed. Thereafter, an anisotropic etching is conducted on the exposed conductive layer, using the mask layer as a hard mask, to form a plurality of conductive lines followed by a removal of the mask layer.

Abstract: A method of producing a micro structure on a substrate which has a support portion and a plate-like portion supported thereby at a distance from the substrate, comprising the steps of forming a spacer layer consisting of an insulating material on a substrate having an electrically conductive layer formed on its surface, forming a latent image layer consisting of an electrically conductive material on the spacer layer at a site where the plate-like portion of an intended structure is to be formed, producing an aperture, where a part of the electrically conductive layer is exposed, on the spacer layer at a site where the supporting portion of an intended structure is to be formed, forming a structure layer consisting of plating film inside of the aperture and on the latent image layer by electroplating the electrically conductive layer as a cathode, and removing the spacer layer.

Abstract: In one embodiment, the present invention relates to a method of forming a circuit structure containing at least one sub-lithographic gate conductor involving the steps of providing a substrate comprising active regions and a preliminary gate conductor film over portions of the substrate and portions of the active regions; forming a sidewall template mask having at least one sidewall over a portion of the preliminary gate conductor film that is positioned over portions of the active regions; forming a sidewall film over the sidewall template mask, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template mask and a horizontal portion in areas not adjacent the sidewall of the sidewall template mask; removing the horizontal portion of the sidewall film exposing a portion of the sidewall template mask and removing the sidewall template mask; providing a second mask over the portions of the preliminary gate conductor film that are not positioned over portions of the active regions;

Abstract: Forming a protective layer such as chromium, chrome alloys, nickel or cobalt as a cap over an aluminum film protects an underlying ITO layer from corrosion during the fabrication of flat panel displays such as field emission devices and the like. The presence of the protective layer during fabrication processes such as photolithography prevents diffusion of solutions through the aluminum into the ITO. This protective layer is especially effective during the development and resist stripping stages of photolithography which use solutions or solvents that would otherwise cause reductive corrosion of ITO in contact with aluminum. The methods and apparatus described herein are particularly advantageous for the fabrication of flat panel displays such as field emission devices and other display devices, because ITO is often used in such devices in contact with aluminum while exposed to corrosion-inducing media.

Abstract: A method of removing regions of an anti-reflective coating includes etching the anti-reflective coating with a fluorinated hydrocarbon-based plasma etch and etching the anti-reflective coating with an oxygen-based plasma etch. In some implementations, the oxygen-based plasma etch is performed following the fluorinated hydrocarbon-based etch. The technique can be used to remove regions of an anti-reflective coating so that a more uniform and controlled etch of an underlayer can subsequently be performed. The disclosed technique is particularly useful for etching organic or organometallic anti-reflective layers, but can be used to etch other anti-reflective layers as well. In addition, the techniques are particularly advantageous for etching anti-reflective coatings disposed on certain oxide and nitride layers, although the underlayer can be formed of other materials as well.

Abstract: During the formation of a spherical cavity in a substrate, self-limiting etching behavior of an isotropic etchant can be utilized when a tape is used as an etch mask. Such a self-limiting behavior is due to the presence of gas bubbles (consisted of SiF4 and NO, etch by-products) which close the etch window and limit the mass transport of the etchant to this silicon surface. Because of that, the spherical cavity size depends mostly on the size of the etch-mask opening, and is independent of the etching time. This self-limiting etching behavior precisely controls the dimension and uniformity of the spherical cavity.

Abstract: A method for forming an electrode. The method includes forming a conductive plug through a first dielectric layer. The plug extends from an upper surface of the first dielectric layer to a contact region in a semiconductor substrate. The electrode is formed photolithographically, misalignment of a mask registration in the photolithography resulting in exposing surface portions of the barrier contact. A second dielectric layer is deposited over the first dielectric layer, over side portions and top portions of the formed electrode, and over the exposed portions of barrier contact. A sacrificial material is provided on portions of the second dielectric layer disposed on lower sides of the, electrode, on portions of the second dielectric layer disposed on the first dielectric layer, and on said exposed portions of the barrier contact while exposing portions of the second dielectric layer on the top portions and upper side portions of the formed electrode.

Abstract: A process for forming a dual damascene structure. The process includes forming a stack including insulating layers and a stop layer where two masks are formed above the stack. One of the masks is used to form via or contact openings in the insulating layers and the second mask is used to form grooves for interconnections in the insulating layers.

Abstract: A method for manufacturing a conductive strip includes forming a doped dielectric layer along a surface of a trench. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. Next step is to implant ions into the ion-implanted-sensitive resist by substantially vertical implantation such that the ion-implanted-sensitive resist over the lower and upper horizontal surfaces is insoluble portions in a developer and the vertical surface is soluble in the developer. Subsequently, the vertical surface is removed by using the developer and then the doped dielectric layer attached on the vertical surface is also removed. Then, a CMP process is used to remove the ion-implanted-sensitive resist and the doped dielectric layer. Next, a thermal treatment is used to diffuse the dopants in the doped dielectric layer into the lower horizontal surface.

Abstract: A method for patterning a layer of photoresist includes the steps of 1) exposing the photoresist through a standard precision mask to define all possible cut points, 2) etching all possible cut points in a dielectric layer, 3) selectively exposing a second layer of photoresist with a non-precision targeting energy beam or mask to select the desired cut points. Consequently, no custom precision masks are required to pattern the various layers of photoresist during the fabrication of application specific integrated circuits (ASICs), thereby reducing both the lead-time and costs for manufacturing ASICs.

Abstract: After depositing an anti-reflection coating of an organic material for absorbing an energy beam on an etching target film formed on a semiconductor substrate, a photosensitive film of a photosensitive material including a sulfonyl compound is deposited on the anti-reflection coating. After selectively irradiating the photosensitive film with an energy beam, an exposed or unexposed portion of the photosensitive film is removed, thereby forming a patterned photosensitive film. By using the patterned photosensitive film as a mask, the etching target film is dry etched. Thus, a pattern of the etching target film is formed.

Abstract: A method of producing a micro structure on a substrate which has a support portion and a plate-like portion supported thereby at a distance from the substrate, comprising the steps of forming a spacer layer consisting of an insulating material on a substrate having an electrically conductive layer formed on its surface, forming a latent image layer consisting of an electrically conductive material on the spacer layer at a site where the plate-like portion of an intended structure is to be formed, producing an aperture, where a part of the electrically conductive layer is exposed, on the spacer layer at a site where the supporting portion of an intended structure is to be formed, forming a structure layer consisting of plating film inside of the aperture and on the latent image layer by electroplating the electrically conductive layer as a cathode, and removing the spacer layer.

Abstract: Method of fabricating microstructures on a substrate. The method comprises providing a substrate layer having a first surface with a resist layer. First selected regions of the resist layer are exposed to an environment that renders the resist layer more or less soluble in a developer solution. The resist layer is then developed in the developer solution to expose selected regions of the substrate surface. Second selected regions of the resist layer are then exposed to an environment that renders the resist layer more or less soluble in the developer solution by aligning exposure of the second selected regions to the first selected regions. The first selected regions of the substrate surface are etched.

Abstract: After films composing a TFT are laminated on an insulating substrate, a resist mask having a plurality of regions with different film thicknesses is formed by patterning on the uppermost layer of the above-stated films. Then, a conductor film is formed by patterning with a liftoff method using this resist mask. Alternatively, using other resist mask having a plurality of regions with different film thicknesses as an etching mask, a plurality of material films among the laminated material films are processed in succession. By the above-stated new pattern forming method and the processing method, the liquid crystal display device, which has been manufactured by five photolitho processes in a conventional art is manufactured by two or three photolitho processes.

Abstract: Disclosed is a method for manufacturing a thin film transistor LCD device, in which a counter and a gate bus line are made in a single photolithography process, and a channel of a thin film transistor, a source electrode, a drain electrode, ohmic contacts for the source and drain electrodes are made in a single photolithography process.

Abstract: A method of manufacturing a semiconductor device through use of an organic polymeric material, the material having a superior embedding characteristic which enables uniform embedding without regard to density of hole patterns and realizing a high etch rate, an embedding material for use with the method and a semiconductor device. An organic polymeric material can be embedded into the hole patterns to a uniform height regardless of their density, by means of coating the material several times. Further, there is formed the organic polymeric material film 30 which is to be used for embedding hole patterns and from which a pigment component is eliminated so that the etch rate of the organic polymeric film 30 is increased. By means of applying the organic anti-reflective material film 32 over the organic polymeric material film 30, a film of uniform height can be formed through multiple stages. The interconnection trenches which do not require consideration for embedding hole patterns are formed first.

Abstract: The present invention relates to a method for forming an etch mask. A photoresist layer is patterned, wherein d1 is a smallest space dimension of an exposed area of a layer underlying the photoresist layer. An ARC layer under the photoresist layer is etched. A nitride layer is formed to be conformal to the patterned ARC layer and exposed portions of an underlayer underying the patterned ARC layer. The nitride layer is etched to form nitride sidewalls, the nitride sidewalls reducing the smallest space dimension of the exposed underlayer area to d2, wherein d2<d1.

Abstract: A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

Abstract: A method of forming a shallow trench isolation is provided. In the method, a barrier oxide layer is formed on a substrate, and a silicon nitride layer is formed on the barrier oxide layer. A metal layer is formed on the silicon nitride layer, and an ultra-thin photoresist is formed on the metal layer. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a shallow trench. The ultra-thin photoresist layer is used as a mask during a first etch step to transfer the shallow trench pattern to the metal layer. The first etch step includes an etch chemistry that is selective to the metal layer over the ultra-thin photoresist layer. The metal layer is used as a hard mask during a second etch step to form the shallow trench by etching portions of the silicon nitride layer, barrier oxide layer and substrate.

Abstract: A method of forming a dual damascene structure in low k dielectric material employs a multiple layer hard mask over the low k dielectric layer. The trench pattern is etched into the hard mask layer, followed by etching of a via pattern. The trench pattern is widened to completely coincide with the via if the via does not fall completely within the trench pattern due to alignment errors. The low dielectric constant material is protected from the photoresist removal process during the patterning and initial formation of the trench and via in the multiple layer hard mask.

Abstract: A method of manufacturing an electronic device with two layers of organic-containing material which enables a structure with well-defined dimensions to be made in the layers of organic-containing material. This is accomplished through a series of steps of applying a first layer of organic-containing material to a substrate, covering the it with a first layer of inorganic material, applying a second distinct layer of inorganic material, providing a first mask layer of resist having first openings, and etching through the second layer of inorganic material at the first openings using an etch process where the second inorganic material is selectively etched with respect to the first inorganic material. The first mask layer of resist is removed, and etching is performed through the first layer of inorganic material at the location of the first openings. A second layer of organic-containing material is applied and is covered with a third layer of inorganic material.

Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon oxynitride layer over the oxide layer; depositing an ultra-thin photoresist over the silicon oxynitride layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon oxynitride layer; etching the exposed portion of the silicon oxynitride layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.

Abstract: A method for forming contacts on an integrated circuit that are self-aligned with the wiring patterns of the integrated circuit. In the method a thicker lower layer of a first material and a thinner upper layer of a second material are formed on a substrate. The features of the metal wiring is patterned first on the upper layer. The wiring pattern trenches are etched through the thinner surface layer, and partially through the second, thicker layer. After the wiring pattern is etched, the contacts for the wiring layer are printed as line/space patterns which intersect the wiring pattern. The contact pattern is etched into the lower, thicker layer with an etch process that is selective to the upper thinner layer. The contact is only formed at the intersection point of the wiring image with the contact image, therefore the contact is self-aligned to the metal.

Abstract: A method of forming a metal wiring using a dual damascene process is provided. A photosensitive polymer having low permittivity is used as an etch mask. Though the etch mask remains in the final structure, its low permittivity reduces parasitic capacitance effects. In this method, a photosensitive polymer pattern having a first hole with a first width is formed on a first interlayer dielectric film. A second interlayer dielectric film is formed on the photosensitive polymer pattern. A mask pattern, having a second hole, above the first hole, with a second width larger than the first width, is formed on the second interlayer dielectric film. A wiring region is formed by dry-etching the second interlayer dielectric film using the mask pattern as an etch mask. A via hole region is formed by dry-etching the first interlayer dielectric film using the photosensitive polymer pattern as an etch mask.

Abstract: The invention provides methods for forming contact openings to a substrate location with which electrical connection is desired. According to one aspect, a multi-level layer comprising masking material or photoresist is formed atop an electrically conductive substrate surface and defines a mask opening through which a contact opening is to be formed to an elevationally lower substrate location. A single layer of photoresist is patterned to form an elevationally thicker first layer immediately laterally adjacent the mask opening than a second layer which is formed laterally outward of the first layer. The electrically conductive substrate surface is etched through the mask opening to form the contact opening. The photoresist second layer is removed and the conductive substrate surface is etched to form a portion of an outer conductive component. Thereafter, conductive material is formed in the contact opening to electrically connect elevationally separated layers.

Abstract: In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a sidewall template over a first portion of the conductive film wherein a second portion of the conductive film is exposed, the sidewall template having at least one sidewall over the conductive film; depositing a sidewall film over the conductive film and the sidewall template, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template and a horizontal portion in areas not adjacent the sidewall of the sidewall template; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; removing the sidewall template exposing a fourth portion of the conductive film; and etching the third portion and the fourth portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlyin

Abstract: A method of forming a pattern which comprises the steps of, forming an organosilicon film on a work film, the organosilicon film comprising an organosilicon compound having a silicon-silicon bond in a backbone chain thereof and a glass transition temperature of 0° C. or more, forming a resist pattern on the organosilicon film, and transcribing the resist pattern on the organosilicon film through an etching of the organosilicon film by making use of an etching gas containing at least one kind of atom selected from the group consisting of chlorine, bromine and iodine. The organosilicon pattern obtained by the etching is employed as a mask for patterning the work film.

Abstract: A method of forming a metal wiring using a dual damascene process is provided. A photosensitive polymer having low permittivity is used as an etch mask. Though the etch mask remains in the final structure, its low permittivity reduces parasitic capacitance effects. In this method, a photosensitive polymer pattern having a first hole with a first width is formed on a first interlayer dielectric film. A second interlayer dielectric film is formed on the photosensitive polymer pattern. A mask pattern, having a second hole, above the first hole, with a second width larger than the first width, is formed on the second interlayer dielectric film. A wiring region is formed by dry-etching the second interlayer dielectric film using the mask pattern as an etch mask. A via hole region is formed by dry-etching the first interlayer dielectric film using the photosensitive polymer pattern as an etch mask.

Abstract: A double exposure process is disclosed whereby a first exposure produced by conventional photolithographic techniques generates a latent negative image in a photoresist etch mask layer (22), the image subsequently employed to modulate a second exposure generated by the multiple beam interferometric lithography technique. Periodic surface relief structures (80) patterned by the second exposure and formed after development of the exposed photoresist material, are restricted to regions (52) defined by the initial exposure, with the photoresist material (54) outside these regions remaining unmodulated, or devoid of the periodic structures (80), and suitable for use as a mask in a subsequent etching process.

Abstract: High density built-up multilayer printed circuit boards are produced by constructing microvias with photoimageable dielectric materials. A photosensitive dielectric composition on a conductive foil is laminated to conductive lines on a core. After imaging the foil and imaging and curing the photosensitive dielectric composition, vias are formed to the conductive lines. Thereafter the conductive lines are connected through the vias to the conductive foil, and then the conductive foil is patterned.

Abstract: The present invention lengthens gate conductors used in memory chips to limit leakage current, while still allowing the overall size of cells to remain the same. The channel length for each gate is increased by decreasing the size of spaces between gates. Decreases in space size occurs by using photolithographic image enhancement techniques. These techniques allow the space between gate conductors to be smaller while the gate size increases. In addition, a groove may be added that additionally lengthens the effective channel length and provides an additional electrical shield to limit leakage current. These techniques lead to the same density memory cells for a given process with less leakage. Finally, if grooved gate structures are used, having a longer gate conductor allows a three sigma process to be used, which increases yields.

Abstract: The invention is a method for making a lead frame (30) having fine pitched lead frame leads (32). A first side of the lead frame material is etched to for the lead frame and define the lead frame leads and die pad, but the etch process does not etch completely through the lead frame material. The partially etched first side is then covered with a tape (31) or layer of photoresist (71). The second side of the lead fame material is then etched to complete the lead frame. The lead frame may then be plated.

Abstract: An integrated circuit and a method of removing photoresist is described. The process described uses a low oxygen gas or non-oxygen gas plasma that removes the photoresist and provides a protective surface layer over the low-k dielectric material. The low-k dielectric material is part of a dielectric stack. After exposure to the gas plasmas the integrated circuit is subjected to solvent.

Abstract: The present invention provides methods and apparatus for defining a single structure on a semiconductor wafer by spatial frequency components whereby some of the spatial frequency components are derived by optical lithography and some by interferometric lithographic techniques. Interferometric lithography images the high frequency components while optical lithography images the low frequency components. Optics collects many spatial frequencies and the interferometry shifts the spatial frequencies to high spatial frequencies. Thus, because the mask does not need to provide high spatial frequencies, the masks are configured to create only low frequency components, thereby allowing fabrication of simpler masks having larger structures. These methods and apparatus facilitate writing more complex repetitive as well as non-repetitive patterns in a single exposure with a resolution which is higher than that currently available using known optical lithography alone.

Abstract: An antireflective layer for use in semiconductor photolithography is fabricated of silicon nitride (Si1−x−yNxHy) in a plasma-enhanced chemical vapor deposition process using a gaseous mixture of ammonia, silane and nitrogen. By varying the process temperature and the ratio of ammonia to silane, acceptable values of the refractive index n and extinction coefficient k can be obtained. The silicon nitride layer produced by this technique etches rapidly and therefore allows the antireflective layer to be removed quickly, thereby minimizing the damage to the underlying structures in a semiconductor device.

Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and an amorphous silicon layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the amorphous silicon layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the amorphous silicon layer. The first etch step includes an etch chemistry that is selective to the amorphous silicon layer over the ultra-thin photoresist layer and the dielectric layer. The amorphous silicon layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.