Abstract: A mask fabrication and repair technique including multiple exposures is provided. In this multiple exposure technique, the first exposure can define the critical dimensions (CDs) of the shapes for the mask. A subsequent exposure can eliminate isolated defects and significantly reduce the size of defects proximate to the desired shapes on the mask. Because similar processes (i.e. forming, exposing, and developing a photoresist layer) are used for creating and repairing the mask, certain repair-related defects, such as phase and transmission defects, can be minimized. Wafer repair can also be performed using the same multiple exposure technique.

Abstract: A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.

Abstract: The present invention provides a method for forming a via (e.g., a trench, via or contact) in a substrate. The method, in one embodiment of the invention, includes patterning an opening 220 in a photoresist layer 210 located over an intermediate layer located over a substrate. In that particular embodiment the opening 220 has a predetermined width 230. The method may further include etching into the intermediate layer 120 such that an intermediate opening 310 is formed, the intermediate opening 310 having a decreasing width that terminates at a targeted width 320 less than the predetermined width 230. Additionally, the method may include continuing the etching within the intermediate opening 310 and at least partially into the substrate 110 to form a via opening 510 in the substrate. In this particular embodiment, the width 520 of the via opening 510 is substantially equal to the targeted width 320.

Abstract: A dual damascene process is disclosed which reduces capacitance increases caused by excess and unnecessary remnants of an etching stop layer and which also improves multi-level interconnect structures by removing the etching stop layer except for a portion that surrounds the via hole. This reduces or eliminates capacitance increase and avoids erosion of underlying interlayer insulating layers during formation of an upper, wider trench.

Abstract: Provided is a method of forming a fine pattern, in which a silicon oxide layer is formed on a photoresist pattern and dry etching is performed on the resultant structure. According to the method, a photoresist pattern is formed on a material layer on which a fine pattern is to be formed, a silicon oxide layer is conformally deposited on the photoresist pattern without damaging the photoresist pattern, and dry etching is performed on a lower layer. During the dry etching, spacers are formed along the sidewalls of the photoresist pattern, and then, a polymer layer is formed on the photoresist pattern. Accordingly, it is possible to prevent the thinning of the photoresist pattern so that a desired pattern can be obtained, and further, to prevent striation or wiggling from occurring on the patterned material layer.

Abstract: A manufacturing method for a MOSFET gate structure. The method comprises providing a substrate, sequentially depositing a pad layer and a dielectric layer thereon, defining a gate trench passing through the dielectric layer and the pad layer to expose a predetermined gate area of the substrate, sequentially forming a gate dielectric layer, a first conductive layer, a second conductive layer, and a cap layer on the exposed substrate in the gate trench to form a damascene gate structure, and removing the dielectric layer.

Abstract: A method of fabricating a polysilicon film by an excimer laser crystallization process is disclosed. First, a substrate with a first region, a second region surrounding the first region, and a third region is provided. An amorphous silicon film is formed on the substrate. A photo-etching process is performed to remove parts of amorphous silicon film in the third region to form an alignment mark. Then, a mask layer is formed on the amorphous silicon film and a second photo-etching process is performed to remove the mask layer in the first region to expose the amorphous silicon film in the first region. After that, an excimer laser irradiation process is performed so that the amorphous silicon film in the first region is crystallized and becomes a polysilicon film.

Abstract: Method and apparatus for etching a metal layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for processing a photolithographic reticle including positioning the reticle on a support member in a processing chamber, wherein the reticle comprises a metal photomask layer formed on a silicon-based substrate, and a patterned resist material deposited on the silicon-based substrate, etching the substrate with an oxygen-free processing gas, and then etching the substrate with an oxygen containing processing gas.

Abstract: A method of fabricating a semiconductor multilevel interconnect structure employs a dual hardmask technique in a dual damascene process. The method includes using amorphous carbon as a first hardmask layer capable of being etched by a second etch process, and a second hardmask layer capable of being etched by a first etch process, as a dual hardmask. By virtue of the selective etch chemistry employed with the dual hardmask, the method affords flexibility unattainable with conventional processes. The via is never in contact with the photoresist, thus eliminating residual photoresist at the trench/via edge and the potential “poisoning” of the intermetal dielectric layer. Since trench/via imaging is completed before further etching, any patterning misalignments can be easily reworked. Because the amorphous carbon layer and the second hardmask layer are used as the dual hardmask, the photoresist can be made thinner and thus optimized for the best imaging performance.

Abstract: An electrode film and a protective electrode film are formed on an insulating film and a first magnetic film in turn. Then, a first photoresist layer, an intermediate layer and a second photoresist layer are formed on the protective electrode film in turn. The intermediate layer is formed by a sputtering method so that the surface temperature of the intermediate layer is set to 140° C. or below. Then, the first photoresist layer is exposed and developed, to fabricate a photoresist pattern. Then, the intermediate layer is partially etched and removed via the photoresist pattern as a mask by a reactive ion etching method using a chlorine-based gas.

Abstract: A carbon containing masking layer is patterned to include a plurality of container openings therein having minimum feature dimensions of less than or equal to 0.20 micron. The container openings respectively have at least three peripheral corner areas which are each rounded. The container forming layer is plasma etched through the masking layer openings. In one implementation, such plasma etching uses conditions effective to both a) etch the masking layer to modify shape of the masking layer openings by at least reducing degree of roundness of the at least three corners in the masking layer, and b) form container openings in the container forming layer of the modified shapes. Capacitors comprising container shapes are formed using the container openings in the container forming layer. Other implementations and aspects are disclosed.

Abstract: A structure and method for forming a tamper respondent electronic circuit enclosure that includes an integrated circuit structure, a mesh structure surrounding the integrated circuit structure, and a sealed enclosure surrounding the mesh structure. The mesh structure includes a layer of flexible dielectric having a first side and a second side, a screen-printed pattern of flexible electrically conductive first circuit lines forming a first resistor network on the first side, and a photo lithographically-formed pattern of flexible electrically conductive second circuit lines forming a second resistor network on the second side.

Abstract: A method of etching a noble metal electrode layer disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.35 ?m and having a noble metal profile equal to or greater than about 80°. The method comprises heating the substrate to a temperature greater than about 150° C., and etching the noble metal electrode layer by employing a high density inductively coupled plasma of an etchant gas comprising a gas selected from the group consisting of nitrogen, oxygen, a halogen (e.g., chlorine), argon, and a gas selected from the group consisting of BCl3, HBr, and SiCl4 mixtures thereof. Masking methods and etching sequences for patterning high density RAM capacitors are also provided.

Abstract: A thin film to be milled is formed on a substrate 1, and thereafter, a polymethylglutarimide layer and a photoresist layer are coated. Then, the photoresist layer is exposed and developed via a given mask, to form a pre-resist pattern. Then, ashing treatment is performed for the pre-resist pattern to a narrowed resist pattern. Subsequently, the thin film to be milled is milled via the resist pattern to obtain a patterned thin film.

Abstract: An arbitrary gap between the two chips of a MEMS device arranged in a flip-chip arrangement is achieved by etching into a first substrate to form mesas which act as spacers between which, or even on which, any required circuit elements are formed. Points of a layer at a first surface of the second substrate within which MEMS structures are made are bonded to the mesas of the first substrate. The second substrate is then removed, leaving the structures bonded to the mesas. The mesas may be formed by placing a hard mask, such as silicon oxide, which defines the desired pattern of mesas on the first substrate, and then etching the unmasked portion of the substrate using a mixture of potassium hydroxide (KOH) with isopropanol (IPA) or, tetramethyl ammonium hydroxide (TMAH) mixed with a surfactant, e.g., nonylphenol ethoxy ether or other equivalent compounds.

Abstract: The invention provides a method for making ink feed vias in semiconductor silicon substrate chips for an ink jet printhead and ink jet printheads containing silicon chips made by the method. The method includes applying a first photoresist material to a first surface side of the chip. The first photoresist material is patterned and developed to define at least one ink via location therein. An etch stop material is applied to a second surface side of the chip. At least one ink via is anisotropically etched with a dry etch process through the thickness of the silicon chip up to the etch stop layer from the first surface side of the chip. As opposed to conventional ink via formation techniques, the method significantly improves the throughput of silicon chip and reduces losses due to chip breakage and cracking. The resulting chips are more reliable for long term printhead use.

Abstract: A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.

Abstract: A photosensitive composition for sandblasting comprising the components of: (A) a photopolymerizable urethane (meth)acrylate oligomer comprising (meth)acryloyl group; (B) an acrylic copolymer; and (C) a photopolymerization initiator, wherein the component (B) comprises, as a monomer unit, one of copolymerizable monomers comprising one of a benzene ring and a cyclohexyl group.

Abstract: A method for exposing a semiconductor wafer in an exposer includes applying a first resist layer on a layer covering an alignment mark. A microscope measuring instrument, which has a visible and an ultraviolet light source, uses the visible light source for aligning the wafer and uses the ultraviolet light source for exposing a region in the first resist layer above the alignment mark without using a mask to free expose the alignment marks. The semiconductor wafer is then developed, the alignment mark is etched free and covered again with a second resist, which is exposed in an exposer in order to transfer a mask structure following an alignment with the alignment mark. The capacity of expensive exposers is thus advantageously increased, and microscope measuring instruments can be used multifunctionally, for example for the free exposure and for the detection of defects.

Abstract: There are provided steps of forming a lower resist layer on a patterning objective layer, forming an organic intermediate layer made of organic material, that contains no Si—O bond in its structure, on the lower resist layer, forming an upper resist layer made of alicyclic resin on the organic intermediate layer, forming a pattern by exposing/developing the upper resist layer, transferring the pattern of the upper resist layer onto the organic intermediate layer by etching the organic intermediate layer while using the upper resist layer as a mask, transferring a pattern of the organic intermediate layer onto the lower resist layer by etching the lower resist layer while using the organic intermediate layer as a mask, and etching the patterning objective layer while using the lower resist layer as a mask.

Abstract: In the halftone region of a photomask, uniformity in thickness of the photoresist is enhanced. The halftone region of the photomask is arranged such that a transmitting portion and a shielding portion are alternately provided to form a transmitting/shielding pattern. The transmitting portion at the end of the transmitting/shielding pattern has a larger area than the other transmitting portion.

Abstract: To provide a liquid crystal display apparatus exhibiting optimum display performance despite reduction in the number of PR(photolithography) processes, and a method for producing the apparatus. A method for producing a liquid crystal display apparatus having a first substrate including a thin film transistor and a reflector on an insulating substrate. An etching mask is formed on a metal layer formed on the insulating substrate and, using this etching mask, the metal layer is etched to form a constituent portion of the thin film transistor and protrusions. Only the etching mask is caused to reflow to cover exposed surface portions of the constituent portion of the thin film transistor and protrusions and near-by surface portions of the insulating substrate with the etching mask as the insulating substrate is partially exposed. Using the etching mask, recesses are formed in an exposed area of the insulating substrate. A reflector is formed on the protrusions and recesses.

Abstract: The present invention aims to provide a method of manufacturing a semiconductor device having an SOI structure, which is capable of setting an etching process so as to cause contact etching to widely have a process margin even in a semiconductor elemental device using an extra-thin SOI layer. The present method is a method of manufacturing a fully depleted-SOI device. A cobalt layer is formed on an SOI layer. Cobalt is transformed into a cobalt silicide layer by heat treatment. An interlayer insulating film is formed on the cobalt silicide layer, and a contact hole is defined in the interlayer insulating film by dry etching. As an etching gas used in such a dry etching step, a CHF3/CO gas is used. An etching condition is set through the use of a dry etching rate held substantially constant by use of the etching gas. Described specifically, etching time is suitable set.

Abstract: Improved methods for forming multilayer circuit structures are disclosed. In some embodiments, conductive layers, dielectric layers and conductive posts can be formed on both sides of a circuitized core structure. The conductive posts are disposed in the dielectric layers and can be stacked to form a generally vertical conduction pathway which passes at least partially through a multilayer circuit structure. The formed multilayer circuit structures can occupy less space than corresponding multilayer circuit structures with stacked via structures.

Abstract: A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.

Abstract: A method of forming a silicon carbide layer for use in integrated circuits is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a nitrogen source in the presence of an electric field. The as-deposited silicon carbide layer incorporates nitrogen therein from the nitrogen source.

Abstract: Disclosed is an in-situ process that prevents pattern collapse from occurring after they have been etched in S02-containing plasmas. The developed process involving treating the etched wafer to another plasma comprising of a chemically reducing gas such as H2. This treatment chemically reduces the hygroscopic sulfites/sulfates left on the surface after the main etch step. The lower sulfite/sulfate concentration on the wafer translates into considerably less moisture pick up and prevents high aspect ratio feature collapse.

Abstract: The present invention uses a double exposure and double etching method to improve critical dimension uniformity. A coating layer is formed on a wafer that includes a first area and a second area. The first area and the second area are separately patterned with different processing conditions. By means of this two-stage patterning, the CD uniformity between wafer center and wafer edge is successfully improved over the conventional single-stage patterning process. The fabrication yield is thus enhanced.

Abstract: A method of forming a device feature using an extreme ultraviolet (EUV) imaging layer (or a sub-deep ultraviolet imaging layer) and one or more other masks layers. The method includes forming a device feature layer; forming a photoresist layer over the device feature layer; forming a contact mask layer (CML) over the photoresist layer; forming an extreme ultraviolet (EUV) imaging layer over the CML; forming a first opening through the EUV imaging layer to expose a first underlying region of the CML; forming a second opening through the CML to expose a second underlying region of the photoresist layer, wherein the second opening is situated directly below the first opening; forming a third opening through the photoresist layer to expose a third underlying region of the device feature layer, wherein the third opening is situated directly below the second opening; forming a fourth opening through the device feature material layer, wherein the fourth opening is situated directly below the third opening.

Abstract: A method of protecting a sensitive layer from harsh chemistries. The method includes forming a first sensitive layer, forming a second layer upon the first layer, then forming a third layer over the second layer. The third layer is utilized as a mask during patterning of the second layer. During patterning, however, the second layer is only partially etched, thus leaving a buffer layer overlying the first layer. The third layer is completely removed while the buffer layer protects the first layer from the harsh chemicals that are utilized to remove the third layer. Then, the buffer layer is carefully removed down to the surface of the first layer.

Abstract: Disclosed is a micro-pattern forming method for a semiconductor device comprising: sequentially forming first and second insulation films on a semiconductor substrate; forming a photosensitive film on the second insulation film; dry etching the second insulation film; removing the photosensitive film; forming a third insulation film on the substrate; forming a fourth insulation film on a resultant structure; etching the third and fourth insulation films using a proper formal solution; etching the third insulation film using the fourth and second insulation films as masks to form a third insulation film pattern; and filling a conductive film into spaces between the second and third insulation films and second flattening the conductive film to form conductive lines.

Abstract: During the patterning of a semiconductor layer, an N-free SiOx layer is produced under an acid-forming photoresist layer in order to prevent a resist degradation. The Si content of the grown SiOx layer being varied in order to set a desired extinction coefficient k and a desired refractive index n. The SiOx layer formation is effected by a vapor phase deposition, SiH4 and O2 being used as starting gases.

Abstract: The present invention provides a method for forming a via (e.g., a trench, via or contact) in a substrate. The method, in one embodiment of the invention, includes patterning an opening 220 in a photoresist layer 210 located over an intermediate layer located over a substrate. In that particular embodiment the opening 220 has a predetermined width 230. The method may further include etching into the intermediate layer 120 such that an intermediate opening 310 is formed, the intermediate opening 310 having a decreasing width that terminates at a targeted width 320 less than the predetermined width 230. Additionally, the method may include continuing the etching within the intermediate opening 310 and at least partially into the substrate 110 to form a via opening 510 in the substrate. In this particular embodiment, the width 520 of the via opening 510 is substantially equal to the targeted width 320.

Abstract: In a semiconductor memory device and a method of fabricating the same, a semiconductor memory device having a transistor and a data storing portion includes a heating portion interposed between the transistor and the data storing portion and a metal interconnection layer connected to the data storing portion, wherein the data storing portion includes a chalcogenide material layer, which undergoes a phase change due to a heating of the heating portion, for storing data therein.

Abstract: The status of a plurality of service orders is summarized. A first data set that includes a plurality of records corresponding to service orders, such as requests for initiation of telephone or other communications services, is imported into a database application. At least one query or test may be executed on the first data set to generate a second data set that includes at least part of the first data set and one or more labels that have been appended to at least some of the plurality of records in the first data set. This second data may be imported into a spreadsheet application so that the spreadsheet application can automatically generate a summary of at least some of the data contained in the second data set.

Abstract: A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.

Abstract: A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Abstract: A method for manufacturing a polysilicon type thin film transistor comprises the steps of forming a polysilicon layer on a substrate, forming a gate insulating layer on the polysilicon layer, forming a gate layer on the gate insulating layer, forming a gate pattern by patterning, implanting impurities in the substrate over which the gate pattern is formed, forming a cover layer over the substrate in which impurities are implanted, and thermally annealing the substrate over which the cover layer is formed. In the invention, the thermal annealing is carried out instead of a costly laser annealing after the impurity implantation.

Abstract: An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed and, on the basis of a reflective layer which is located under the photoresist layer, additionally exposed areas are exposed completely. In consequence, a first etching mask which is used for etching a substrate can be renewed by a second etching mask in that a photoresist layer which is applied to the first etching mask or instead of the first etching mask is exposed such that areas which have been exposed once are not yet completely exposed, and areas which have been additionally exposed on the basis of a reflective layer which is located under the photoresist layer and corresponds to the first etching mask are exposed completely.

Abstract: The present invention relates to an overlay mark used for the measurement of the overlay accuracy between layered patterns and alignment at the time of exposure; which has a grooved pattern surrounding a mark pattern that is formed by engraving a groove or an indent in a prescribed position on a layer where a circuit pattern is formed so as to protect this mark pattern from being deformed by thermal expansion or contraction of this layer. The present invention enables to form a multi-layered circuit pattern with a high accuracy and a high yield in production, even in the formation of a minute and densely-spaced circuit pattern.

Abstract: The invention provides a microfabrication process which may be used to manufacture a MEMS device. The process comprises depositing one or a stack of layers on a base layer, said one layer or an uppermost layer in said stack of layers being a sacrificial layer; patterning said one or a stack of layers to provide at least one aperture therethrough through which said base layer is exposed; depositing a photosensitive layer over said one or a stack of layers; and passing light through said at least one aperture to expose said photosensitive layer.

Abstract: Disclosed is a method for forming a fine pattern of a semiconductor device in which the spacing between neighboring lines is reduced to be less than the resolution limit of a lithographic process. The method includes the steps of: (a) sequentially forming a base layer to be patterned, a lower photoresist layer, a blocking layer and an upper photoresist layer on a substrate; (b) forming the first photoresist pattern on the upper photoresist layer, and etching the blocking layer according to the first photoresist pattern; (c) forming the second photoresist pattern on the lower photoresist layer, which is opened by the spacing of the first photoresist pattern, wherein the spacing of the first photoresist pattern is greater than a line width of the second photoresist pattern; (d) etching the base layer using the second photoresist pattern as a mask; and (e) stripping the remaining photoresist layer.

Abstract: A method if provided for improving a photolithographic patterning process in a dual damascene process by forming a resinous plug in a via opening to prevent out diffusion of nitrogen containing species from a low-k IMD layer in subsequent lithographic patterning and RIE etching processes to form a trench opening formed substantially over the via opening.

Abstract: This invention provides a lithographic process for multi-etching steps by using single reticle, wherein the develop step is performed next to a bake step after the photoresist layer has been exposed, such that a photoresist residue is formed on the peripheral region around a transformed pattern of the photoresist. Because the photoresist residue has thinner thickness compared to the photoresist layer, this kind of developed photoresist layer can be used as the very mask for multi-etching steps.

Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride layer on a semiconductor substrate on which a predetermined pattern is formed. The silicon nitride layer includes a plurality of bonds formed between silicon and nitrogen. A portion of the bonds formed between silicon and nitrogen is broken to form at least one free bonding site on a surface of the silicon nitride layer. A silane compound and a flow fill method are used to form a silicon oxide layer on the silicon nitride layer.

Abstract: Acid-catalyzed positive resist compositions suitable for bilayer or multilayer lithographic applications are enabled by the use of a combination of (a) an acid-sensitive imaging polymer, (b) a radiation-sensitive acid generator, and (c) a non-polymeric silicon additive. The imaging polymer is preferably imageable with 193 nm or shorter wavelength imaging radiation. The resist compositions preferably contain at least about 5 wt. % silicon based on the weight of the imaging polymer. The compositions generally provide reduced line edge roughness compared to conventional silicon-containing resists.

Abstract: The silicon-containing resist compositions which have low silicon outgassing and high resolution lithographic performance, especially in bilayer or multilayer lithographic applications using 193 nm or shorter wavelength imaging radiation are enabled by the presence of an imaging polymer having silicon-containing, non-acid-labile pendant groups. The resist compositions of the invention are preferably further characterized by the substantial absence of silicon-containing acid-labile moieties.

Abstract: A method for forming a structure element in a layer arranged on a wafer by a trimming mask set, a developing step, and an etching step for the transfer of the structure pattern are carried out between the exposure steps carried out by the masks. Consequently, edges that are incipiently exposed below a limit value for the structure formation around the resist structures in a first resist layer, which are exposed using a first mask of the set, are transferred dimensionally accurately into an underlying layer on the wafer. Then, the exposure postprocesses the pattern of the first mask using a second mask of the set, the trimming mask, into a second, subsequently applied second resist layer.

Abstract: An electronic circuit is manufactured by the following method. Elements are formed on a front surface of a substrate, and then, a recess is formed around each of the element in the front surface of the substrate. Then, a portion of the substrate is removed from a back surface of the substrate until reaching the bottom of the recess. In the method, the elements are separated at once by removing the portion of the substrate from the back surface, and thus, the elements are manufactured efficiently.

Abstract: A gate insulating (GI) layer, an amorphous silicon layer, and a metal layer are sequentially formed on a gate formed on a substrate of a thin film transistor liquid crystal display (TFT LCD). A first photoresist layer and a second photoresist layer with an opening are then sequentially formed on the metal layer. Two etching processes are performed to form a source and a drain of the TFT LCD thereafter. Finally, a passivation layer is formed to cover the substrate.