Abstract: Forming a protective layer such as chromium, chrome alloys, nickel or cobalt as a cap over an aluminum film protects an underlying ITO layer from corrosion during the fabrication of flat panel displays such as field emission devices and the like. The presence of the protective layer during fabrication processes such as photolithography prevents diffusion of solutions through the aluminum into the ITO. This protective layer is especially effective during the development and resist stripping stages of photolithography which use solutions or solvents that would otherwise cause reductive corrosion of ITO in contact with aluminum. The methods and apparatus described herein are particularly advantageous for the fabrication of flat panel displays such as field emission devices and other display devices, because ITO is often used in such devices in contact with aluminum while exposed to corrosion-inducing media.

Abstract: A polymer used for a negative type resist composition having a first repeating unit of a Si-containing monomer unit, a second repeating unit having a hydroxy group or an epoxy ring and copolymerized with the first repeating unit is provided.

Abstract: A process and related structure are disclosed for using photo-definable layers that may be selectively converted to insulative materials in the manufacture of semiconductor devices, including for example dynamic random access memories (DRAMs), synchronous DRAMs (SDRAMs), static RAMs (SRAMs), FLASH memories, and other memory devices. One possible photo-definable material for use with the present invention is plasma polymerized methylsilane (PPMS), which may be selectively converted into photo-oxidized siloxane (PPMSO) through exposure to deep ultra-violet (DUV) radiation using standard photolithography techniques. According to the present invention, structures may be formed by converting exposed portions of a photo-definable layer to an insulative material and by using the non-exposed portions in a negative pattern scheme, or the exposed portions in a positive pattern scheme, to transfer a pattern into to an underlying layer.

Abstract: A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.

Abstract: A photosensitive material is coated on an insulating material (13) stacked on a substrate (1) (FIG. 16A), and exposed and developed using a mask having a light-shielding film capable of controlling a light transmittance from 100% to 0% annularly and continuously to form a spiral photosensitive material (FIG. 16B). After conducting treatment at a high temperature, the insulating material under the photosensitive material is spirally formed by etching (FIG. 16C). A metal (12) is stacked on the substrate (FIG. 16D), and a photosensitive material is coated (FIG. 16E). The photosensitive material is exposed and developed using a mask having an annular light-shielding film with a light transmittance of 0% to leave the photosensitive material covering only the metal on the base of the spiral structure (FIG. 16F). After treatment at a high temperature is conducted and the metal exposed is etched (FIG. 16G), the photosensitive material is removed (FIG. 16H).

Abstract: A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.

Abstract: The invention provides a method for making ink feed vias in semiconductor silicon substrate chips for an ink jet printhead and ink jet printheads containing silicon chips made by the method. The method includes applying a first photoresist material to a first surface side of the chip. The first photoresist material is patterned and developed to define at least one ink via location therein. An etch stop material is applied to a second surface side of the chip. At least one ink via is anisotropically etched with a dry etch process through the thickness of the silicon chip up to the etch stop layer from the first surface side of the chip. As opposed to conventional ink via formation techniques, the method significantly improves the throughput of silicon chip and reduces losses due to chip breakage and cracking. The resulting chips are more reliable for long term printhead use.

Abstract: A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (<20° C.), high density oxygen and argon plasma and intense UV radiation is used to simultaneously trim and harden a photoresist linewidth in an ICP chamber. As an alternative, a UV hardening step can be performed in a flood exposure tool prior to the ICP plasma etch. Another option is to perform the argon plasma treatment first to harden the resist and then in a second step apply an oxygen plasma to trim the photoresist. Vertical and horizontal etch rates are decreased in a controllable manner which is useful for producing gate lengths in MOS transistors of less than 100 nm. The process can also be used to controllably increase a space width in a photoresist feature.

Abstract: Disclosed herein is a method for inductor An Improved Structure For the Endpiece of Tape Rule of the high frequency integrated passive devices in which a spiral inductor pattern is formed on an insulation substrate, the spiral inductor pattern is spirally coiled outwards from the center. A thick film dielectric layer made of bisbenzocyclobutene (BCB) is formed on the spiral inductor pattern. A metal layer can be formed according to under bump metallization technique (UBM). The metal layer is either formed into a continuous spirally coiled form or a spread discrete configuration. With this structure, laser trimming can be applied to the metal layer pattern so as to acquire an ideal inductance value, thereby achieving wafer level trimming and compensating the process tolerance.

Abstract: A method of determining overlay layers utilizing advanced lithographic materials utilizes a post-etch overlay metrology. After etching, a relatively opaque layer is removed so that registration markers such as trench isolation structures can be observed. Lithographic parameters associated with the process can be adjusted in accordance with the observations. In a preferred embodiment, an overlay error is determined and adjustments are made to the reduce the overlay error.

Abstract: In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.

Abstract: A method of manufacturing a semiconductor device is provided. In one example, the method includes fabricating holes and/or trenches in organosiloxane insulating film without damaging the film by ashing and without causing a problem of shape deterioration or obstacles. The method comprising forming a second insulating film and a inorganic thin film soluble to a dissolving solution on an organosiloxane insulating film, fabricating the organosiloxane insulating film using the inorganic thin film as a hard mask, and removing the hard mask after fabrication by a dissolving solution.

Abstract: In a method for forming a photoresist pattern, a method for forming a capacitor, and a capacitor manufactured using the same, a light is selectively irradiated onto a selected portion of a photoresist film formed on a substrate. An interfered light generated from the irradiated light is transmitted through other portions of the photoresist film except a ring-shaped portion of the photoresist film having a predetermined width along a boundary of the selected portion. The photoresist film is exposed using the interfered light and the light irradiated onto the selected portion. A cylindrical photoresist pattern having a minute width may be formed through developing the photoresist film. With the cylindrical pattern, the capacitor can be easily formed.

Abstract: A technique for etching with a single layered patterned photomask at wavelengths of 193 nanometers or less. Specifically, a method for etching a bottom anti-reflectant coating layer that utilizes a combination of CF4, CH2F2, and O2 to produce a stabilized pattern in the photoresist layer. The etching process results in a structure with a defined pattern having minimal defects and that maintains integrity through the remainder of the etching.

Abstract: One example of a separation-material composition for a photo-resist according to the present invention comprises 5.0 weight % of sulfamic acid, 34.7 weight % of H2O, 0.3 weight % of ammonium 1-hydrogen difluoride, 30 weight % of N,N-dimethylacetamide and 30 weight % of diethylene glycol mono-n-buthyl ether. Another example of a separation-material composition for a photo-resist according to the present invention comprises 1-hydroxyethylidene-1, 3.0 weight % of 1-diphosphonic acid, 0.12 weight % of anmonium fluoride, 48.38 weight % of H2O and 48.5 weight % of diethylene glycol mono-n-buthl ether.

Abstract: A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed. Thereby, a trench is formed over the via hole.

Abstract: A method and corresponding article of manufacture are provided for manufacturing a semiconductor device with contact holes of the same step formed by two photolithography processes, where the manufacture includes forming a photoresist pattern by a first photolithography process on an insulating interlayer in which a first contact hole is formed, the photoresist pattern covering the first contact hole, etching the insulating interlayer to form a second contact hole by using the photoresist pattern as an etching mask, partially removing the photoresist pattern to remove an etch by-product from the second contact hole, and performing a process on the second contact hole by using the photoresist pattern residue as a mask to thereby decrease the number of photo processes and simplify the manufacturing process.

Abstract: Method of forming a magnetic memory device are disclosed. In one embodiment, a first plurality of conductive lines are formed over a semiconductor workpiece. A plurality of magnetic material lines are formed over corresponding ones of the first plurality of conductive lines and a second plurality of conductive lines are formed over the semiconductor workpiece. The second plurality of conductive lines cross over the first conductive lines and the magnetic material lines. These second lines can be used as a mask to while the magnetic material lines are patterned.

Abstract: In a process for forming a photoresist mask, a photoresist layer is applied to a substrate. A silyated layer is formed in the photoresist layer. The features of the silyated area correspond to the features of a photoresist mask to be formed. The photoresist layer is then etched to form a photoresist base beneath the silyated area. The photoresist base is etched to remove material from its sides such that it becomes narrower than the silyated area. The silyated area is then removed, leaving a photoresist mask on the substrate.

Abstract: A droplet/electrospray device and a liquid chromatography-electrospray system are disclosed. The droplet/electrospray device comprises a substrate defining a channel between an entrance orifice on an injection surface and an exit orifice on an ejection surface, a nozzle defined by a portion recessed from the ejection surface surrounding the exit orifice, and an electrode for application of an electric potential to the substrate to optimize and generate droplets or an electrospray. A plurality of these electrospray devices can be used in the form of an array of miniaturized nozzles. The liquid chromatography-electrospray device comprises a separation substrate defining an introduction channel between an entrance orifice and a reservoir and a separation channel between the reservoir and an exit orifice, the separation channel being populated with separation posts perpendicular to the fluid flow.

Abstract: A method for transferring patterns. After a patterned photoresist is formed on a substrate, the patterned photoresist is hardened, and the pattern of the hardened patterned photoresist is transferred into the substrate. Moreover, a popular method to harden is the silylation process, it is acceptable to only harder the top of the patterned photoresist or to harden both the top and the sidewall of the patterned photoresist. Besides, it is optional to change the thickness and the critical dimension of the patterned photoresist before it is hardened. Significantly, because the etch resistance of hardened patterned photoresist is higher than that of the non-hardened patterned photoresist, the method can improve any defect induced by etched photoresist during the pattern transferring process. Similarly, because a thinner non-hardened photoresist is available for the method, a smaller critical dimension of the patterned photoresist is available for the method while the photolithography technology being not improved.

Abstract: An organic bottom antireflective composition containing an aromatic polymer compound, a thermal cross-linking agent, and an organic solvent is provided. The aromatic polymer compound has a functional group that absorbs exposure light of a short wavelength of less than about 248 nm and is thermally cross-linkable and de-crosslinkable by acid hydrolysis. The thermal cross-linking agent causes a thermal cross-linking reaction by reacting with the functional group of the aromatic polymer compound. The organic bottom antireflective composition is soluble in a photoresist developer. When the organic bottom antireflective composition is-applied to a photolithography and etching process, a layer formed of the organic bottom antireflective composition can be developed together with a photoresist layer into a pattern in a development process following photoresist exposure and baking processes.

Abstract: A method for creating a phase shift photomask which includes a layer of hard mask material, the inclusion of which improves the uniformity of critical dimensions on the photomask by minimizing the affect of macro and micro loading. The method for producing the phase shift photomask of the instant invention includes two etching processes. The first etching process etches the layer of hard mask, and the second etching process etches opaque material (and anti-reflective layer, if used) and phase shift layers.

Abstract: Silica dielectric films, whether nanoporous foamed silica dielectrics or nonporous silica dielectrics are readily damaged by fabrication methods and reagents that reduce or remove hydrophobic properties from the dielectric surface. The invention provides for methods of imparting hydrophobic properties to such damaged silica dielectric films present on a substrate. The invention also provides plasma-based methods for imparting hydrophobicity to both new and damaged silica dielectric films. Semiconductor devices prepared by the inventive processes are also provided.

Abstract: A photolithographic process that involves building a sandwich photoresist structure. A first photoresist layer is formed over a substrate. An anti-reflection layer is formed over the first photoresist layer. A second photoresist layer is formed over the anti-reflection layer. A first photo-exposure is conducted and the exposed second photoresist layer is developed to pattern the second photoresist layer and the anti-reflection layer. Using the second photoresist layer and the anti-reflection layer as a mask, a second photo-exposure and a second photoresist development are conducted to pattern the first photoresist layer.

Abstract: A Si-containing water-soluble polymer layer is formed on a resist pattern, and contacting portions of the resist pattern and the Si-containing water-soluble polymer layer are reacted to form Si-containing material layers. Thereafter, the portions of the Si-containing water-soluble polymer layer, which have not reacted with the resist pattern, are removed using deionized water so that Si-containing material layers encompassing the resist pattern remain. Since such Si-containing material layers improve the etching resistance and the thickness of the resist pattern, the semiconductor material having a step difference can be etched. In addition, a CD of the adjacent resist pattern can be increased. Furthermore, since an etching resistance against an electron-beam improves, the shrinkage of the CD when measuring the CD using an in-line scanning electron microscope (ILS) is prevented so that the CD can be maintained.

Abstract: The present invention discloses a method for forming a semiconductor device which increases capacitance by forming a structure of a trench capacitor and uses an inner side face of the capacitor as a capacitor region.

Abstract: A desired pattern is formed in a photoresist layer that overlies a semiconductor wafer using a reflective mask. This mask is formed by consecutively depositing a reflective layer, an absorber layer and an anti-reflective (ARC) layer. The ARC layer is patterned according to the desired pattern. The ARC layer is inspected to find areas in which the desired pattern is not achieved. The ARC layer is then repaired to achieve the desired pattern with the absorber layer protecting the reflective layer. The desired pattern is transferred to the absorber layer to reveal the reflective portion of mask. Radiation is reflected off the reflective mask to the semiconductor wafer to expose the photoresist layer overlying the semiconductor wafer with the desired pattern.

Abstract: Provided is a process for creating vias for a circuit assembly including the steps of (a) applying a curable coating composition to a substrate, some or all of which is electrically conductive, to form an uncured coating thereon; (b) applying a resist over the uncured coating; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the uncured coating; (e) removing the exposed areas of the uncured coating; and (f heating the coated substrate of step (e) to a temperature and for a time sufficient to cure the coating. Also disclosed is a process of fabricating a circuit assembly.

Abstract: Provided is a process for creating a via through a substrate including the steps of (a) providing a substantially void-free film of a curable composition; (b) applying a resist onto the curable film; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the curable film; (e) removing the exposed areas of the curable film to form holes through the curable film; and (f) heating the curable film of step (e) to a temperature and for a time sufficient to cure the curable composition. Also disclosed is a process of fabricating a circuit assembly which includes building patterned circuit layers upon a substrate that has vias provided by the aformentioned process.

Abstract: After films composing a TFT are laminated on an insulating substrate, a resist mask having a plurality of regions with different film thicknesses is formed by patterning on the uppermost layer of the above-stated films. Then, a conductor film is formed by patterning with a liftoff method using this resist mask. Alternatively, using other resist mask having a plurality of regions with different film thicknesses as an etching mask, a plurality of material films among the laminated material films are processed in succession. By the above-stated new pattern forming method and the processing method, the liquid crystal display device, which has been manufactured by five photolitho processes in a conventional art is manufactured by two or three photolitho processes.

Abstract: A method for manufacturing a circuit board having a conductive via comprises the steps of providing a substrate having a first surface and a first conductive layer on at least one region of the first surface, forming an insulating layer on the first conductive layer, forming an opening in the insulating layer, so that the opening extending to the first conductive layer, forming a second conductive layer inside the opening and at least on the insulating layer near the opening, applying a positive photoresist on the second conductive layer, exposing the positive photoresist, developing the exposed positive photoresist, and removing the positive photoresist on the second conductive layer, except a portion of the second conductive layer that is inside the opening, etching the second conductive layer, to expose a surface of the second conductive layer, removing the positive photoresist from inside the opening, and forming a third conductive layer inside the opening.

Abstract: A negative resist composition and a method for patterning semiconductor devices using the composition are provided. The negative resist composition contains an alkali-soluble hydroxy-substituted base polymer, a silicon-containing crosslinker having an epoxy ring, and a photoacid generator. In the method for patterning semiconductor devices, fine patterns are formed according to a bi-layer resist process using the negative resist composition.

Abstract: A manufacturing method for a MOSFET gate structure. The method comprises providing a substrate, sequentially depositing a pad layer and a dielectric layer thereon, defining a gate trench passing through the dielectric layer and the pad layer to expose a predetermined gate area of the substrate, sequentially forming a gate dielectric layer, a first conductive layer, a second conductive layer, and a cap layer on the exposed substrate in the gate trench to form a damascene gate structure, and removing the dielectric layer.

Abstract: A method of forming a system on chip(SOC) comprising read only memory(ROM) and nitride read only memory(NROM) by utilizing nitride read only memory. The method is to form a plurality of field oxide layers on a surface of a substrate in order to define an active area of each device. An ONO dielectric layer is then formed on the surface of the substrate, thereafter performing a photolithography and ion implantation process to form a plurality of N-type bit lines and P-type pocket doping areas in the substrate inside the memory area. After that, an etching process is performed in order to remove regions of the ONO dielectric layer in the periphery area and regions of the ONO dielectric layer in the memory area, optionally. After that, a thermal oxidation process is utilized in order to form a buried drain oxide layer atop each bit line and a gate oxide layer on the surface of the active area in the periphery area, respectively.

Abstract: A negative resist composition and a patterning method for semiconductor devices using the composition are provided. In one aspect, a negative resist composition comprises an alkali-soluble base polymer having an epoxy ring substituent, a silicon-containing crosslinker having multiple hydroxy groups, and a photoacid generator. In another aspect, a patterning method includes using the negative resist composition in a bi-layer resist process to form fine patterns.

Abstract: A manufacturing method of ceramic device comprising the steps of forming by layer accumulation of a lower electrode, a piezoelectric/electrostrictive layer, and an upper electrode on a substrate using a mixture of photosensitive resin and metal or piezoelectric/electrostrictive ceramic; and patterning by light exposure at a single time, thereby, producing a ceramic device of high shape ratio can be produced and precision degree is very high so as to produce a ceramic device very precise in arrangement between layers or with infrastructure so that another effect may be made to systematically prevent the short between upper and lower electrodes.

Abstract: An etch barrier to be used in a photolithograph process is disclosed. A silicon rich etch barrier is deposited on a substrate using a low energy deposition technique. A diamond like carbon layer is deposited on the silicon rich etch barrier. Photoresist is then placed on this etch barrier DLC combination. To form photolithographic features, successive steps of oxygen and flourine reactive ion etching is used.

Abstract: Provided is a method of manufacturing a printed wiring board which keeps a good etching factor of formed circuits, eliminates an etching residue and can effectively prevent the occurrence of surface layer migration.

Abstract: A method of forming openings on a semiconductor wafer comprising an initial step of providing a first film layer over the semiconductor wafer. A first opening in the first film layer is created by transferring an image of the first opening from a photoresist layer into the first film layer using an etching procedure. The first opening includes horizontal and vertical surfaces and has first width and height dimensions. After removing the photoresist layer, a second film layer is deposited over the first film layer and the opening such that the opening has a second width and height dimension which is less than the first width and height dimension. The second film layer is then anisotropically etched from the horizontal surface of the first film layer, and the horizontal surface of the opening such that the opening includes the first height dimension and the second width dimension.

Abstract: A method for manufacturing a photomask is provided. A transparent substrate is provided and a mask layer is formed thereon. A resist layer is formed on the mask layer and then patterned and defined to define a critical dimension of the photomask. A third layer is deposited over the patterned and defined resist layer to decrease the critical dimension of the photomask. And the third layer and the mask layer are etched afterwards.

Abstract: A desirable pattern is formed in a photoresist layer that overlies a semiconductor wafer using an attenuating phase shift reflective mask. This mask is formed by consecutively depositing an attenuating phase shift layer, a buffer layer and a repairable layer. The repairable layer is patterned according to the desirable pattern. The repairable layer is inspected to find areas in which the desirable pattern is not achieved. The repairable layer is then repaired to achieve the desirable pattern with the buffer layer protecting the attenuating phase shift layer. The desirable pattern is transferred to the buffer layer and then transferred to the attenuating phase shift layer to achieve the attenuating phase shift reflective mask. Radiation is reflected off the attenuating phase shift reflective mask to the photoresist layer to expose it with the desirable pattern.

Abstract: A method of fabricating a semiconductor multilevel interconnect structure employs a dual hardmask technique in a dual damascene process. The method includes using amorphous carbon as a first hardmask layer capable of being etched by a second etch process, and a second hardmask layer capable of being etched by a first etch process, as a dual hardmask. By virtue of the selective etch chemistry employed with the dual hardmask, the method affords flexibility unattainable with conventional processes. The via is never in contact with the photoresist, thus eliminating residual photoresist at the trench/via edge and the potential “poisoning” of the intermetal dielectric layer. Since trench/via imaging is completed before further etching, any patterning misalignments can be easily reworked. Because the amorphous carbon layer and the second hardmask layer are used as the dual hardmask, the photoresist can be made thinner and thus optimized for the best imaging performance.

Abstract: A dual damascene process using a single photo mask in which a photo mask having patterns with different transparency is applied. A mask layer with a dual layer opening is formed first and then serves as an etching mask to form a dual opening in the dielectric layer. Then a metal layer is filled in the dual layer opening in the dielectric layer to form a dual damascene structure. Therefore, only a single photolithography process is necessary and overlay due to misalignment can be avoided.

Abstract: A method including forming a photoimageable material on a substrate; developing the photoimageable material over an opening area, the photoimageable material over a first portion of the opening area developed to a first extent and the photoimageable material over a second portion of the opening area developed to a different second extent; removing developed photoimageable material from the opening area; and forming an opening in the substrate in the opening area.

Abstract: A method for improving a photolithographic patterning process in a dual damascene process including providing at least one via opening in a substrate including a low dielectric constant material; blanket depositing a photo-sensitive resinous layer to fill the at least one via opening; partially removing the photo-sensitive resinous layer to form an at least partially filled via plug; photo-curing the via plug such that an activating light source causes a polymer cross-linking chemical reaction; and, forming a trench line opening disposed substantially over the at least one via opening using a trench line photoresist to pattern the trench line opening.

Abstract: A resist pattern of a resist film is formed by exposing the resist film using a gate electrode forming mask (a Levenson phase shift mask), and developing the resist film. An antireflection film is etched using the resist pattern as an etching mask, and the resist pattern and the antireflection film are trimmed. The manner of this trimming is not to etch a hard mask made of an inorganic material, but to etch the resist pattern and the antireflection film made of an organic material. Since a region consistent with a wiring pattern of the hard mask is covered by the resist pattern completely, breaking down and retraction of the wiring are prevented.

Abstract: Antireflective compositions characterized by the presence of an SiO-containing polymer having chromophore moieties and transparent moieties are useful antireflective hardmask compositions in lithographic processes. These compositions provide outstanding optical, mechanical and etch selectivity properties while being applicable using spin-on application techniques. The compositions of the invention are advantageously useful with shorter wavelength lithographic processes and/or have minimal residual acid content.

Abstract: A method of fabricating a lead frame. The method includes providing an electrically conductive layer having a pair of opposing major surfaces. A pattern is etched in the layer extending partially through the layer to form cavities with sidewalls in the layer. A patterned mask is provided on the etched layer including masking of the sidewalls. The layer is again etched within the cavities. The patterned mask is preferably a liquid photo resist and the electrically conductive layer is preferably one of a copper or copper-based material or ALLOY 42. The etch can take place from both major surfaces.

Abstract: A composite photoresist structure includes an first organic layer located on a substrate, a sacrificial layer located on the first organic layer, and a second organic layer located on the sacrificial layer. The first organic layer is made of materials that can be easily removed by plasma. Therefore, the surface of the substrate will not be damaged while transferring a predetermined pattern onto the substrate.