Named Electrical Device Patents (Class 430/319)
  • Patent number: 11119274
    Abstract: An optical waveguide includes a core extending in a transmission direction of light, a clad covering the core along the transmission direction, and a mixing layer containing a material for the core and a material for the clad on the interface between the core and the clad, and the mixing layer includes a plurality of regions each having a different thickness in the transmission direction.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 14, 2021
    Assignee: NITTO DENKO CORPORATION
    Inventors: Naoto Konegawa, Yuichi Tsujita
  • Patent number: 11018015
    Abstract: The invention provides: a composition for forming an organic film, the composition having high filterability and enabling formation of an organic film which has high pattern-curving resistance, and which prevents a high-aspect line pattern particularly finer than 40 nm from line collapse and twisting after dry etching; a method for forming an organic film and a patterning process which use the composition; and a substrate for manufacturing a semiconductor device, including the organic film formed on the substrate. The composition for forming an organic film includes a condensate (A), which is a condensation product of dihydroxynaphthalene shown by the following formula (1) and a condensation agent, or a derivative of the condensate (A). A sulfur content among constituent elements contained in the condensate (A) or the derivative of the condensate (A) is 100 ppm or less in terms of mass.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 25, 2021
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tsutomu Ogihara, Daisuke Kori, Seiichiro Tachibana, Yusuke Biyajima, Naoki Kobayashi, Kazumi Noda
  • Patent number: 10983438
    Abstract: An exposure apparatus that scans and exposes each of a plurality of areas on a glass substrate, by irradiating the substrate with an illumination light via a projection optical system and relatively driving the substrate with respect to the illumination light, is equipped with: a substrate holder that levitates and supports a first area of the substrate; a substrate carrier that holds the glass substrate levitated and supported by the substrate holder; an X coarse movement stage that drives the substrate holder; an X voice coil motor that drives the substrate carrier; and a controller that controls the X coarse movement stage and the X voice coil motor so that the substrate holder and the substrate carrier are driven, respectively, in scanning exposure. Accordingly, an exposure apparatus with improved position controllability of an object can be provided.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: April 20, 2021
    Assignee: NIKON CORPORATION
    Inventor: Yasuo Aoki
  • Patent number: 10967428
    Abstract: Disclosed herein are coated copper particles formed of copper cores that are surface coated with a coating composition comprising one or more conductive oxides. Further disclosed herein are electrically conductive adhesives (ECA) comprising: (a) organic binder, (b) surface coated copper particles, and optional (c) solvent.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: April 6, 2021
    Inventors: Minfang Mu, Dan Feng, Jose M. Rodriguez-Parada
  • Patent number: 10942444
    Abstract: Optical control modules for integrated circuit device patterning and reticles and methods including the same. The methods include exposing, via a reticle, initial and subsequent reticle exposure fields on a surface of a semiconductor substrate. The initial and subsequent reticle exposure fields pattern corresponding array regions and margin regions on the semiconductor substrate. The initial and subsequent reticle exposure fields partially overlap such that an initial optical control module (OCM), which is patterned during exposure of the initial reticle exposure field, and a subsequent OCM, which is patterned during exposure of the subsequent reticle exposure field, both are positioned within a single control module die. The reticles include reticles that can be utilized during the methods or that can form the integrated circuit devices. The integrated circuit devices include integrated circuit devices formed utilizing the methods or the reticles.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: March 9, 2021
    Assignee: NXP USA, INC.
    Inventors: Leendertjan Mekking, Johannes Cobussen, Antonius Hendrikus Jozef Kamphuis
  • Patent number: 10844167
    Abstract: A composition for forming a resist underlayer film that has a high dry etching rate, functions as an anti-reflective coating during exposure, and fills a recess having a narrow space and a high aspect ratio. A composition for forming a resist underlayer film has a copolymer having a structural unit of following formula (1), a cross-linkable compound, a cross-linking catalyst, and a solvent: wherein R1 and R2 are each independently a C1-3 alkylene group or a single bond, Z is an —O— group, a —S— group, or a —S—S— group, and Ar is an arylene group. The copolymer is synthesized by a reaction of a carboxyl group of a dicarboxylic acid compound having an —O— group, a —S— group, or a —S—S— group with an epoxy group of a diglycidyl ether compound having an arylene group.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 24, 2020
    Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Hiroto Ogata, Yuki Usui, Mamoru Tamura, Takahiro Kishioka
  • Patent number: 10824071
    Abstract: Multiple model functions may be calculated by detecting alignment marks on a semiconductor wafer structure. The model functions may be combined to determine a combined model function by using a weight function that assigns a different weight to each of basis functions of the model functions. Thus, even when asymmetry of alignment marks or overlay marks has high dependency on a horizontal location on a wafer, reliability of exposure process is insured.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moo-song Lee, Seung-yoon Lee
  • Patent number: 10824073
    Abstract: A radiation-sensitive resin composition includes a first compound represented by formula (1), a first polymer comprising an acid-labile group, and a radiation-sensitive acid generator other than the first compound. The radiation-sensitive acid generator includes an onium salt compound. In the formula (1), n is 2 or 3; m is 1 or 2; Y+ represents a monovalent radiation-sensitive onium cation; and L represents a single bond or an organic group having a valency of n. L includes linking moieties each linking two of the carboxylate groups in formula (1). Number of atom(s) included in a linking moiety having a minimum number of bonds among the linking moieties is 0 to 10. In a case where L represents a single bond, n is 2, and in a case where n is 2, m is 1.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: November 3, 2020
    Assignee: JSR CORPORATION
    Inventors: Katsuaki Nishikori, Hayato Namai
  • Patent number: 10651129
    Abstract: Some embodiments include provision of a mass of semiconductor material having a first region and a second region. A first pattern set is formed to extend across the first region, and a third pattern set is formed to extend across the second region. The first pattern set includes first lines and first trenches between the first lines. The third pattern set includes alignment marks. The first trenches are utilized to form rails from the semiconductor material within the first region. The alignment marks are parallel to the rails. A second pattern set is formed to extend across the first region, and a fourth pattern set is formed to extend across the second region. The second pattern set includes first openings, and the fourth pattern set includes second openings. The first openings are utilized to subdivide the rails into pillars. The second openings transform the alignment marks into an overlay pattern.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hideo Hironaka
  • Patent number: 10559463
    Abstract: A semiconductor structure is provided that contains a non-volatile battery which controls gate bias and has increased output voltage retention and voltage resolution. The semiconductor structure may include a semiconductor substrate including at least one channel region that is positioned between source/drain regions. A gate dielectric material is located on the channel region of the semiconductor substrate. A battery stack is located on the gate dielectric material. The battery stack includes, a cathode current collector located on the gate dielectric material, a cathode material located on the cathode current collector, a first ion diffusion barrier material located on the cathode material, an electrolyte located on the first ion diffusion barrier material, a second ion diffusion barrier material located on the electrolyte, an anode region located on the second ion diffusion barrier material, and an anode current collector located on the anode region.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Yun Seog Lee, Joel P. de Souza, Devendra K. Sadana
  • Patent number: 10490519
    Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 26, 2019
    Assignee: INTEL CORPORATION
    Inventors: Charles H. Wallace, Hossam A. Abdallah, Elliot N. Tan, Swaminathan Sivakumar, Oleg Golonzka, Robert M. Bigwood
  • Patent number: 10434707
    Abstract: A touch substrate manufactured by three-dimensional printing and a method for manufacturing the same are disclosed. The method for manufacturing the touch substrate works together with a three-dimensional printer. The three-dimensional printer includes a first nozzle, a second nozzle, and a light source. The method includes the steps of: jetting a photocuring material by the first nozzle and exposing the photocuring material to the light source to form a base layer; jetting a conductive material on the base layer by the second nozzle and exposing the conductive material to the light source to form a touch electrode layer; and jetting the photocuring material on the base layer and the touch electrode layer by the first nozzle and exposing the photocuring material to the light source to form a protective layer. The touch electrode layer is embedded between the base layer and the protective layer.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 8, 2019
    Assignee: TPK Universal Solutions Limited
    Inventors: Shun-Jie Yang, Shun-Ta Chien, Shih-Ching Chen, Wen-Fu Huang
  • Patent number: 10386297
    Abstract: The present application relates to a method for examining at least one element of a photolithographic mask for an extreme ultraviolet (EUV) wavelength range, wherein the method includes the steps of: (a) examining the at least one element with light in the EUV wavelength range; and (b) determining the behavior of the at least one element in the EUV wavelength range.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 20, 2019
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Jörg Frederik Blumrich, Johannes Ruoff
  • Patent number: 10324370
    Abstract: A manufacturing method of a circuit substrate is provided. A substrate is provided. A positive photoresist layer is coated on the substrate. Once exposure process is performed on the positive photoresist layer disposed on the substrate so as to simultaneously form concaves with at least two different depths.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: June 18, 2019
    Assignee: Unimicron Technology Corp.
    Inventors: Pu-Ju Lin, Shih-Lian Cheng, Yu-Hua Chen, Cheng-Ta Ko, Jui-Jung Chien, Wei-Tse Ho
  • Patent number: 10290551
    Abstract: The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10261413
    Abstract: Provided are a photocurable composition for imprints, having good releasability and temporal stability of the releasability, a pattern forming method, and a method for manufacturing a device. This photocurable composition for imprints includes a monofunctional chained aliphatic (meth)acrylate (A1) not containing a fluorine atom, a bifunctional or higher polyfunctional (meth)acrylate (A2) not containing a fluorine atom, a monofunctional (meth)acrylate (B) containing a fluorine atom, a photopolymerization initiator (C), and a non-polymerizable compound (D) having a polyoxyalkylene structure in a proportion of 1% to 5% by mass, in which the monofunctional chained aliphatic (meth)acrylate (A1) not containing a fluorine atom has a boiling point of 100° C. to 200° C. at a pressure of 0.67 kPa, and the monofunctional (meth)acrylate (B) containing a fluorine atom has a boiling point of 100° C. to 200° C. at a pressure of 0.67 kPa.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: April 16, 2019
    Assignee: FUJIFILM Corporation
    Inventors: Hirotaka Kitagawa, Yuichiro Goto
  • Patent number: 10263051
    Abstract: An organic light-emitting diode (OLED) touch-control substrate is provided. The organic light-emitting diode (OLED) touch-control substrate comprises a plurality of OLEDs, each of the OLEDs having a first electrode, a second electrode and a light-emitting layer between the first electrode and the second electrode; a plurality of first touch-control electrodes disposed in a same layer with the first electrodes and insulated from the first electrode lines; and a plurality of second touch-control electrodes disposed in a same layer with the second electrodes and insulated from the second electrode lines and the first touch-control electrodes.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: April 16, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Chengdu BOE Optoelectronics Technology Co., Ltd.
    Inventors: Xiangdan Dong, Weiyun Huang
  • Patent number: 10261426
    Abstract: An optimization method for overlay error compensation is disclosed.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 16, 2019
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Yunqing Dai, Jian Wang
  • Patent number: 10249859
    Abstract: A battery built-in board includes a battery component comprising a battery and an insulation part covering the battery, a first insulation layer in which the battery component is placed, and a second insulation layer formed on the first insulation layer and covering the battery component. Rigidity of the insulation part is lower than that of the first insulation layer and the second insulation layer.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: April 2, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kazuyuki Kubota
  • Patent number: 10214415
    Abstract: A silicon carbide based MOS integrated circuit is monolithically integrated with a suspended piezoelectric aluminum nitride member to form a high-temperature-capable hybrid MEMS-over-MOS structure. In the integrated structure, a post-MOS passivation layer of silicon carbide is deposited over the MOS passivation and overlain by a structural layer of the MEMS device. Electrical contact to refractory metal conductors of the MOS integrated circuit is provided by tungsten vias that are formed so as to pass vertically through the structural layer and the post-MOS passivation layer.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 26, 2019
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Benjamin Griffin, Scott D. Habermehl, Peggy J. Clews
  • Patent number: 10175571
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: January 8, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xiangdong Chen, Hyeokjin Bruce Lim, Ohsang Kwon, Mickael Malabry, Jingwei Zhang, Raymond George Stephany, Haining Yang, Kern Rim, Stanley Seungchul Song, Mukul Gupta, Foua Vang
  • Patent number: 10156923
    Abstract: An in-cell touch display panel, a driving method thereof and a display device are provided. The display panel includes a common electrode layer and a plurality of touch sensing electrodes. The common electrode layer comprises a plurality of first touch driving electrodes and a plurality of second touch driving electrodes that are configured for loading of common electrode signals in a display period and for loading of touch signals in a touch period. The second touch driving electrodes include a plurality of second touch driving sub-electrodes. Projections of the touch sensing electrodes on an array substrate are at gaps of the second touch driving sub-electrodes that are adjacent within the second touch driving electrodes. With this display panel, the touch sensitivity can be enhanced.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: December 18, 2018
    Assignees: BOE TECHNOLOGY GROUP., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yingming Liu, Xue Dong, Haisheng Wang, Xiaoliang Ding, Shengji Yang
  • Patent number: 10074466
    Abstract: An NTC component comprising a first electrode (1) and a second electrode (2) is specified. The NTC component further comprises an NTC element (3) disposed between the first electrode (1) and the second electrode (2), wherein the NTC element (3) comprises a ceramic having the general composition AB2O4, and where A and B each comprise one or more of the materials Mn, Ni, Co and Cu, and B additionally comprises one or more of the materials Fe, Y, Pr, Al, In, Ga and Sb.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: September 11, 2018
    Assignee: EPCOS AG
    Inventor: Manfred Schweinzger
  • Patent number: 10056426
    Abstract: A light guide grid can include a grid structure having a plurality of intersecting grid lines, each grid line having a width w, and a plurality of openings for photosensor elements between intersecting grid lines. The grid structure has a diagonal grid width between two adjacent ones of the plurality of openings in a diagonal direction. The diagonal grid width has a value exceeding approximately ?3 w. An image sensor can include a light guide grid having a grid structure as described above and further include a micro-lens such as a sinking micro-lens and a color filter. A method of fabricating a light guide grid can include forming a grid above at least one photo sensor, the grid having intersecting grid lines of width w and a diagonal grid width in a diagonal direction having a value exceeding approximately ?3 w.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Volume Chien, I-I Cheng, Chi-Cherng Jeng
  • Patent number: 9984878
    Abstract: The present invention provides a resist under layer film composition containing a novolak resin having a repeating unit shown by the formula (1), wherein R represents a group containing one or more fluorine atoms. There is provided a resist under layer film composition that is excellent in filling property, generates little outgas, and has excellent dry etching resistance and heat resistance.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: May 29, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Hatakeyama, Daisuke Kori
  • Patent number: 9977342
    Abstract: A lithography stepper alignment and control method, comprising: providing a test template having a plurality of field sizes, and deriving a set of overlay values for each field size (S1); calculating a set of compensation amounts for the overlay value of each field size (S2); and, comparing a set of estimated alignment compensation values for a product with each compensation amount for each field size, selecting as the product alignment compensation values the set of compensation amounts of a field size closest to the set of estimated alignment compensation values, and, using the product alignment compensation values to perform alignment compensation on said product (S3).
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: May 22, 2018
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Zhenhai Yao
  • Patent number: 9972522
    Abstract: A processing apparatus for processing a substrate chucked by a chuck installed on a stage includes: a conveying unit configured to convey the substrate to the chuck; a robot configured to selectively convey, to the stage, a pressing member capable of pressing the substrate to reduce a warp of the substrate chucked by the chuck and a cleaning member capable of cleaning a chuck surface; and a controller configured to cause the robot holding the pressing member to execute pressing processing for correcting the warp of the substrate and cause the robot holding the cleaning member to execute cleaning processing of the chuck surface.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 15, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shinichi Hirano, Kohei Yamada
  • Patent number: 9928330
    Abstract: In a method of decomposing a layout of a semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines are crossed, among polygons included in the layout of the semiconductor device may be determined as a complex polygon. A first stitch may be inserted between the plurality of intersections on the complex polygon. A plurality of decomposed patterns may be generated by performing a pattern dividing operation on the layout.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: March 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Kwon Kang, Ji-young Jung, Dong-Gyun Kim, Jae-Seok Yang, Sung-Wook Hwang
  • Patent number: 9846361
    Abstract: A photosensitive conductive paste contains conductive particles (A), a photosensitive organic compound (B), an epoxy resin (C) and an ion adsorbent (D) that is selected from the group consisting of hydrotalcite, magnesium oxide, aluminum oxide, aluminum hydroxide, magnesium hydroxide, magnesium carbonate, zirconium oxide, magnesium silicate, silicon dioxide, zeolite and a carbon-based powder.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: December 19, 2017
    Assignee: Toray Industries, Inc.
    Inventors: Miharu Tanabe, Kazutaka Kusano
  • Patent number: 9768450
    Abstract: A method of fabricating a thin film battery may comprise: depositing a first stack of blanket layers on a substrate, the first stack comprising a cathode current collector, a cathode, an electrolyte, an anode and an anode current collector; laser die patterning the first stack to form one or more second stacks, each second stack forming the core of a separate thin film battery; blanket depositing an encapsulation layer over the one or more second stacks; laser patterning the encapsulation layer to open up contact areas to the anode current collectors on each of the one or more second stacks; blanket depositing a metal pad layer over the encapsulation layer and the contact areas; and laser patterning the metal pad layer to electrically isolate the anode current collectors of each of the one or more thin film batteries. For electrically non-conductive substrates, cathode contact areas are opened-up through the substrate.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: September 19, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Daoying Song, Chong Jiang, Byung-Sung Leo Kwak
  • Patent number: 9733532
    Abstract: The plurality of thin film transistors are provided corresponding to intersections between a plurality of gate wires and a plurality of source wires, respectively. The pixel electrodes are connected to the thin film transistors. The counter electrodes face the pixel electrodes. The leading line is provided outside a display area and connected to one of gate wires. The conversion portion is provided in the vicinity of the display area, at which the leading line is connected to another wiring layer. The insulating film is provided on the conversion portion at a side of the counter substrate. The conductive layer faces the conversion portion with the insulating film interposed therebetween and has transparency. To the conductive layer together with the counter electrodes, applied is a common potential.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: August 15, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazunori Okumoto
  • Patent number: 9733750
    Abstract: A touch panel and a method of fabricating the same are provided. The touch panel may include: a substrate; first sensing electrodes disposed on a first surface and arranged along a first direction and second sensing electrodes arranged along a second direction; at least one first connector connecting the first sensing electrodes in the first direction; a first insulating layer pattern disposed on the first connector; at least one second connector disposed on the first insulating layer pattern, intersecting the first connector, and connecting the second sensing electrodes in the second direction; and wires disposed on the first surface of the substrate in the peripheral area and electrically connected to the first sensing electrodes and the second sensing electrodes. The first connector includes a first light-transmitting conductive pattern disposed on the first surface of the substrate and a first light-blocking conductive pattern disposed on the first light-transmitting conductive pattern.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: August 15, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung Kyun Park, Cheol Kyu Kim, Ki Hyun Cho, Sun Haeng Cho, Kyung Seop Kim, Jae Neung Kim
  • Patent number: 9728407
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming mandrels over a material layer and forming spacers along sidewalls of mandrels, forming a patterned hard mask to cover a first region, depositing a filling layer in a second region while the patterned hard mask covers the first region. A space between two adjacent spacers in the second region is filled in by the filling layer. The method also includes recessing the filling layer to form a filling block in the space between two adjacent spacers in the second region, removing the patterned hard mask, removing mandrels and etching the material layer by using spacers and the filling block as an etch mask to form material features in the first region and the second region, respectively.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ken-Hsien Hsieh, Chi-Cheng Hung, Chih-Ming Lai, Wei-Liang Lin, Chun-Kuang Chen, Ru-Gun Liu
  • Patent number: 9703912
    Abstract: According to one embodiment, there is provided a mask set including a first mask and a second mask. The first mask includes a first device pattern and a first mark pattern. The first mark pattern is used for an inspection of a position of the first device pattern on a surface of the first mask. The second mask is used to perform multiple exposure on a substrate together with the first mask. The second mask includes a second device pattern and a second mark pattern. The second mark pattern is used for an inspection of a position of the second device pattern on a surface of the second mask. The second mark pattern includes a pattern corresponding to a pattern obtained by inverting the first mark pattern.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: July 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ai Furubayashi, Takashi Obara, Takaki Hashimoto, Nobuhiro Komine
  • Patent number: 9651864
    Abstract: An object of the present invention is to provide a negative resin composition which can produce a pattern with high sensitivity, high resolution and low line edge roughness in pattern formation by exposure to electron beams or EUV, a method for producing a relief pattern and an electronic component using the negative resist composition. Disclosed is a negative resist composition comprising a phenolic compound (A) which has: two or more phenolic hydroxyl groups per molecule; one or more substituents of one or more kinds selected from the group consisting of a hydroxymethyl group and an alkoxymethyl group per molecule in the ortho-position of any of the phenolic hydroxyl groups; and a molecular weight of 400 to 2,500, wherein the content of the phenolic compound (A) is 70% by weight or more of the total solid content of the negative resist composition.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: May 16, 2017
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Kenichi Okuyama, Satoru Kanke
  • Patent number: 9626472
    Abstract: A method of forming a layout design is disclosed. The method includes placing a first set of layout patterns in a first layout layer and placing a second set of layout patterns in a second layout layer. The first set of layout patterns is aligned with one or more grid lines of a first set of grid lines. The first set of grid lines extends along a first direction, where two grid lines of the first set of grid lines overlap two cell boundaries of a standard cell layout. The second set of layout patterns is aligned with one or more grid lines of a second set of grid lines. The second set of grid lines extends along the first direction and has at least two different line pitches, where two grid lines of the second set of grid lines overlap two cell boundaries of the standard cell layout.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: April 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Wei Chiang, Li-Chun Tien, Hui-Zhong Zhuang, Zhe-Wei Jiang
  • Patent number: 9624581
    Abstract: A composition that includes a high-valent compound of copper, silver or indium; a linear, branched or cyclic C1-18 alcohol; and a Group VIII metal catalyst forms a metal film of copper, silver or indium on a substrate when the composition is coated on the substrate and heated to reduce the high-valent compound. The composition may alternatively include metal particles of silver, copper or indium in which the surface layer of the particle includes a high-valent compound of copper, silver or indium. A metal film of copper, silver or indium may also be formed on a substrate by coating a substrate with the composition including the metal particles, and heating to reduce the high-valent compound in the same manner as above.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: April 18, 2017
    Assignees: TOSOH CORPORATION, SAGAMI CHEMICAL RESEARCH INSTITUTE
    Inventors: Tetsu Yamakawa, Noriaki Oshima, Takahiro Kawabata, Tomoyuki Kinoshita, Toshio Inase
  • Patent number: 9600025
    Abstract: Disclosed is a touch panel. The touch panel includes a plurality of sensing electrode patterns spaced apart from each other on a substrate; and a bridge electrically connecting the sensing electrode patterns to each other, wherein an end portion of the bridge is perpendicular to a surface of the substrate or is inclined within a predetermined angle with respect to a perpendicular line of the surface of the substrate.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 21, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Dong Keon Lee, Ja Ram Kim, Jae Hong Lee, Jong Sun Kim, Bum Sun Hong
  • Patent number: 9590277
    Abstract: A power storage device having a small thickness is manufactured. A manufacturing method of the power storage device includes: forming a first layer and a second layer over a first substrate; forming a first insulating layer, a positive electrode and a negative electrode over the second layer; forming a solid electrolyte layer over the first insulating layer, the positive electrode, and the negative electrode; forming a sealing layer to cover the solid electrolyte layer; forming a planarization film and a support over the sealing layer; separating the first layer and the second layer from each other so that the second layer, the positive electrode, the negative electrode, the solid electrolyte layer, the sealing layer, the planarization film, and the support are separated from the first substrate; attaching the separated structure to a second substrate which is flexible; and separating the support from the planarization film.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: March 7, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Konami Izumi
  • Patent number: 9488912
    Abstract: In the method for forming a protective coat on an electrode for a touch panel according to the invention, a photosensitive layer comprising a photosensitive resin composition containing a binder polymer having a carboxyl group and an acid value of 30 to 120 mgKOH/g, a photopolymerizable compound having at least three ethylenic unsaturated groups, and a photopolymerization initiator, is formed on a base material having an electrode for a touch panel, prescribed sections of the photosensitive layer are cured by irradiation with active light rays and then the sections other than the prescribed sections are removed, to form a protective coat comprising the cured sections of the photosensitive resin composition covering all or a portion of the electrode.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: November 8, 2016
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Ikuo Mukai, Yasuharu Murakami, Naoki Sasahara, Hiroshi Yamazaki
  • Patent number: 9465465
    Abstract: A touchpad apparatus extends, without having to be covered by a cover, up to an outer housing edge of an operating device. In two possible cases, not only touchpads and connections between the touchpads in the touchpad area are formed by patterns of conductive strips which cannot be resolved by the human eye, but also contact connection lines which connect contact elements to each other at two sides of the touchpad area.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: October 11, 2016
    Assignee: PolyIC GmbH & CO. KG
    Inventors: Walter Fix, Andreas Ullmann, Manfred Walter
  • Patent number: 9448471
    Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: September 20, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Teng-Chin Kuo, Yuan-Chi Pai, Chun-Chi Yu
  • Patent number: 9360897
    Abstract: A touchscreen panel sensor film, with alignment marks or product information assigned thereto is formed so as to improve post-processing accuracy. The touchscreen panel sensor film includes a transparent base film and a transparent electrical conductor pattern provided on at least one surface of the base film, and achieves the improvement of post-processing accuracy by having alignment marks or product information in a non-active area on the sensor film.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: June 7, 2016
    Assignee: Dai Nippon Printing Co., Ltd
    Inventor: Masahiro Takahashi
  • Patent number: 9323092
    Abstract: A touch panel including a first substrate, plural first electrode lines and plural second electrode lines is provided. The first electrode lines and the second electrode lines are respectively arranged on the first substrate and extended along two different directions respectively. Each of the first electrode lines includes plural electrode pads and plural first connecting parts connected therebetween, wherein each of the first connecting parts has two end portions and a center portion, a width of each of the first connecting parts is decreased from the two end portions to the center portion, and corners of connections between the end portions and the corresponding electrode pads are smooth curved surfaces. The second electrode lines are electrically insulated with the first electrode lines, and perpendicular projections of each of the second electrode lines and the corresponding first connecting part on the first substrate are intersected to form an overlap region.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: April 26, 2016
    Assignee: HTC Corporation
    Inventors: Pi-Lin Lo, Yen-Cheng Lin, Yi-Fan Hsueh, Jui-Liang Chen, Yi-Cheng Li
  • Patent number: 9297958
    Abstract: An opto-electric hybrid board includes: an electric circuit board including an insulative layer, and an element mounting electrode formed on the front surface of the insulative layer; an optical element mounted on the element mounting electrode by contact frictional heat; and an optical waveguide including a first cladding layer in contact with the back surface of the insulative layer of the electric circuit board. Between the insulative layer and the first cladding layer, a reinforcing layer is provided at the portion corresponding to the element mounting electrode. A reinforcing layer is provided at the portion corresponding to the element mounting electrode, in the surface of the first cladding layer, which is on the side opposite to the insulative layer. The resin-made reinforcing layer is greater than the first cladding layer in storage modulus at the temperature of the board when the element is being mounted.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: March 29, 2016
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuichi Tsujita, Toshikazu Baba, Shotaro Masuda
  • Patent number: 9292148
    Abstract: The disclosure relates to a method of fabricating a capacitive touch pane where a plurality of groups of first conductive patterns are formed along a first direction, a plurality of groups of second conductive patterns are formed along a second direction, and a plurality of connection components are formed on a substrate. Each of the first conductive patterns is electrically connected to another adjacent first conductive pattern in the same group by each of the connection components and each of the plurality of groups of the second conductive patterns is interlaced with and insulated from each of the plurality of groups of the first conductive patterns. A plurality of curved insulation mounds are formed to cover the first connection components. A plurality of bridge components are formed to electrically connect each of the second conductive patterns with another adjacent second conductive pattern in the same group.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: March 22, 2016
    Assignees: INNOCOM TECHNOLOGY (SHENZHEN) CO., LTD., INNOLUX CORPORATION
    Inventors: Chao-Sung Li, Lien-Hsin Lee, Kai Meng
  • Patent number: 9196500
    Abstract: A method for manufacturing semiconductor structures includes providing a substrate having a plurality of mandrel patterns and a plurality of dummy patterns, simultaneously forming a plurality of first spacers on sidewalls of the mandrel patterns and a plurality of second spacers on sidewalls of the dummy patterns, and removing the second spacers and the mandrel patterns to form a plurality of spacer patterns on the substrate.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: November 24, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Po-Chao Tsao, Chia-Jui Liang, Chien-Ting Lin
  • Patent number: 9128339
    Abstract: The present disclosure relates to an ultra high-resolution liquid crystal display having a compensating thin film transistor at each pixel. The present disclosure suggests a thin film transistor substrate comprising: gate lines running in horizontal direction and data lines running in vertical direction which define a plurality of pixel area on a substrate; a first gate electrode and a second gate electrode formed by dividing any one gate line disposed at any one of an upper side and a lower side; a first thin film transistor connected to the first gate electrode; and a second thin film transistor connected to the first thin film transistor and the second gate electrode. The flat panel display according to the present disclosure has an ultra high-density resolution over 300PPI with the high aperture ratio.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: September 8, 2015
    Assignee: LG Display Co., Ltd.
    Inventor: Jungil Lee
  • Patent number: 9081278
    Abstract: A photosensitive conductive paste includes a dicarboxylic acid or an acid anhydride thereof (A); a compound (B) having an acid value of 40 to 200 mg KOH/g; an alicyclic compound (C); a photopolymerization initiator (D); and a conductive filler (E).
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: July 14, 2015
    Assignee: Toray Industries, Inc.
    Inventors: Tsukuru Mizuguchi, Satoshi Matsuba, Kazutaka Kusano
  • Patent number: 9069247
    Abstract: The present invention provides a silicon-containing surface modifier containing one or more repeating units each represented by the following general formula (A), or one or more partial structures each represented by the following general formula (C): It is aimed at providing a resist lower layer film which is usable for a resist pattern formed of a hydrophilic organic compound to be obtained in a negative development.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: June 30, 2015
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tsutomu Ogihara, Takafumi Ueda, Yoshinori Taneda