Radiation Mask Patents (Class 430/5)
  • Patent number: 9950349
    Abstract: Systems and methods for rinsing one or more pellicles during fabrication, including immersing and soaking the one or more pellicles in a rinse bath solution for a particular time period, forming a top layer above the rinse bath solution, the top layer having a lower surface tension than the rinse bath, and withdrawing the one or more pellicles through the top layer for drying.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: April 24, 2018
    Assignee: Internationa Business Machines Corporation
    Inventor: Dario L. Goldfarb
  • Patent number: 9946170
    Abstract: The present disclosure provides a method for exposure and development, a system for controlling exposure and a system for exposure and development. The method for exposure and development is configured to expose and develop a substrate when the substrate having a size larger than that of a mask. The method includes: exposing and developing a plurality of different regions of the substrate by means of the mask respectively, wherein the plurality of different regions are pieced to form an entire region which needs to be exposed and developed.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: April 17, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xuequan Yu, Xianhua Xu, Zhi Liu, Zhiqiang Wang, Wei Zhang, Xuepei Cheng
  • Patent number: 9946155
    Abstract: A method is provided for fabricating a photolithographic mask. The method includes providing a transparent substrate; and forming an opaque layer on the transparent substrate. The method also includes writing layout patterns with at least one sub-resolution assistant feature with non-uniform size along a longitudinal direction to increase an adhesion force between the sub-resolution assistant feature with non-uniform size along the longitudinal direction and the transparent substrate in the opaque layer. Further, the method include cleaning residual matters generated by writing the layout patterns in the opaque layer. Further, the method also includes spin-drying the transparent substrate with the layout patterns and the sub-resolution assistant feature with non-uniform size along the longitudinal direction.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: April 17, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Boxiu Cai, Yi Huang
  • Patent number: 9946150
    Abstract: One embodiment of the present invention provides a light reflection type lithography mask including: a substrate; and a reflection layer. The reflection layer is formed on the substrate, and has a first pattern and a second pattern as viewed from above. The second pattern is located so as to be closest to one of one side and the other side of the first pattern in a first direction. A reflectivity at a portion corresponding to the first pattern is different from a reflectivity at a portion corresponding to the second pattern.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: April 17, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Kosuke Takai
  • Patent number: 9946152
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to modified surfaces of extreme ultraviolet lithography photomasks and methods of manufacture. The structure includes a reflective surface having a patterned design, and a black border region at edges of the patterned design. The black border region includes a modified surface morphology to direct light away from reaching a subsequent mirror.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: April 17, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Zhengqing John Qi, Christina A. Turley, Jed H. Rankin
  • Patent number: 9939724
    Abstract: A photolithography method and system based on a high step slope are provided. The method includes: S1, manufacturing a sacrificial layer with a high step slope on a substrate; S2, adopting a spin-on PR coating process to cover the sacrificial layer with a photoresist layer to form a photolithographic layer; S3, forming a mask pattern and a compensation pattern on a mask; and S4, performing photolithography processes, by a photolithography machine, on the photolithographic layer. By forming a slope-top compensation pattern and a slope compensation pattern on a mask to perform photolithography on the substrate of a sacrificial layer, a relatively wide compensation pattern is set in a part of the top of the slope with a small thickness, thereby compensating the overexposure at the top of the slope, reducing the error in the photolithographic pattern, and improving the precision of photolithography of the high step slope.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: April 10, 2018
    Assignee: CSMC TECHNOLOGIES FABI CO., LTD.
    Inventor: Jiale Su
  • Patent number: 9933698
    Abstract: To provide a phase-shift mask in which the reduction in thickness of a light-shielding film is provided when a transition metal silicide-based material is used for the light-shielding film and by which the problem of ArF light fastness can be solved; and a mask blank for manufacturing the phase-shift mask. A mask blank 10 comprises a phase-shift film 2 and a light-shielding film 4 on a transparent substrate 1, the phase-shift film 2 is made of a material with ArF light fastness, and at least one layer in the light-shielding film 4 is made of a material which contains transition metal, silicon, and nitrogen, and satisfies the conditions of Formula (1) below: CN?9.0×10?6×RM4?1.65×10?4×RM3?7.718×10?2×RM2+3.611×RM?21.084??Formula (1) wherein RM is a ratio of the content of transition metal to the total content of transition metal and silicon in said one layer, and CN is the content of nitrogen in said one layer.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: April 3, 2018
    Assignee: HOYA CORPORATION
    Inventors: Atsushi Matsumoto, Hiroaki Shishido, Takashi Uchida
  • Patent number: 9927697
    Abstract: Provided is a mask blank, including: a resist layer formed by a chemically amplified resist; a protective layer formed to coat the resist layer; and a buffer layer provided between the resist layer and the protective layer, wherein the protective layer contains an acidic substance, a basic substance, and a salt generated by a reaction between the acidic substance and the basic substance, and the buffer layer has a portion which is a surface layer portion of a pre-coated resist layer before being coated by the protective layer, and in which the pre-coated resist layer and the protective layer 4 are in contact with each other, and this portion is formed by receiving the acidic substance, the basic substance, and the salt moved from the protective layer 4.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: March 27, 2018
    Assignee: HOYA CORPORATION
    Inventors: Takahiro Hiromatsu, Masahiro Hashimoto
  • Patent number: 9927694
    Abstract: A pattern data generation method includes setting drawing pattern data based on design pattern data including first and second pattern regions. The drawing pattern data includes third and fourth pattern regions. The method includes setting the width of the third pattern region to a third width. The method includes setting first and second irradiation amount data based on the drawing pattern data. The method includes calculating a first thickness of the first pattern region and a second thickness of the second pattern region based on the first irradiation amount data, and calculating a third thickness of the third pattern region based on the second irradiation amount data. The method includes calculating, based on the first to third widths and the first to third thicknesses, a range of a first exposed region exposed onto a patterning substrate.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: March 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Kunihiro Ugajin
  • Patent number: 9927696
    Abstract: Embodiments disclosed herein relate to an exposure pattern alteration software application which manipulates exposure polygons having lines with angles substantially close to angles of symmetry of a hex close pack arrangement, which suffer from long jogs. Long jogs present themselves as high edge placement error regions. As such, the exposure pattern alteration software application provides for line wave reduction by serrating polygon edges at affected angles to reduce edge placement errors during maskless lithography patterning in a manufacturing process.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: March 27, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Joseph R. Johnson, Christopher Dennis Bencher, Thomas L. Laidig
  • Patent number: 9927695
    Abstract: In a halftone phase shift mask blank comprising a transparent substrate and a halftone phase shift film thereon, the halftone phase shift film is composed of a silicon base material consisting of silicon, nitrogen and 0-6 at % of oxygen, has a refractive index n of at least 2.4, an extinction coefficient k of 0.4-0.7, and a thickness of 40-67 nm. The halftone phase shift film is thin enough to be advantageous for photomask pattern formation, has chemical resistance against chemical cleaning, and maintains a necessary phase shift for phase shift function and a necessary transmittance for halftone function.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 27, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Takuro Kosaka, Yukio Inazuki
  • Patent number: 9927698
    Abstract: A method and system for: forming a first rectangular shape with photomask writing equipment, using a first sub-threshold dosage on a photoresist layer of a photomask substrate; forming an overlapping second rectangular shape with the photomask writing equipment using a second sub-threshold dosage on the photoresist layer, the second rectangular shape being rotated relative to the first rectangular shape to form one of: a hexagonal overlap area and an octagonal overlap area, that exposes the photoresist layer to at least a threshold dosage; and forming a photomask, based on developing the exposed photoresist layer, to provide optical transmission corresponding to the one of: the hexagonal overlap area of at least the threshold dosage and the octagonal overlap area of at least the threshold dosage, for use by a photolithography system to write any of a contact, a via, or a curvilinear shape on an integrated circuit substrate.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: March 27, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jed H. Rankin, Adam C. Smith
  • Patent number: 9921466
    Abstract: Obtaining optimal focus for exposing a photoresist in an EUV lithography with an EUV mask containing a pattern with an assist feature is disclosed. The EUV mask contains a repeating pattern, wherein the repeating pattern has two different pitches, i.e. a first pitch and a second pitch, and contains an assist feature between main features. Because the two different pitches have different focus offsets, the difference between linewidths of said gratings provides a calibration curve which is a measure of focus. The method for monitoring focus is performing a EUV exposure using a focus position with a pre-determined focus position as calibrated using the linewidth difference between the two gratings. The EUV mask for monitoring focus of present invention is applicable to both test and product masks.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: March 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Allan Brunner, Martin Burkhardt
  • Patent number: 9921467
    Abstract: A mask blank and a mask are provided. The mask blank includes a substrate, and an etching stop layer embedded in the substrate. The mask includes the mask blank with the embedded etching stop layer, and a plurality of recesses formed in the mask blank. The recess exposes the embedded etching stop layer.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen
  • Patent number: 9921471
    Abstract: A method of forming a photonic device structure comprises forming a photoresist over a photonic material over a substrate. The photoresist is exposed to radiation through a gray-tone mask to form at least one photoexposed region and at least one non-photoexposed region of the photoresist. The at least one photoexposed region of the photoresist or the at least one non-photoexposed region of the photoresist is removed to form photoresist features. The photoresist features and unprotected portions of the photonic material are removed to form photonic features. Other methods of forming a photonic device structure, and a method of forming an electronic device are also described.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: March 20, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Roy E. Meade, Gurtej S. Sandhu
  • Patent number: 9914243
    Abstract: A mold base of an embodiment is a mold base for use in manufacture of a mold that has a porous alumina layer over its surface, including: a base; and an aluminum alloy layer provided on the base, wherein the aluminum alloy layer contains aluminum, a non-aluminum metal element, and nitrogen. The aluminum alloy layer of the mold base of an embodiment of the present invention has high specularity.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: March 13, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Akinobu Isurugi, Kiyoshi Minoura, Hiroyuki Sugawara
  • Patent number: 9915625
    Abstract: Methods and systems for detecting defects on a wafer are provided. One system includes one or more computer subsystems configured for generating a rendered image based on information for a design printed on the wafer. The rendered image is a simulation of an image generated by an optical inspection subsystem for the design printed on the wafer. Generating the rendered image includes one or more steps, and the computer subsystem(s) are configured for performing at least one of the one or more steps by executing a generative model. The computer subsystem(s)) are also configured for comparing the rendered image to an optical image of the wafer generated by the optical inspection subsystem. The design is printed on the wafer using a reticle. In addition, the computer subsystem(s) are configured for detecting defects on the wafer based on results of the comparing.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: March 13, 2018
    Assignee: KLA-Tencor Corp.
    Inventors: Lisheng Gao, Tao Luo, Keith Wells, Xiaochun Li
  • Patent number: 9911619
    Abstract: Methods for a lithographic process used to pattern fins for fin-type field-effect transistors (FinFETs). A first plurality of hardmask sections may be formed, and sacrificial spacers may be formed on vertical sidewalls of the first plurality of hardmask sections. Each of the first plurality of hardmask sections is comprised of a first material. Gaps between the sacrificial spacers are filled with a second material, which is selected to etch selectively to the first material, in order to define a second plurality of hardmask sections each comprised of the second material.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: March 6, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Hoon Kim, Catherine B. Labelle, Lars W. Liebmann, Chanro Park, Min Gyu Sung
  • Patent number: 9910349
    Abstract: A pellicle is proposed in which the agglutinant layer which enables the pellicle to adhere to a photomask is doped with a de-foaming agent which depends on a reactive fluorine-modified silicone oil for its anti-foaming performance, and typically such reactive fluorine-modified silicone oil has a vinyl group at both ends of its molecular chain.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: March 6, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Horikoshi, Yu Yanase
  • Patent number: 9910350
    Abstract: The present disclosure provides a method of repairing a mask. The method includes receiving a mask that includes a patterned feature, the patterned feature producing a phase-shift and having a transmittance; identifying a defect region on the mask; and forming a repair feature over the defect region on the mask, wherein forming the repair feature includes forming a first patterned material layer over the defect region and forming a second patterned material layer over the first patterned material layer to form the repair feature, the repair feature producing the phase-shift and having the transmittance.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: March 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Shang-Lun Tsai, Sheng-Chi Chin, Yuan-Chih Chu, Yueh-Hsun Li
  • Patent number: 9904757
    Abstract: A processor receives an integrated circuit design, divides the integrated circuit design into a test portion and a remaining portion, and adds sub-resolution assist features (SRAFs) having different size and spacing parameters to the test portion of the integrated circuit design to generate a single test pattern. Exposure and development equipment performs a single exposure and development process of the single test pattern to produce a single test photoresist. The processor analyzes the single test photoresist to determine which of the size and spacing parameters are unacceptable and which are acceptable, based on differences between the single test photoresist and a model photoresist that the test portion of the integrated circuit design without the SRAFs would produce. The processor adds SRAFs having the acceptable size and spacing parameters to the remaining portion of the integrated circuit design.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: February 27, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Amr Y. Abdo, Ioana Graur
  • Patent number: 9904164
    Abstract: A glass substrate for a mask blank has main surfaces. A root-mean-square surface roughness (RMS) in at least one main surface is 0.15 nm or less. An aspect ratio of a surface profile (Str) of the main surface in accordance with ISO 25178-2:2012, where s=0.2, is 0.30 or more. The aspect ratio is determined through measurement of the surface profile at measurement intervals of 0.2 nm or less in a measurement range of 100 nm×100 nm using an atomic force microscope.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: February 27, 2018
    Assignee: ASAHI GLASS COMPANY, LIMITED
    Inventor: Hiroshi Nakanishi
  • Patent number: 9897910
    Abstract: A method for forming a lithography mask includes forming a capping layer on a reflective multilayer layer, the capping layer comprising a first material, forming a patterned patterning layer on the capping layer, and introducing a secondary material into the capping layer, the secondary material having an atomic number that is smaller than 15.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: February 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Cheng Hsu, Chih-Cheng Lin, Ta-Cheng Lien, Wei-Shiuan Chen, Hsin-Chang Lee, Anthony Yen
  • Patent number: 9897908
    Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool is described. The BAA includes three distinct aperture arrays of different pitch.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventors: Yan A. Borodovsky, Donald W. Nelson, Mark C. Phillips
  • Patent number: 9897911
    Abstract: A halftone phase shift photomask blank is provided comprising a transparent substrate and a halftone phase shift film thereon having a phase shift of 150-200° and a transmittance of 9-40%. The halftone phase shift film consists of a transition metal, Si, O and N, has an average transition metal content of at least 3 at %, and is composed of a plurality of layers including a stress relaxation layer having an oxygen content of at least 3 at % and a phase shift adjusting layer having a higher oxygen content of at least 5 at %.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: February 20, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Takuro Kosaka
  • Patent number: 9891518
    Abstract: A mask, comprising an opaque region, a first semi-transparent region, and a second semi-transparent region. The transmittance of the second semi-transparent region is less than that of the first semi-transparent region. The mask solves the over-etching problem caused by the difference between the thicknesses of photoresist in different regions.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: February 13, 2018
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Deshuai Wang, Lianjie Qu
  • Patent number: 9891520
    Abstract: In a method for cleaning photo masks having patterns with smallest line-space dimensions below 200 nm, a surfactant composition A is used, wherein A contains at least three short-chain perfluorinated groups Rf selected from the group consisting of trifluoromethyl, pentafluoroethyl, 1-heptafluoropropyl, 2-heptafluoropropyl, and pentafluorosulfanyl and wherein A exhibits, at a 1% by weight aqueous solution, a static surface tension below 25 mN/m.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: February 13, 2018
    Assignee: BASF SE
    Inventors: Andreas Klipp, Andrei Honciuc, Chu-Ya Yang
  • Patent number: 9885962
    Abstract: Disclosed are apparatus and methods for determining overlay error in a semiconductor target. For illumination x-rays having at least one angle of incidence (AOI), a correlation model is obtained, and the correlation model correlates overlay error of a target with a modulation intensity parameter for each of one or more diffraction orders (or a continuous diffraction intensity distribution) for x-rays scattered from the target in response to the illumination x-rays. A first target is illuminated with illumination x-rays having the at least one AOI and x-rays that are scattered from the first target in response to the illumination x-rays are collected. An overlay error of the first target is determined based on the modulation intensity parameter of the x-rays collected from the first target for each of the one or more diffraction orders (or the continuous diffraction intensity distribution) and the correlation model.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: February 6, 2018
    Assignee: KLA-Tencor Corporation
    Inventors: Andrei Veldman, Michael S. Bakeman, Andrei V. Shchegrov, Walter D. Mieher
  • Patent number: 9885949
    Abstract: The disclosure is directed to a method for designing a lithographic mask to print a pattern of structural features, wherein an OPC-based methodology may be used for producing one or more simulated patterns as they would be printed through the optimized mask. A real mask is then produced according to the optimized design, and an actual print is made through the mask. To evaluate the printed pattern and the PW on wafer more accurately, experimental contours are extracted from the CD-SEM measurements of the printed pattern. The verification of the mask is based on a comparison between on the one hand the contour obtained from the printed pattern, and on the other hand the intended pattern and/or the simulated contour. A direct comparison can be made between simulation and experiment, without losing all the pieces of info contained in each single CD-SEM picture.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: February 6, 2018
    Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D
    Inventors: Julien Mailfert, Werner Gillijns
  • Patent number: 9881808
    Abstract: According to one embodiment, a mask includes a substrate, first and second pattern portions. The substrate includes a first surface, and the substrate is light transmissive. The first pattern portion includes first optical members. The first optical members are provided on the first surface. A light transmittance of the first optical members is lower than a light transmittance of the substrate. A distance between the adjacent two first optical members is a first distance. The second pattern portion includes second optical members. The second optical members are provided on the first surface. A light transmittance of the second optical members is lower than the light transmittance of the substrate. A distance between the adjacent two second optical members is a second distance. A first phase of a light penetrating the first pattern portion is different from a second phase of a light penetrating the second pattern portion.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 30, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Takashi Sato, Satoshi Tanaka
  • Patent number: 9880461
    Abstract: The present invention relates to a method for manufacturing a master mold, a master mold manufactured by the method, a method for manufacturing a transparent photomask, a transparent photomask manufactured by the method, and a method for manufacturing a conductive mesh pattern by using the transparent photomask.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: January 30, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Jeongho Park, Jinmi Jung, Yujin Jeong, Bu Gon Shin
  • Patent number: 9880426
    Abstract: A display panel and a manufacturing method thereof, a mask and a manufacturing method thereof, and a display device. The display panel includes a first display substrate and a second display substrate arranged to be opposed to each other, and main spacers and assistant spacers arranged between the first display substrate and the second display substrate. The main spacers and the assistant spacers are both arranged on the first display substrate. The main spacers have a height equal to a distance from the first display substrate to the second display substrate to support the first display substrate and the second display substrate. The assistant spacers have a height smaller than that of the main spacers. An end surface of a suspending end of at least one of the assistant spacers is planar and/or an end surface of a suspending end of at least one of the assistant spacers is convex.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: January 30, 2018
    Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Huifang Yuan
  • Patent number: 9874809
    Abstract: A pellicle for a reflective mask including a pellicle body, a light shielding pattern, a grating pattern, and a pellicle frame. The pellicle body includes a central region and a peripheral region, wherein the peripheral region surrounds the central region. The light shielding pattern is formed on the peripheral region of the pellicle body; the grating pattern is formed on the light shielding pattern, and the pellicle frame is located under the peripheral region of the pellicle body, and the pellicle frame is configured to support the pellicle body.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: January 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-min Park, Jin-hong Park, Myung-soo Hwang
  • Patent number: 9875334
    Abstract: An illustrative method includes providing a layout of at least a portion of a photomask, the layout comprising a plurality of target features, each target feature having a shape in accordance with a corresponding one of at least one target shape, for each of the target shapes, providing a local map specifying a respective value of a local sub-resolution assist feature (SRAF) usefulness for each of a plurality of positions relative to the target shape, generating a global usefulness map specifying a respective global SRAF usefulness for each of the plurality of positions relative to at least a portion of the photomask on the basis of the assignment of the values of the local SRAF usefulness.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 23, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Andrey Lutich
  • Patent number: 9870935
    Abstract: A monitoring and deposition control system and method of operation thereof including: a deposition chamber for depositing a material layer on a substrate; a sensor array for monitoring deposition of the material layer for changes in a layer thickness of the material layer during deposition; and a processing unit for adjusting deposition parameters based on the changes in the layer thickness during deposition.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: January 16, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Edward W. Budiarto, Majeed A. Foad, Ralf Hofmann, Thomas Nowak, Todd Egan, Mehdi Vaez-Iravani
  • Patent number: 9869939
    Abstract: A method for being used in a lithography process is provided. The method includes receiving a first mask, a second mask and a substrate with a set of baseline registration marks. A first set of registration marks is formed on the substrate using the first mask and a first exposure tool, and a first set of overlay errors is determined. The first set of registration marks is removed and a second set of registration marks is formed on the substrate using the second mask and a second exposure tool. A second set of overlay errors is determined. A set of tool-induced overlay errors is generated from the first and second sets of overlay errors and used in fabricating a third mask. The third mask can then be used in the lithography process to accommodate the overlay errors caused by different exposure tools, different masks, and different mask writers.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shinn-Sheng Yu, Anthony Yen
  • Patent number: 9869895
    Abstract: A coating device includes an upper stage, a lower stage and a spraying part. The upper stage masks an upper surface of a display panel. The lower stage masks a lower surface of the display panel. The spraying part sprays ink to a side surface of the display panel. The side surface of the display panel is exposed between the upper stage and the lower stage. The coating device includes the upper stage and the lower stage, so that the coating device may form a coating layer of uniform thickness by precisely spraying ink. In addition, a cross-section of the coating layer may be precisely formed having specific shape such as an L or C shape. A display apparatus having high light usage efficiency and reduced light leakage may be provided by using the coating device.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: January 16, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seok-Ho Lee, Min-Sung Kim, Ki-Su Jin, Jung-Min Hong
  • Patent number: 9864269
    Abstract: A photomask blank comprising a transparent substrate and a chromium-containing film is provided. The chromium-containing film is formed of a chromium compound containing Cr, N, and optionally O, has a total Cr+N+O content?93 at %, and meets the formula: 3Cr?2O+3N. A chromium compound layer meeting a first composition having a N/Cr atomic ratio?0.95, a Cr content ?40 at %, a Cr+N content?80 at %, and an O content?10 at % accounts for 10-70% of the overall thickness of the chromium-containing film.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 9, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Kouhei Sasamoto
  • Patent number: 9864266
    Abstract: A photomask blank comprising a transparent substrate and a chromium-containing film is provided. The chromium-containing film is constructed by one or more chromium compound layers which are formed of a chromium compound containing Cr, N and optionally O, and have a composition having a Cr content ?30 at % and a total Cr+N+O content ?93 at %, and meeting the formula: 3Cr?2O+3N. A chromium compound layer meeting a first composition having an N/Cr atomic ratio ?0.95, a Cr content ?40 at %, a total Cr+N content ?80 at %, and an O content ?10 at % is included to a thickness of more than 70% to 100% of the overall thickness of the chromium-containing film.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 9, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Kouhei Sasamoto, Yukio Inazuki
  • Patent number: 9857677
    Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having second sizes, and a plurality of bar-like third dummy patterns having varied third sizes. The pattern densities are smartly equalized by positioning the second dummy patterns.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
  • Patent number: 9857679
    Abstract: A mask includes a doped substrate having a first region, a second region and a third region. The doped substrate in the first region has a first thickness to define a first mask state and in the second region has a second thickness to define a second mask state. The second thickness is different than the first thickness. The mask also includes an absorption material layer disposed over the third region to define a border region.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Cheng Hsu, Ta-Cheng Lien, Tzu-Ling Liu
  • Patent number: 9851632
    Abstract: Disclosed is a phase-shift blankmask, in which a light-shielding film includes a metal compound and having a structure of a multi-layer film or a continuous film, which includes a first light-shielding layer and a second light-shielding layer. The second light-shielding layer has higher optical density at an exposure wavelength per unit thickness (?) than the first light-shielding layer. The first light-shielding layer occupies 70% to 90% of the whole thickness of the light-shielding film. With this, the blankmask secures a light-shielding effect, has an improved etching speed, and makes a resist film thinner, thereby achieving a fine pattern.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: December 26, 2017
    Assignee: S&S TECH CO., LTD.
    Inventors: Kee-Soo Nam, Cheol Shin, Chul-Kyu Yang, Jong-Hwa Lee, Min-Ki Choi, Chang-Jun Kim, Kyu-Jin Jang
  • Patent number: 9846358
    Abstract: A photomask includes a light transmission substrate, and a transfer pattern disposed over the light transmission substrate, a shape of the transfer pattern being transferred onto a wafer by an exposure process. The transfer pattern comprises a first transfer pattern having a closed loop shape and having a first thickness, and a plurality of second transfer patterns disposed in an opening surrounded by the first transfer pattern, the plurality of second transfer patterns being arrayed in a first direction such that adjacent second transfer patterns are spaced apart from each other by a first distance, the second transfer patterns having a second thickness which is less than the first thickness of the first transfer pattern.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: December 19, 2017
    Assignee: SK HYNIX INC.
    Inventor: Tae Joong Ha
  • Patent number: 9841668
    Abstract: A photomask includes a light transmission substrate having a transfer region and a frame region, a light-transmitting region exposing a portion of the light transmission substrate in the transfer region corresponding to a transfer pattern, a phase shift region surrounding the light-transmitting region in the transfer region. The phase shift region includes a first phase shift region surrounding the light-transmitting region and a second phase shift region surrounding the first phase shift region. A first phase shift pattern is disposed on the light transmission substrate in the first phase shift region, and a plurality of second phase shift patterns are disposed on the light transmission substrate in the second phase shift region.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: December 12, 2017
    Assignee: SK HYNIX INC.
    Inventor: Byung Ho Nam
  • Patent number: 9841669
    Abstract: The present invention relates to a method for manufacturing a conductive mesh pattern, a mesh electrode manufactured by the same, and a laminate.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: December 12, 2017
    Assignee: LG CHEM, LTD.
    Inventors: Jeongho Park, Bu Gon Shin, Jae Jin Kim, Jongbyung Lee, Jinmi Jung, Yujin Jeong
  • Patent number: 9835939
    Abstract: The present disclosure relates to a gray-tone mask (GTM) and the manufacturing method thereof. The GTM includes at least one first light-blocking bar and at least on second light-blocking bar. A first gap is formed between any two adjacent first light-blocking bars. The second light-blocking bar is arranged within the first gap. The first gap includes a first crack being formed between adjacent first light-blocking bar and second light-blocking bar, wherein a length of the second light-blocking bar is “a”, a width of the first crack is “b”, and a ratio of the length of the second light-blocking bar (“a”) to the width of the first crack (“b”) satisfy the relationship: 0.9<a/b<1.1. In this way, the design scope is limited. Thus, a reasonable GTM design may be obtain and the experimental cost may be reduced.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: December 5, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Zhuming Deng, Feng Zhao, Chung-Yi Chiu
  • Patent number: 9829785
    Abstract: An extreme ultraviolet lithography (EUVL) system for patterning a semiconductor wafer includes an extreme ultraviolet (EUV) mask. The EUV mask includes first and second states, and further includes a polygon region and an open-spacing region. The polygon region includes a plurality of main polygons separated by a plurality of first fields. The open-spacing region is located outside the polygon region, and includes a plurality of sub-resolution polygon and second fields, and does not include any main polygons. The system also includes a nearly on-axis illumination (ONI) to expose the EUV mask and optics to direct diffracted lights reflected from the EUV mask towards the semiconductor wafer.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9817309
    Abstract: Provided are photomasks, methods of fabricating the photomasks, and methods of fabricating a semiconductor device by using the photomasks, in which a critical dimension (CD) of a pattern of a specific region of the photomask is corrected to improve the distribution of CDs of the pattern formed on a wafer. The photomasks may include a substrate and a light-blocking pattern formed on the substrate that includes an absorber layer and an anti-reflection coating (ARC) layer. The light-blocking pattern may include at least one of a first corrected area in which a top surface of the absorber layer is exposed, and a second corrected area in which a correction layer is formed on the ARC layer.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: November 14, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-hwan Lee, Byung-gook Kim, Sang-hyeon Lee
  • Patent number: 9810978
    Abstract: A EUV mask comprises a low thermal expansion material (LTEM) substrate, a reflective multi-layer (ML) over the LTEM substrate, and a patterned absorber layer over the reflective ML. The reflective ML includes a defect. The EUV mask further comprises a mark associated with the defect. The mark is one of: a deposit over the patterned absorber layer at a distance offset from the defect, and a cavity into the patterned absorber layer in an area over the defect.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsun-Chuan Shih, Yuan-Chih Chu
  • Patent number: 9811619
    Abstract: A specialized low drop-out voltage regulator (LDO) computer system stores a generalized base model of an LDO. The base model includes values representing a circuit topology and a set of analog behavior blocks associated with the generalized LDO. Values of a set of operational parameters associated with a specific model of LDO are input to the specialized LDO computer system from a data sheet associated with the specific model of LDO. The specialized LDO computer system transforms the set of operational parameters into a computer model of the specific LDO. The LDO-specific computer model is output as a netlist or as a set of instantiation control values to control external hardware such as an integrated circuit die tooling system or a computer graphical display system.
    Type: Grant
    Filed: September 13, 2014
    Date of Patent: November 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robert Nichols Atwell, Britt Eric Brooks