Radiation Mask Patents (Class 430/5)
  • Patent number: 11754918
    Abstract: The invention relates to a pellicle assembly comprising a pellicle frame defining a surface onto which a pellicle is attached. The pellicle assembly comprises one or more three-dimensional expansion structures that allow the pellicle to expand under stress. The invention also relates to a pellicle assembly for a patterning device comprising one or more actuators for moving the pellicle assembly towards and way from the patterning device.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: September 12, 2023
    Assignee: ASML NETHERLANDS B.V.
    Inventors: David Ferdinand Vles, Chaitanya Krishna Ande, Antonius Franciscus Johannes De Groot, Adrianus Johannes Maria Giesbers, Johannes Joseph Janssen, Paul Janssen, Johan Hendrik Klootwijk, Peter Simon Antonius Knapen, Evgenia Kurganova, Marcel Peter Meijer, Wouter Rogier Meijerink, Maxim Aleksandrovich Nasalevich, Arnoud Willem Notenboom, Raymond Olsman, Hrishikesh Patel, Mária Péter, Gerrit Van Den Bosch, Wilhelmus Theodorus Anthonius Johannes Van Den Einden, Willem Joan Van Der Zande, Pieter-Jan Van Zwol, Johannes Petrus Martinus Bernardus Vermeulen, Willem-Pieter Voorthuijzen, Hendrikus Jan Wondergem, Aleksandar Nikolov Zdravkov
  • Patent number: 11754917
    Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a multilayer stack of absorber layers on the capping layer, the multilayer stack of absorber layers including a plurality of absorber layer pairs.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: September 12, 2023
    Assignee: Applied Materials, Inc.
    Inventor: Vibhu Jindal
  • Patent number: 11749615
    Abstract: A display device includes: a substrate including a first component area in which a first transmission portion is arranged, a second component area that surrounds the first component area and in which a second transmission portion is arranged, and a main display area surrounding at least a portion of the second component area; an insulating layer having a first transmission hole corresponding to the first transmission portion and a second transmission hole corresponding to the second transmission portion, the first transmission hole and the second transmission hole exposing an upper surface of the substrate; a plurality of display elements arranged on the insulating layer and corresponding to the first component area, the second component area, and the main display area; and an alignment pattern arranged on the substrate and overlapping the second transmission hole and configured to align a component with the second component area.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: September 5, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seungchan Lee, Sungjin Hong, Sanghee Jang, Sunhee Lee
  • Patent number: 11747562
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to spiral waveguide absorbers and methods of manufacture. The structure includes: a photonics component; and a waveguide absorber with a grating pattern coupled to a node of the photonics component.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: September 5, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventor: Yusheng Bian
  • Patent number: 11740560
    Abstract: A method for determining an inspection strategy for at least one substrate, the method including: quantifying, using a prediction model, a compliance metric value for a compliance metric relating to a prediction of compliance with a quality requirement based on one or both of pre-processing data associated with the substrate and any available post-processing data associated with the at least one substrate; and deciding on an inspection strategy for the at least one substrate, based on the compliance metric value, an expected cost associated with the inspection strategy and at least one objective value describing an expected value of the inspection strategy in terms of at least one objective relating to the prediction model.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: August 29, 2023
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Eleftherios Koulierakis, Carlo Lancia, Juan Manuel Gonzalez Huesca, Alexander Ypma, Dimitra Gkorou, Reza Sahraeian
  • Patent number: 11740547
    Abstract: A method for manufacturing a reticle is provided. The method includes forming a first reflective multilayer over a mask substrate. The method also includes forming a capping layer over the first reflective ML. The method further includes depositing a first absorption layer over the capping layer. In addition, the method includes depositing an etch stop layer over the first absorption layer. The method also includes forming a second reflective multilayer (ML) over the etch stop layer. The method further includes forming a second absorption layer over the second reflective ML. In addition, the method includes forming an opening through the second absorption layer and the second reflective ML until the etch stop layer is exposed. The method also includes etching the etch stop layer and the first absorption layer through the opening until the capping layer is exposed.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chang Hsueh, Huan-Ling Lee, Chia-Jen Chen, Hsin-Chang Lee
  • Patent number: 11740553
    Abstract: A method of manufacturing a photomask set includes: preparing a mask layout, the mask layout including a plurality of first layout patterns apart from one another in a first region, wherein distances between center points of three first layout patterns adjacent to one another from among the plurality of first layout patterns respectively have different values; grouping pairs of first layout patterns, in which a distance between two first layout patterns adjacent to each other does not have a smallest value, and splitting the mask layout pattern into at least two mask layouts; and forming a photomask set including at least two photomasks each including a mask pattern corresponding to the first layout pattern included in each of the mask layout patterns split into at least two mask layouts.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: August 29, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hungbae Ahn, Sangoh Park, Sunggon Jung
  • Patent number: 11740548
    Abstract: A filtration formed nanostructure pellicle film is disclosed. The filtration formed nanostructure pellicle film includes a plurality of carbon nanofibers that are intersected randomly to form an interconnected network structure in a planar orientation. The interconnected structure allows for a high minimum EUV transmission rate of at least 92%, with a thickness ranging from a lower limit of 3 nm to an upper limit of 100 nm, to allow for effective EUV lithography processing.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: August 29, 2023
    Assignee: LINTEC OF AMERICA, INC.
    Inventors: Marcio D. Lima, Takahiro Ueda
  • Patent number: 11740552
    Abstract: A manufacturing method includes the steps of: (a) preparing a lower layer member having a first base layer, a first protective thin film, and a first CNT thin film; (b) preparing a first upper layer member having a second base layer, a second protective thin film, and a second CNT thin film or a second upper layer member having a second base layer and a second protective thin film; (c) arranging the lower layer member above the first CNT thin film; (d) forming a group member by arranging the second CNT thin film of the first upper layer member or the second protective film of the second upper layer member to be stacked on the first CNT thin film; and € removing the second base layer from the group member.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: August 29, 2023
    Assignee: ESOL Inc.
    Inventor: Dong Gun Lee
  • Patent number: 11740549
    Abstract: A method of forming an extreme ultraviolet (EUV) mask including forming a multilayer stack comprising alternating stacked Mo-containing layer and Si-containing layer over a mask substrate, forming a first nitride layer over the multilayer stack forming a capping layer over the multilayer stack, forming an absorber layer over the capping layer, and etching the absorber layer to form a pattern in the absorber layer.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yun-Yue Lin
  • Patent number: 11733601
    Abstract: An EUV photomask having a main area and a scribe lane area and reflecting EUV light includes a reflective multilayer film and an absorption pattern, wherein the scribe lane area includes first and second lanes, wherein the first lane includes first and second sub-lanes extending in the same direction as an extending direction of the first lane, wherein the first sub-lane includes a first dummy pattern that is a portion of the absorption pattern, and the second sub-lane includes a second dummy pattern that is a portion of the absorption pattern, and when EUV light that is not absorbed by the first and second dummy patterns and is reflected by the reflective multilayer film is irradiated at least twice by overlapping a negative tone photoresist, an amount of light exceeds a threshold dose of light in the negative tone photoresist corresponding to the first lane.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: August 22, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soonmok Ha, Jaehee Kim, Sangho Yun, Chan Hwang
  • Patent number: 11726400
    Abstract: The present disclosure discloses a lithography process method for defining sidewall morphology of a lithography pattern, comprising: Step 1: designing a mask, wherein a mask pattern is formed on the mask, the mask pattern being used to define a lithography pattern; the lithography pattern has a sidewall, and a mask side face pattern structure that defines sidewall morphology of the lithography pattern is provided on the mask pattern, the mask side face pattern structure having a structure that enables an exposure light intensity to gradually change; Step 2: coating a to-be-exposed substrate with a photoresist; Step 3: exposing the photoresist by using the mask, and then performing development to form the lithography pattern; and Step 4: performing post-baking. The present disclosure can define the sidewall morphology of a lithography pattern, facilitating formation of a lithography pattern sidewall with an inclined side face.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: August 15, 2023
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Hui Wang
  • Patent number: 11727552
    Abstract: A method of verifying optical proximity effect correction includes generating a design pattern layout including a target pattern, generating a correction pattern layout from the design pattern layout by performing optical proximity effect correction, generating a contour image including an image pattern using the correction pattern layout, detecting a defect pattern from the image pattern of the contour image, and correcting the correction pattern layout using data of the defect pattern. Detecting the defect pattern includes acquiring position data of a center of gravity of the target pattern, acquiring position data of a center of gravity of the image pattern, and determining whether the image pattern is a defect pattern by comparing a defect pattern detection reference with a distance between the center of gravity of the target pattern and the center of gravity of the image pattern.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: August 15, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kisung Kim
  • Patent number: 11726401
    Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Hao Lee, You-Cheng Jhang, Han-Zong Pan, Jui-Chun Weng, Chiu-Hua Chung, Sheng-Yuan Lin, Hsin-Yu Chen
  • Patent number: 11726413
    Abstract: Methods of fabricating and using an overlay mark are provided. In some embodiments, the overlay mark includes an upper layer and a lower layer disposed below the upper layer. The lower layer includes a first plurality of compound gratings extending in a first direction and disposed in a first region of the overlay mark, each of the first plurality of compound gratings including one first element and at least two second elements disposed on one side of the first element, and a second plurality of compound gratings extending the first direction and disposed in a second region of the overlay mark, each of the second plurality of compound gratings including one third element and at least two fourth elements on one side of the third element. The first plurality of compound gratings is a mirror image of the second plurality of compound gratings.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Chih Hsieh, Kai-Hsiung Chen, Po-Chung Cheng
  • Patent number: 11726399
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes one or more alternating pairs of a first Cr based layer and a second Cr based layer different from the first Cr based layer.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Cheng Hsu, Ching-Huang Chen, Hung-Yi Tsai, Ming-Wei Chen, Ta-Cheng Lien, Hsin-Chang Lee
  • Patent number: 11727183
    Abstract: A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first layer including conductive lines (C_1st lines) which include interspersed alpha C_1st lines and beta C_1st lines designated correspondingly for first and second reference voltages; and forming a second layer over the first layer, the second layer including segments (C_2nd segments) which include interspersed alpha C_2nd segments and beta C_2nd segments designated correspondingly for the first and second reference voltages; and, relative to the first direction, each beta C_2nd segment being substantially asymmetrically between corresponding adjacent ones of the alpha C_2nd segments.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang
  • Patent number: 11720015
    Abstract: Aspects described herein relate to mask synthesis using design guided offsets. A target shape on an image surface to be fabricated using a mask based on a design of an integrated circuit is obtained. Rays are generated emanating from respective anchor points. The anchor points are on a boundary of the target shape or a boundary of a mask shape of the mask. For each ray of the rays, a distance is defined between a first intersection of the respective ray and the boundary of the target shape and a second intersection of the respective ray and the boundary of the mask shape. An analysis is performed by one or more processors, where the analysis is configured to modify the distances based on an error between the target shape and a resulting shape simulated to be on the image surface resulting from the mask shape.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: August 8, 2023
    Assignee: Synopsys, Inc.
    Inventors: Thomas Cecil, Kevin Hooker
  • Patent number: 11720025
    Abstract: A method of forming an extreme ultraviolet (EUV) mask includes forming a multilayer Mo/Si stack comprising alternating stacked Mo and Si layers over a mask substrate; forming a ruthenium capping layer over the multilayer Mo/Si stack; doping the ruthenium capping layer with a halogen element, a pentavalent element, a hexavalent element or combinations thereof; forming an absorber layer over the ruthenium capping layer; and etching the absorber layer to form a pattern in the absorber layer.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tsung Shih, Yu-Hsun Wu, Bo-Tsun Liu, Tsung-Chuan Lee
  • Patent number: 11714349
    Abstract: A method performed by a computing system includes receiving a layout pattern, receiving a target pattern associated with the layout pattern, receiving a set of constraints related to the target pattern, simulating a first contour associated with the layout pattern, determining a first difference between the first contour and the target pattern, simulating a second contour associated with a modified layout pattern, and determining a second difference between the second contour and a modified target pattern. The modified target pattern is different than the target pattern and within the constraints. The method further includes fabricating a mask having the final layout pattern.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Daniel Beylkin, Sagar Vinodbhai Trivedi
  • Patent number: 11714355
    Abstract: Method of forming pattern in photoresist layer includes forming photoresist layer over substrate, selectively exposing photoresist layer to actinic radiation forming latent pattern. Latent pattern is developed by applying developer to form pattern. Photoresist layer includes photoresist composition including polymer: A1, A2, L are direct bond, C4-C30 aromatic, C4-C30 alkyl, C4-C30 cycloalkyl, C4-C30 hydroxylalkyl, C4-C30 alkoxy, C4-C30 alkoxyl alkyl, C4-C30 acetyl, C4-C30 acetylalkyl, C4-C30 alkyl carboxyl, C4-C30 cycloalkyl carboxyl, C4-C30 hydrocarbon ring, C4-C30 heterocyclic, —COO—, A1 and A2 are not both direct bonds, and are unsubstituted or substituted with a halogen, carbonyl, or hydroxyl; A3 is C6-C14 aromatic, wherein A3 is unsubstituted or substituted with halogen, carbonyl, or hydroxyl; R1 is acid labile group; Ra, Rb are H or C1-C3 alkyl; Rf is direct bond or C1-C5 fluorocarbon; PAG is photoacid generator; 0?x/(x+y+z)?1, 0?y/(x+y+z)?1, and 0?z/(x+y+z)?1.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Po Yang, Wei-Han Lai, Ching-Yu Chang
  • Patent number: 11714350
    Abstract: A method includes placing a photomask having a contamination on a surface thereof in a plasma processing chamber. The contaminated photomask is plasma processed in the plasma processing chamber to remove the contamination from the surface. The plasma includes oxygen plasma or hydrogen plasma.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Fu Yang, Pei-Cheng Hsu, Ta-Cheng Lien, Hsin-Chang Lee
  • Patent number: 11703763
    Abstract: A reticle, a reticle container and a method of lithography process are provided. The reticle container includes: a cover configured to protect a reticle, a baseplate, and a discharging device on the baseplate. The baseplate has: a top surface configured to engage to the cover and a bottom surface opposite to the top surface. The discharging device is configured to neutralize static charges accumulated on the reticle.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Lun Chang, Chueh-Chi Kuo, Tsung-Yen Lee, Tzung-Chi Fu, Li-Jui Chen, Po-Chung Cheng, Che-Chang Hsu
  • Patent number: 11703752
    Abstract: A method of testing a photomask assembly includes placing the photomask assembly into a chamber, wherein the photomask assembly includes a pellicle attached to a first side of a photomask. The method further includes exposing the photomask assembly to a radiation source having a wavelength ranging from about 160 nm to 180 nm in the chamber to accelerate haze development, wherein the exposing of the photomask assembly includes illuminating an entirety of an area of the photomask covered by the pellicle throughout an entire illumination time and illuminating a frame adhesive attaching the pellicle to the photomask. The method further includes detecting haze of the photomask following exposing the photomask assembly to the radiation source. The method further includes predicting performance of the photomask assembly during a manufacturing process based on the detected haze of the photomask following exposing the photomask assembly to the radiation source.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wu-Hung Ko, Kun-Lung Hsieh, Chih-Wei Wen
  • Patent number: 11698580
    Abstract: A reflective mask blank for EUV lithography includes a substrate, a reflective layer for reflecting EUV light, and an absorption layer for absorbing EUV light. The reflective layer and the absorption layer are formed on or above the substrate in this order. The absorption layer contains tantalum (Ta) and niobium (Nb), and the absorption layer has a composition ratio Ta:Nb of Ta (at %) to Nb (at %) of from 4:1 to 1:4. Among diffraction peaks derived from the absorption layer observed at 2?: from 20° to 50° by out-of-plane XRD method, a peak having the highest intensity has a half width FWHM of 1.0° or more.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: July 11, 2023
    Assignee: AGC INC.
    Inventors: Hirotomo Kawahara, Hiroyoshi Tanabe, Toshiyuki Uno, Hiroshi Hanekawa, Daijiro Akagi
  • Patent number: 11693307
    Abstract: A stocker for holding a plurality of reticle pods is provided. Each of the reticle pods is configured to accommodate a reticle assembly. The reticle assembly includes a reticle and a pellicle covering the reticle. The stocker includes a main frame and an electrostatic generator. The main frame has an inner space and at least one pod support disposed in the inner space. The pod support divides the inner space into a plurality of chambers configured to respectively accommodate the plurality of reticle pods. The electrostatic generator is coupled to the reticle assembly and configured to generate static electricity to the reticle assembly. The static electricity alternates between positive electricity and negative electricity.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 4, 2023
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Jiyong Yoo, Byung-In Kwon, Dae-Youp Lee
  • Patent number: 11693306
    Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: July 4, 2023
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
  • Patent number: 11687006
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Cheng Chen, Chia-Jen Chen, Hsin-Chang Lee, Shih-Ming Chang, Tran-Hui Shen, Yen-Cheng Ho, Chen-Shao Hsu
  • Patent number: 11686997
    Abstract: A pellicle for a lithographic apparatus, the pellicle including nitridated metal silicide or nitridated silicon as well as a method of manufacturing the same. Also disclosed is the use of a nitridated metal silicide or nitridated silicon pellicle in a lithographic apparatus. Also disclosed is a pellicle for a lithographic apparatus including at least one compensating layer selected and configured to counteract changes in transmissivity of the pellicle upon exposure to EUV radiation as well as a method of controlling the transmissivity of a pellicle and a method of designing a pellicle.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: June 27, 2023
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Pieter-Jan Van Zwol, Adrianus Johannes Maria Giesbers, Johan Hendrik Klootwijk, Evgenia Kurganova, Maxim Aleksandrovich Nasalevich, Arnoud Willem Notenboom, Mária Péter, Leonid Aizikovitsj Sjmaenok, Ties Wouter Van Der Woord, David Ferdinand Vles
  • Patent number: 11681214
    Abstract: A substrate with a multilayer reflective film, a reflective mask blank, a reflective mask and a method of manufacturing a semiconductor device that can prevent contamination of the surface of the multilayer reflective film even in the case of having formed reference marks on the multilayer reflective film. A substrate with a multilayer reflective film contains a substrate and a multilayer reflective film that reflects EUV light formed on the substrate. Reference marks are formed to a concave shape on the surface of the substrate with the multilayer reflective film. The reference marks have grooves or protrusions roughly in the center. The shape of the grooves or protrusions when viewed from overhead is similar or roughly similar to the shape of the reference marks.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: June 20, 2023
    Assignee: HOYA Corporation
    Inventors: Kazuhiro Hamamoto, Tsutomu Shoki
  • Patent number: 11675263
    Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; and an absorber layer comprising tantalum and iridium or ruthenium and antimony.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: June 13, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Shuwei Liu, Shiyu Liu, Vibhu Jindal
  • Patent number: 11676813
    Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include delivering a dopant-containing precursor with the silicon-containing precursor and the boron-containing precursor. The dopant-containing precursor may include one or more of carbon, nitrogen, oxygen, or sulfur. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-and-boron material on a substrate disposed within the processing region of the semiconductor processing chamber. The silicon-and-boron material may include greater than or about 1 at. % of a dopant from the dopant-containing precursor.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: June 13, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Aykut Aydin, Rui Cheng, Yi Yang, Krishna Nittala, Karthik Janakiraman, Bo Qi, Abhijit Basu Mallick
  • Patent number: 11676814
    Abstract: A material for forming an organic film using a polymer including an imide group for forming an organic underlayer film that cures under film-forming conditions in the air and in an inert gas, generates no by-product in heat resistance and embedding and flattening characteristics of a pattern formed on a substrate, also adhesiveness to a substrate for manufacturing a semiconductor apparatus, a method for forming an organic film, and a patterning process. The material includes (A) a polymer having a repeating unit represented by the following general formula (1A) whose terminal group is a group represented by either of the following general formulae (1B) or (1C), and (B) an organic solvent: wherein, W1 represents a tetravalent organic group, and W2 represents a divalent organic group: wherein, R1 represents any of the groups represented by the following formula (1D), and two or more of R1s may be used in combination.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: June 13, 2023
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Daisuke Kori, Takashi Sawamura, Keisuke Niida, Seiichiro Tachibana, Takeru Watanabe, Tsutomu Ogihara
  • Patent number: 11662661
    Abstract: A reticle structure includes a reticle having patterned features and a first border section enclosing the patterned features. The reticle structure includes a membrane having a middle section a second border section enclosing the middle section. The reticle structure includes a frame disposed between the membrane and the reticle to mount the membrane over the patterned features of the reticle. The frame creates an enclosure between the reticle and the membrane and encircles the patterned features of the reticle. The frame includes a plurality of holes and the plurality of holes produces a threshold percentage of opening in the frame to maintain an equalized pressure difference between the enclosure and outside the enclosure below a threshold pressure.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yun-Yue Lin
  • Patent number: 11656544
    Abstract: A robust, high-transmission pellicle for extreme ultraviolet lithography systems is disclosed. In one example, the present disclosure provides a pellicle that includes a membrane and a frame supporting the membrane. The membrane may be formed from at least one of a transparent carbon-based film and a transparent silicon based film. The at least one of the transparent carbon-based film and the transparent silicon based film may further be coated with a protective shell. The frame may include at least one aperture to allow for a flow of air through a portion of the pellicle.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yun-Yue Lin
  • Patent number: 11658114
    Abstract: A fusible structure includes a metal line with different portions having different thicknesses. Thinner portions of the metal line are designed to be destructively altered at lower voltages while thicker portions of the metal line are designed to be destructively altered at lower voltages. Furthermore, one or more dummy structures are disposed proximal to the thinner portions of the metal line. In some embodiments, dummy structures are placed with sufficient proximity so as to protect against metal sputtering when metal line is destructively altered.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Ting Wu, Meng-Sheng Chang, Shao-Yu Chou, Chung-I Huang
  • Patent number: 11650493
    Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Cheng Hsu, Chun-Fu Yang, Ta-Cheng Lien, Hsin-Chang Lee
  • Patent number: 11650494
    Abstract: The substrate with a multilayer reflective film includes a substrate and the multilayer reflective film configured to reflect exposure light, the multilayer reflective film comprising a stack of alternating layers on a substrate, the alternating layers including a low refractive index layer and a high refractive index layer, in which the multilayer reflective film contains molybdenum (Mo) and at least one additive element selected from nitrogen (N), boron (B), carbon (C), zirconium (Zr), oxygen (O), hydrogen (H) and deuterium (D), and the crystallite size of the multilayer reflective film calculated from a diffraction peak of Mo (110) by X-ray diffraction is 2.5 nm or less.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: May 16, 2023
    Assignee: HOYA CORPORATION
    Inventors: Masanori Nakagawa, Hirofumi Kozakai
  • Patent number: 11650512
    Abstract: Some implementations described herein provide a reticle cleaning device and a method of use. The reticle cleaning device includes a support member configured for extension toward a reticle within an extreme ultraviolet lithography tool. The reticle cleaning device also includes a contact surface disposed at an end of the support member and configured to bond to particles contacted by the contact surface. The reticle cleaning device further includes a stress sensor configured to measure an amount of stress applied to the support member at the contact surface. During a cleaning operation in which the contact surface is moving toward the reticle, the stress sensor may provide an indication that the amount of stress applied to the support member satisfies a threshold. Based on satisfying the threshold, movement of the contact surface and/or the support member toward the reticle ceases to avoid damaging the reticle.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Chang Hsu, Sheng-Kang Yu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Patent number: 11646211
    Abstract: A measuring device includes a measuring stage on which a subject is placed, an X-ray irradiation unit, an X-ray detection unit that detects scattered X-rays generated from the subject and an analysis unit that analyzes the diffraction image obtained by photo-electrically converting scattered X-rays and presumes (estimates) the three-dimensional shape of the subject. In the subject, holes are formed in the ON stack film from the opening of the etching mask film formed on the ON stack film. The analysis unit presumes the three-dimensional shape of the subject based a plurality of the diffraction images acquired while changing a rotation angle of the measuring stage and the measurement data of the subject by at least one of measuring methods of a multi-wavelength light measurement and a laser ultrasonic wave measurement.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: May 9, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Hiroyuki Tanizaki
  • Patent number: 11644741
    Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer, the absorber layer made from carbon and antimony.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: May 9, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Shuwei Liu, Vibhu Jindal
  • Patent number: 11644742
    Abstract: Provided is a phase shift mask blank including a substrate, and a phase shift film thereon, the phase shift film composed of a material containing silicon and nitrogen and free of a transition metal, exposure light being KrF excimer laser, the phase shift film consisting of a single layer or a plurality of layers, the single layer or each of the plurality of layers having a refractive index n of at least 2.5 and an extinction coefficient k of 0.4 to 1, with respect to the exposure light, and the phase shift film having a phase shift of 170 to 190° and a transmittance of 4 to 8%, with respect to the exposure light, and a thickness of up to 85 nm.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: May 9, 2023
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Takuro Kosaka
  • Patent number: 11646265
    Abstract: A semiconductor device is disclosed, which relates to a three-dimensional (3D) semiconductor memory device. The semiconductor device includes a first connection pattern, a bit line disposed over the first connection pattern in a vertical direction, and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern so that the bit-line contact pad, and formed as an island when viewed along the vertical direction.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 9, 2023
    Assignee: SK hynix Inc.
    Inventors: Dong Hyuk Kim, Sung Lae Oh, Tae Sung Park, Soo Nam Jung
  • Patent number: 11644744
    Abstract: The present application discloses a display panel, a manufacturing method of a display panel and a mask used thereof. The manufacturing method of the display panel comprises the following steps: doping a photo-initiator in photoresist for manufacturing photo spacers; coating the photoresist on the substrates to form photo spacers, and arranging a shade on the same layer; and respectively irradiating corresponding photo spacers by at least two types of light rays of different wavelengths, to control the photo-initiator so as to enable different photo spacers to have different shrinkages.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: May 9, 2023
    Assignees: HKC CORPORATION LIMITED, Chongqing HKC Optoelectronics Technology Co., Ltd.
    Inventor: Chung-Kuang Chien
  • Patent number: 11640109
    Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer, the absorber layer made from antimony and nitrogen.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: May 2, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Shuwei Liu, Shiyu Liu, Vibhu Jindal, Azeddine Zerrade, Ramya Ramalingam
  • Patent number: 11635681
    Abstract: A method comprising the steps of receiving a mask assembly comprising a mask and a removable EUV transparent pellicle held by a pellicle frame, removing the pellicle frame and EUV transparent pellicle from the mask, using an inspection tool to inspect the mask pattern on the mask, and subsequently attaching to the mask an EUV transparent pellicle held by a pellicle frame. The method may also comprise the following steps: after removing the pellicle frame and EUV transparent pellicle from the mask, attaching to the mask an alternative pellicle frame holding an alternative pellicle formed from a material which is substantially transparent to an inspection beam of the inspection tool; and after using an inspection tool to inspect the mask pattern on the mask, removing the alternative pellicle held by the alternative pellicle frame from the mask in order to attach to the mask the EUV transparent pellicle held by the pellicle frame.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: April 25, 2023
    Assignee: ASML Netherlands B.V.
    Inventors: Derk Servatius Gertruda Brouns, Dennis De Graaf, Robertus Cornelis Martinus De Kruif, Paul Janssen, Matthias Kruizinga, Arnoud Willem Notenboom, Daniel Andrew Smith, Beatrijs Louise Marie-Joseph Katrien Verbrugge, James Norman Wiley
  • Patent number: 11636248
    Abstract: An IC layout diagram generation system includes a processor and a non-transitory, computer readable storage medium including computer program code for one or more programs. The non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the system to align a border segment of a cell at a predetermined location relative to a plurality of second metal layer tracks, position the cell relative to a first metal layer cut region alignment pattern based on the plurality of second metal layer tracks, overlap the cell with a first metal layer cut region based on the first metal layer cut region alignment pattern, and generate an IC layout diagram of an IC device based on the cell and the first metal layer cut region.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting Yu Chen, Li-Chun Tien, Fong-Yuan Chang
  • Patent number: 11636249
    Abstract: Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Chung-Te Lin, Fong-Yuan Chang, Ho Che Yu, Li-Chun Tien
  • Patent number: 11630386
    Abstract: The prevent disclosure provides a reflective mask. In some embodiments, the reflective mask includes a substrate, a sp2-hybrid carbon layer, a reflective multilayer, and an absorption pattern. The sp2-hybrid carbon layer is over the substrate. The reflective multilayer is over the sp2-hybrid carbon layer. The absorption pattern is over the reflective multilayer.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsiao-Chen Wu, Pei-Cheng Hsu
  • Patent number: 11630385
    Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer, the absorber layer made from tantalum and ruthenium.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: April 18, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Shuwei Liu, Wen Xiao, Vibhu Jindal, Azeddine Zerrade