Radiation Mask Patents (Class 430/5)
  • Patent number: 10996558
    Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
  • Patent number: 10996554
    Abstract: A substrate with an electrically conductive film for fabricating a reflective mask is obtained that is capable of preventing positional shift of the reflective mask during pattern transfer. Provided is a substrate with an electrically conductive film used in lithography, the substrate with an electrically conductive film having an electrically conductive film formed on one of the main surfaces of a mask blank substrate, and a coefficient of static friction of the surface of the electrically conductive film is not less than 0.25.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: May 4, 2021
    Assignee: HOYA CORPORATION
    Inventors: Takumi Kobayashi, Kazuhiro Hamamoto, Tatsuo Asakawa, Tsutomu Shoki
  • Patent number: 10990744
    Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
  • Patent number: 10990000
    Abstract: The present disclosure teaches a photolithography plate and a mask correction method, and relates to the field of semiconductor technologies. In forms of the mask correction method, a patterned mask is formed on a substrate, a location of a scattering bar embedded in the substrate is determined according to the mask, and an opening is formed at the determined location so as to embed the scattering bar in the opening. A scattering bar is embedded in a substrate of a photolithography plate so as to effectively avoid the impact of the scattering bar on a mask pattern, reduce a deposition loss, improve the correction effect, and shorten a correction time.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: April 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Jiancheng Zhang, Wei Wu, Chenbo Zhang
  • Patent number: 10989999
    Abstract: A halftone phase shift mask blank comprising a transparent substrate and a halftone phase shift film thereon is provided. The halftone phase shift film includes at least one layer composed of a silicon base material having a transition metal content ?3 at %, a Si+N+O content ?90 at %, a Si content of 30-70 at %, a N+O content of 30-60 at %, and an O content ?30 at %, and having a sheet resistance ?1013/?/?. The halftone phase shift film undergoes minimal pattern size variation degradation upon exposure to sub-200 nm radiation, and has chemical resistance and improved processability.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 27, 2021
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Yukio Inazuki, Takuro Kosaka, Kouhei Sasamoto, Hideo Kaneko
  • Patent number: 10990741
    Abstract: A method includes assigning a first color group to a first routing track of the layout. The method further includes assigning a second color group to a second routing track of the layout. The method includes assigning the first color group to a third routing track of the layout, wherein the second routing track is between the first routing track and the third routing track. The method further includes assigning a first color from the first color group to a first conductive element along the first routing track. The method further includes assigning a second color from the first color group to a second conductive element along the first routing track. The method further includes assigning a third color from the second color group to a third conductive element on the second routing track, wherein the third color is different from each of the first color and the second color.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Yuan-Te Hou
  • Patent number: 10988400
    Abstract: The present invention relates to a transparent sealing member. A quartz glass transparent sealing member is used in an optical component having at least one optical element, and a mounting board on which the optical element is mounted, and constitutes, with the mounting board, a package that houses the optical element. The concentration of aluminum in a surface portion is higher than the concentration of aluminum in an inner portion.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: April 27, 2021
    Assignee: NGK Insulators, Ltd.
    Inventors: Yoshio Kikuchi, Hiroyuki Shibata
  • Patent number: 10983427
    Abstract: A mask blank substrate and a method for selecting a mask blank substrate wherein a square calculation region is set on the main surface of the substrate. Specific points are set at the corner portions of the calculation region. The heights of the specific points from a reference plane are acquired, an imaginary plane passing through three of the specific points is set, an intersection between the imaginary plane and a perpendicular line that passes through the remaining of the specific points and that is perpendicular to the reference plane is set, and the distance between the remaining of the specific points and the intersection is calculated. A substrate in which the distance satisfies a predetermined reference value is selected as a mask blank substrate.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: April 20, 2021
    Assignee: HOYA CORPORATION
    Inventor: Masaru Tanabe
  • Patent number: 10983429
    Abstract: A retargeting method for optical proximity correction (OPC) is provided. The method includes: assigning evaluation points for defining profile of a layout pattern; identifying critical regions of the layout pattern that could result in limitation on the process window of the OPC; categorizing the critical regions based on geometries of the critical regions; obtaining movable ranges and address information of the evaluation points; and shifting the evaluation points according to the parameters obtained during the previous steps.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: April 20, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Chun-Liang Lin
  • Patent number: 10969679
    Abstract: The invention relates to a system (2) for producing an optical mask (35) for surface microtexturing, said system (2) comprising: a substrate (10) having a surface (11) that is to be textured; a layer of material (20) which covers the surface (11) of the substrate (10) and has an outer surface (21) that is exposed to the outside environment; and a generating and depositing device for generating and depositing droplets (30) on the outer surface (21) of the layer of material (20), in a specific arrangement (31) under condensation, forming the optical mask (35) on the outer surface (21) of the layer of material (20). The invention also relates to a treatment plant comprising a system (2) of said type. The invention further relates to a method for producing a mask as well as to a surface microtexturing method.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 6, 2021
    Assignees: H.E.F., Universite Jean Monnet Saint Etienne, Centre National De La Recherche Scientifique (CNRS)
    Inventors: Maxime Bichotte, Yves Jourlin, Laurent Dubost
  • Patent number: 10969687
    Abstract: A method for forming patterns is provided in the present invention. The process includes the steps of using a first mask to perform a first exposure process to a photoresist, using a second mask to perform a second exposure process to the photoresist, wherein the corners of the second opening patterns in the second mask and the corners of the first opening patterns in the first mask overlap each other, and performing a development process to remove the unexposed portions of the photoresist in the two exposure processes to form staggered hole patterns therein.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: April 6, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Harn-Jiunn Wang, Kai-Ming Liu, Chin-Lung Lin, Yi-Hsiu Lee
  • Patent number: 10971409
    Abstract: Semiconductor devices having measurement features and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a plurality of stacked semiconductor dies each having measurement features formed along an outer periphery of a surface thereof. One or more image capture devices can image the semiconductor device and a controller can detect the measurement features in imaging data received from the image capture devices. The controller can further determine the distance between two or more of the measurement features to estimate a bond line thickness between semiconductor dies in the stack.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, Lisa R. Copenspire-Ross, Michael D. Kenney
  • Patent number: 10969701
    Abstract: Tooling for a mask assembly suitable for use in a lithographic process, the mask assembly comprising a patterning device; and a pellicle frame configured to support a pellicle and mounted on the patterning device with a mount; wherein the mount provides a releasably engageable attachment between the patterning device and the pellicle frame.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 6, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Frits Van Der Meulen, Maarten Mathijs Marinus Jansen, Jorge Manuel Azeredo Lima, Derk Servatius Gertruda Brouns, Marc Bruijn, Jeroen Dekkers, Paul Janssen, Ronald Harm Gunther Kramer, Matthias Kruizinga, Robert Gabriël Maria Lansbergen, Martinus Hendrikus Antonius Leenders, Erik Roelof Loopstra, Gerrit Van Den Bosch, Jérôme François Sylvain Virgile Van Loo, Beatrijs Louise Marie-Joseph Katrien Verbrugge, Angelo Cesar Peter De Klerk, Jacobus Maria Dings, Maurice Leonardus Johannes Janssen, Roland Jacobus Johannes Kerstens, Martinus Jozef Maria Kester, Michel Loos, Geert Middel, Silvester Matheus Reijnders, Frank Johannes Christiaan Theuerzeit, Anne Johannes Wilhelmus Van Lievenoogen
  • Patent number: 10969678
    Abstract: The invention relates to a system (2) for producing an optical mask (35) for surface treatment, in particular surface microtexturing, said system (2) comprising: a layer of material (20) which has an outer surface (21) that is exposed to the outside environment; and a generating and depositing device for generating and depositing droplets (30) on the outer surface (21) of the layer of material (20) in which a specific arrangement (31), forming the optical mask (35) on the outer surface (21) of the layer of material (20). The invention also relates to a treatment plant comprising a system (2) of said type. The invention further relates to a method for producing a mask as well as to a method for surface treatment.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 6, 2021
    Assignees: H.E.F., Universite Jean Monnet Saint Etienne, Centre National De La Recherche Scientifique (CNRS)
    Inventors: Maxime Bichotte, Yves Jourlin, Laurent Dubost
  • Patent number: 10962874
    Abstract: A method of manufacturing a semiconductor device includes performing extreme ultraviolet (EUV) lithography that uses a mask for the EUV lithography manufactured by using a design layout on which optical proximity correction (OPC) is performed, and performing the OPC includes dividing respective patterns included in the design layout into partial patterns, classifying the partial patterns into a plurality of partial pattern groups, performing a first OPC on the design layout, and performing a second OPC that is different from the first OPC on the design layout on which the first OPC is performed, wherein performing the first OPC is performed on representative patterns selected from the plurality of partial pattern groups.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Akio Misaka, No-young Chung, Ki-soo Kim
  • Patent number: 10962886
    Abstract: Provided is a process of selecting a measurement location, the process including: obtaining pattern data describing a pattern to be applied to substrates in a patterning process; obtaining a process characteristic measured during or following processing of a substrate, the process characteristic characterizing the processing of the substrate; determining a simulated result of the patterning process based on the pattern data and the process characteristic; and selecting a measurement location for the substrate based on the simulated result.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: March 30, 2021
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Hans Van Der Laan, Wim Tjibbo Tel, Marinus Jochemsen, Stefan Hunsche
  • Patent number: 10957555
    Abstract: A process method for producing a photomask with double patterns. The processing method includes obtaining a contact distribution pattern, having multiple contacts. The contacts are sorted into multiple contact blocks in array type, pair type and isolation type. The contacts are decomposed into a first patterning group and a second patterning group, which are configured to interpose to each other. The numbers of contacts of the first patterning group and the second patterning group are equal within an error range. The first patterning group and the second patterning group are check whether or not having adjacent two contacts with a distance less than a minimum distance. If it is less than a minimum distance, one of the adjacent two contacts is changed from a current one of the first patterning group and the second patterning group to another. The first/second patterning groups are output to from first/second photomasks.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: March 23, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Chien-Chin Huang, Shih-Min Tseng
  • Patent number: 10955740
    Abstract: The present invention provides; a pellicle frame which can effectively inhibit distortion of the photo mask (8) caused by mounting the pellicle (1), and which does not have a complex shape, and a pellicle which uses said pellicle frame are provided, and a manufacturing method of a blackened pellicle frame is also provided which can reduce the defect of the surface flickering under concentrated light and which facilitates inspection of the foreign matter adhesion prior to use. The present invention relates to a pellicle frame with an anodized film on a surface of an aluminum alloy frame, characterized in that: the aluminum alloy frame comprises an aluminum alloy which contains Ca: 5.0 to 10.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 23, 2021
    Assignees: NIPPON LIGHT METAL COMPANY, LTD., Mitsui Chemicals, Inc.
    Inventors: Yoshihiro Taguchi, Kazuo Kohmura, Daiki Taneichi
  • Patent number: 10957721
    Abstract: The CMOS LTPS TFT substrate manufacturing method, by a semi-transparent mask, forms a second photoresist pattern having a second photoresist section above a second poly-Si active layer where P-type ion heavy doping is to be performed as protection. Then, N-type ions are effectively prevented from being implanted into the second poly-Si active layer's second source/drain contact region when conducting N-type ion heaving doping to the first poly-Si active layer. There is no need to compensate P-type ions during the subsequent P-type ion heavy doping to the second poly-Si active layer for forming the second source/drain contact region. The present invention therefore reduces the productivity loss in the P-type ion heaving doping process and, as N-type ion heaving doping does not affect the PMOS transistors, enhances the electrical convergence of the PMOS transistors. Damage to the film lattice structure by the ion implantation is also reduced, thereby increasing the device reliability.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 23, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Lisheng Li, Guanghui Liu
  • Patent number: 10948816
    Abstract: The present invention provides a pellicle frame which can effectively inhibit deformation of an exposure master plate (8) caused by affixing the pellicle (1), and which does not have a complex shape, and a pellicle which uses said pellicle frame are provided. The pellicle frame with an anodized film on a surface of an aluminum alloy frame is characterized in that: the aluminum alloy frame comprises an aluminum alloy which contains Ca: 5.0 to 10.0% by weight with the remainder aluminum and unavoidable impurities are contained, and has an area (volume) ratio of an Al4Ca phase, which is a dispersed phase, is greater than or equal to 25%, and a crystal structure of a part of the Al4Ca phase is monoclinic; wherein the anodized film contains Al4Ca particles.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 16, 2021
    Assignee: NIPPON LIGHT METAL COMPANY, LTD.
    Inventors: Yoshihiro Taguchi, Takayuki Yamaguchi, Jun Yu, Yasuo Ishiwata
  • Patent number: 10948817
    Abstract: A circular mold-forming substrate of 125-300 mm diameter having a surface on which a topological pattern is to be formed is provided wherein the thickness of the substrate has a variation of up to 2 ?m within a circle having a diameter of 125 mm.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: March 16, 2021
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Daijitsu Harada, Masaki Takeuchi
  • Patent number: 10947396
    Abstract: Curable antifouling compositions include fluorinated polymers that contain a perfluoropolyether group, a poly(alkyleneoxide) group, a hydrolyzable silane group and a cationic curative. The curable antifouling compositions can be applied on a surface of a substrate, and at least partially cured to provide an article with antifouling properties.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: March 16, 2021
    Assignee: 3M Innovative Properties Company
    Inventors: Zai-Ming Qiu, Alexander J. Kugel, Michael J. Svarovsky
  • Patent number: 10942442
    Abstract: A mask blank is provided in which a phase-shift film is provided on a transparent substrate, the phase-shift film having a predetermined transmittance to ArF exposure light and being configured to shift a phase of ArF exposure light transmitted therethrough, wherein the phase-shift film comprises a nitrogen-containing layer that is formed from a material containing silicon and nitrogen and does not contain a transition metal, and wherein a content of oxygen in the nitrogen-containing layer, when measured by X-ray photoemission spectroscopy, is below a detection limit.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 9, 2021
    Assignee: HOYA CORPORATION
    Inventors: Osamu Nozawa, Hiroaki Shishido, Kazuya Sakai
  • Patent number: 10942441
    Abstract: A mask blank having a phase shift film and a light shielding film laminated on a transparent substrate. The phase shift film transmits ArF exposure light at a transmittance of from 2% to 30% and generates a phase difference of from 150° to 200°, is formed from a material containing Si and not substantially containing Cr, and has a lower layer (L) and an upper layer (U) laminated from the transparent substrate side. A refractive index n for layer L is below that of the substrate while n for layer U is higher, and layer L has an extinction coefficient k higher than that of layer U. The light shielding film includes a layer in contact with the phase shift film that is formed from a material containing Cr, has a n lower than that of layer U, and has an extinction coefficient k higher than that of layer U.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: March 9, 2021
    Assignee: HOYA CORPORATION
    Inventors: Osamu Nozawa, Takenori Kajiwara, Hiroaki Shishido
  • Patent number: 10942445
    Abstract: A blankmask according to the present disclosure includes a light-shielding film provided on a transparent substrate; and a hard mask film provided on the light-shielding film and comprising molybdenum chromium (MoCr). Thus, the hard mask film has not only an enhanced etching speed but also sufficient etching resistance to fluorine (F)-based dry etching, so that an etching load against a resist film can be decreased and a hard mask film pattern and a light-shielding film pattern can be improved in a line edge roughness (LER), thereby forming a photomask for high-precision pattern printing.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 9, 2021
    Assignee: S&S TECH Co., Ltd.
    Inventors: Cheol Shin, Jong-Hwa Lee, Chul-Kyu Yang, Min-Ki Choi
  • Patent number: 10942440
    Abstract: Provided is a mask blank including a phase shift film having a transmittance of 20% or more difficult to achieve in a phase shift film of a single layer made of a silicon nitride material, and the phase shift film is achieved by using a structure having two or more sets of a stacked structure, each set including a low transmission layer and a high transmission layer disposed in order from a transparent substrate side. The mask blank includes a phase shift film on a transparent substrate. The phase shift film has a function of transmitting exposure light of an ArF excimer laser at a transmittance of 20% or more. The mask blank has two or more sets of a stacked structure, each set including a low transmission layer and a high transmission layer. The low transmission layer is formed of a silicon nitride-based material. The high transmission layer is formed of a silicon oxide-based material.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: March 9, 2021
    Assignee: HOYA CORPORATION
    Inventors: Hiroyuki Iwashita, Atsushi Matsumoto, Osamu Nozawa
  • Patent number: 10942443
    Abstract: A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsu-Ting Huang, Shih-Hsiang Lo, Ru-Gun Liu
  • Patent number: 10935882
    Abstract: The present invention is to provide a pellicle frame in a frame shape having an upper end face on which a pellicle film is to be arranged and a lower end face to face a photomask, which is characterized by being provided with a notched part from the outer side face toward inner side face of the lower end face; a pellicle including the pellicle frame as an element; and a method for peeling a pellicle from a photomask onto which the pellicle has been attached, which is characterized by inserting a peeling jig into a notched part from a side face of a pellicle frame, and moving the peeling jig in an upper end face direction of the pellicle frame in this state to peel off the pellicle from the photomask.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: March 2, 2021
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Yu Yanase
  • Patent number: 10937663
    Abstract: Disclosed are methods for removing bridge defects using an angled implant and selective photoresist etch. In one embodiment, a method includes providing a semiconductor device including plurality of photoresist lines on a stack of layers, wherein a bridge defect extends between two or more photoresist lines of the plurality of photoresist lines. The method may further include implanting a sidewall and an upper surface of the two or more photoresist lines with an ion beam disposed at an angle, the angle being a non-zero angle of inclination with respect to a perpendicular to a plane of the upper surface of the stack of layers. The method may further include etching the semiconductor device to remove the bridge defect.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: March 2, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tristan Y. Ma, Juiyuan Hsu
  • Patent number: 10928724
    Abstract: Embodiments of the present disclosure generally provide apparatus and methods for removing an attachment feature utilized to hold a pellicle from a photomask. In one embodiment, an attachment feature removal apparatus for processing a photomask includes an attachment feature puller comprising an actuator, a clamp coupled to the actuator, the clamp adapted to grip an attachment feature, and a coil assembly disposed adjacent to the attachment feature.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: February 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Banqiu Wu, Eli Dagan, Khalid Makhamreh, Bruce J. Fender
  • Patent number: 10928723
    Abstract: A pellicle for a photomask, a reticle including the same, and an exposure apparatus for lithography are provided. The pellicle may include a pellicle membrane, and the pellicle membrane may include nanocrystalline graphene. The nanocrystalline graphene may have defects. The nanocrystalline graphene may include a plurality of nanoscale crystal grains, and the nanoscale crystal grains may include a two-dimensional (2D) carbon structure having an aromatic ring structure. The defects of the nanocrystalline graphene may include at least one of an sp3 carbon atom, an oxygen atom, a nitrogen atom, or a carbon vacancy.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeonjin Shin, Hyunjae Song, Seongjun Park, Keunwook Shin, Changseok Lee, Dongwook Lee, Minsu Seol, Sangwon Kim, Seongjun Jeong
  • Patent number: 10928721
    Abstract: To provide a reflective mask blank for EUV lithography which is excellent in flatness, whereby the deterioration of the overlay accuracy at the time of pattern transfer can be relatively easily corrected, and the deterioration of the overlay accuracy due to the flatness is small.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: February 23, 2021
    Assignee: AGC, Inc.
    Inventor: Yoshiaki Ikuta
  • Patent number: 10928722
    Abstract: Methods of manufacturing a membrane assembly where, in one arrangement, a stack includes a planar substrate and at least one membrane layer. The planar substrate includes an inner region, a border region around the inner region, a bridge region around the border region and an edge region around the bridge region. The inner region and a first portion of the bridge region are removed. The membrane assembly after removal has: a membrane formed from the at least one membrane layer, a border holding the membrane, the border formed from the border region, an edge section around the border, the edge section formed from the edge region, a bridge between the border and the edge section, the bridge formed from the at least one membrane layer and a second portion of the bridge region. The method further involves separating the edge section from the border by cutting or breaking the bridge.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: February 23, 2021
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Paul Janssen, Johan Hendrik Klootwijk, Wilhelmus Theodorus Anthonius Johannes Van Den Einden, Aleksandar Nikolov Zdravkov
  • Patent number: 10928735
    Abstract: A patterning device for use with a lithographic apparatus, the device comprising an absorber portion configured to absorb incident radiation and to reflect a portion of incident radiation, the absorber portion comprising a first layer and a second layer, the first layer of the absorber portion comprising a first material that is different from a second material of the second layer of the absorber portion; a reflector portion arranged beneath the absorber portion, the reflector portion being configured to reflect incident radiation; and a phase tune portion arranged between the reflector portion and the absorber portion, the phase tune portion being configured to induce a phase shift between the radiation reflected by the reflector portion and the portion of radiation reflected by the absorber portion such that the radiation reflected by the reflector portion destructively interferes with the portion of radiation reflected by the absorber portion.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: February 23, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Marcus Adrianus Van De Kerkhof, Laurentius Cornelius De Winter, Eelco Van Setten
  • Patent number: 10921705
    Abstract: Provided is a reflective mask capable of reducing out-of-band light when transferring a prescribed pattern onto a wafer by exposure using EUV light in a process of manufacturing a semiconductor device. The mask blank substrate is provided with a base film on a substrate, the base film is formed with a material having a refractive index smaller than the substrate over a wavelength range of not less than 190 nm and not more than 280 nm, and reflectance of the base film arranged on the surface of the substrate is smaller than the reflectance of the substrate over a wavelength range of not less than 190 nm to not more than 280 nm.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: February 16, 2021
    Assignee: HOYA CORPORATION
    Inventors: Yohei Ikebe, Tsutomu Shoki
  • Patent number: 10915015
    Abstract: An extreme ultraviolet (EUV) mask blank is provided. The EUV mask blank includes a substrate having a first surface and a second surface opposed to each other, a reflective layer having first reflective layers and second reflective layers alternately stacked on the first surface of the substrate, a capping layer on the reflective layer, and a hydrogen absorber layer between the reflective layer and the capping layer, the hydrogen absorber layer configured to store hydrogen and being in contact with the capping layer.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: February 9, 2021
    Inventors: Ho Yeon Kim, Seong Chul Hong, Seong Sue Kim
  • Patent number: 10915016
    Abstract: Provided is a mask blank (100) for manufacturing a phase shift mask.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 9, 2021
    Assignee: HOYA CORPORATION
    Inventors: Osamu Nozawa, Ryo Ohkubo, Hiroaki Shishido
  • Patent number: 10915017
    Abstract: An overlay mark includes a first, a second, a third, and a fourth component. The first component is located in a first region of the first overlay mark and includes a plurality of gratings that extend in a first direction. The second component is located in a second region of the first overlay mark and includes a plurality of gratings that extend in the first direction. The third component is located in a third region of the first overlay mark and includes a plurality of gratings that extend in a second direction different from the first direction. The fourth component is located in a fourth region of the first overlay mark and includes a plurality of gratings that extend in the second direction. The first region is aligned with the second region. The third region is aligned with the fourth region.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: February 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Ching Lee, Te-Chih Huang, Yu-Piao Fang
  • Patent number: 10908495
    Abstract: A photolithography process includes providing a first test layout including test patterns, and a first light source; forming an initial mask layout according to the first test layout; forming a mask layout including mask layout patterns through an optical proximity correction or a phase-shifting masking; forming exposed patterns by exposing the mask layout using the first light source; and determining a weak region from the first test layout. A first distance between adjacent test patterns in the weak region is unequal to a second distance between corresponding exposed patterns. The photolithography process further includes performing a re-layout on the weak region to increase the first distance, thereby providing an adjusted test layout; performing a light-source optimization to obtain an adjusted light source; and determining the adjusted test layout and the adjusted light source as a second test layout and a second light source, respectively when process window requirements are satisfied.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: February 2, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Yao Jun Du, Liang Li, Juan Liu
  • Patent number: 10890842
    Abstract: A reflective mask blank includes, on/above a substrate in the following order from the substrate side, a reflective layer which reflects EUV light, and an absorber layer which absorbs EUV light. The absorber layer contains Sn as a main component and Ta in an amount of 25 at % or more.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: January 12, 2021
    Assignee: AGC INC.
    Inventor: Hiroyoshi Tanabe
  • Patent number: 10890789
    Abstract: The present disclosure relates to a mask and a manufacturing method thereof as well as a display device, the mask includes a transmittable substrate and a mask pattern formed on the transmittable substrate, wherein a transmittance of the transmittable substrate decreases gradually from the edge to the center.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: January 12, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ping Song, Hongmin Li, Zhifu Dong, Wei Xue, Liqing Liao
  • Patent number: 10884345
    Abstract: A first substrate 2002 has a calibration pattern applied to a first plurality of fields 2004 by a lithographic apparatus. Further substrates 2006, 2010 have calibration patterns applied to further pluralities of fields 2008, 2012. The different pluralities of fields have different sizes and/or shapes and/or positions. Calibration measurements are performed on the patterned substrates 2002, 2006, 2010 and used to obtain corrections for use in controlling the apparatus when applying product patterns to subsequent substrates. Measurement data representing the performance of the apparatus on fields of two or more different dimensions (fields 2004, 2008, 2012 in this example) is gathered together in a database 2013 and used to synthesize the information needed to calibrate the apparatus for a new size. Calibration data is also obtained for different scan and step directions.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: January 5, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Emil Peter Schmitt-Weaver, Jens Stäcker, Koenraad Remi André Maria Schreel, Roy Werkman
  • Patent number: 10886234
    Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate which includes a semiconductor chip region and a scribe line region surrounding the semiconductor chip region; an insulating film arranged over the semiconductor chip region and the scribe line region on the substrate, and including a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite to the third surface and connecting the first surface and the second surface; and an opening portion formed on the second surface of the insulating film and the fourth surface of the insulating film to expose the substrate, wherein the opening portion is formed in the scribe line region, and the first surface of the insulating film and the third surface of the insulating film do not include an opening portion which expose the substrate.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Ho Yoon, Yoon Sung Kim, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jung Ho Choi
  • Patent number: 10887997
    Abstract: The present disclosure relates to an apparatus for manufacturing flexible printed circuit board (FPCB) and method for manufacturing the FPCB, having no limitations of length of a circuit pattern being formed on a base film.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: January 5, 2021
    Assignee: INKTEC CO., LTD.
    Inventors: Kwang-Choon Chung, Byung Woong Moon
  • Patent number: 10886303
    Abstract: The application discloses an array substrate, comprising a base, a conductive pattern layer disposed on the base, a transparent electrode layer, and an insulating layer disposed between the conductive pattern layer and the transparent electrode layer, the conductive pattern layer comprises a plurality of first conductive patterns, the transparent electrode layer comprises a plurality of transparent electrodes, each of the transparent electrodes is electrically coupled to a corresponding one of the first conductive patterns through a corresponding via hole in the insulating layer, wherein at a position where at least one via hole is located, a stepped structure is formed between the first conductive pattern corresponding to the via hole and the base and/or the insulating layer such that a groove is formed at an upper surface of the array substrate at a position corresponding to the via hole. The application further discloses a display device.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: January 5, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunping Long, Pan Li
  • Patent number: 10877375
    Abstract: A reflection type exposure mask includes a substrate, a reflective layer provided on the substrate, and a light absorption layer provided on the surface of the reflective layer. The light absorption layer includes a first absorber and a second absorber. The first absorber extends in a first direction along the surface of the reflective layer. The second absorber extends in a second direction along the surface of the reflective layer, which intersects with the first direction. The thickness of the second absorber in a third direction which is perpendicular to the surface of the reflective layer is thinner than the thickness of the first absorber in the third direction.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yumi Nakajima
  • Patent number: 10877368
    Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a an absorber layer on the capping layer, the absorber layer made from an alloy of at least two absorber materials.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: December 29, 2020
    Assignee: Applied Materials, Inc.
    Inventor: Vibhu Jindal
  • Patent number: 10879500
    Abstract: A fabrication method of an organic electroluminescent device includes: providing a substrate configured to an anode of the device; fabricating a blue pixel emission layer on one side of the substrate with a universal mask plate; and fabricating a red pixel emission layer and a green emission layer successively on one side of the blue pixel emission layer which backs toward the substrate. The blue pixel emission layer includes an effective emission area and a non-effective emission area. The red pixel emission layer and the green pixel emission layer both are the same layer and arranged on the non-effective emission area. The present disclosure can reduce equipment expenditure in fabricating the emission layers and the complexities of technology.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: December 29, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Lei Pei, Mingming Chi
  • Patent number: 10871708
    Abstract: Alignment patterns that are selected based on device pattern spatial frequencies are defined on a reticle. The alignment patterns can include periodic arrays of lines, spaces, dots, of other pattern elements. Such patterns can be defined as sets associated with a common spatial frequency or frequency range, or some or all sets can include alignment marks having mark elements associated with different spatial frequencies.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: December 22, 2020
    Assignee: Nikon Corporation
    Inventors: Steven Douglas Slonaker, Stephen P. Renwick
  • Patent number: 10866515
    Abstract: Methods for forming a semiconductor structure including using a photoresist material are provided. The method for forming a semiconductor structure includes forming a material layer over a substrate and forming a photoresist layer over the material layer. The method for forming a semiconductor structure further includes performing an exposure process on the photoresist layer and developing the photoresist layer. In addition, the photoresist layer is made of a photoresist material comprising a photosensitive polymer, and the photosensitive polymer has a first photosensitive functional group bonding to a main chain of the photosensitive polymer and a first acid labile group bonding to the first photosensitive functional group.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hui Weng, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin, Siao-Shan Wang