Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.

Abstract: According to example embodiments, a variable resistance memory device may include memory cells, in which contact areas between word lines and a variable resistance layer are almost constant. The variable resistance memory device may include a vertical electrode on a substrate, horizontal electrode layers and insulating layers sequentially and alternately stacked on the substrate. The horizontal electrode layers and the insulating layers may be adjacent to the vertical electrode. The variable resistance layer may be between the vertical electrode the horizontal electrode layers. A thickness of one of the horizontal electrode layers adjacent to the substrate may be thickness than a thickness of an other of the horizontal electrode layers that is spaced apart from the substrate.

Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 ?cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.

Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises a resistive material that is configured to improve the switching performance and lifetime of the resistive switching memory element. The electrical properties of the current limiting layer are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the resistive switching memory element found in the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel nitride that is a current limiting material that is disposed within a resistive switching memory element in a nonvolatile resistive switching memory device.

Abstract: Some embodiments include memory constructions having a film of phase change material between first and second materials; with the entirety of film having a thickness of less than or equal to about 10 nanometers. The memory constructions are configured to transit from one memory state having a first phase of the phase change material to a second memory state having a second phase of the phase change material, and are configured so that an entirety of the phase change material film changes from the first phase to the second phase in transitioning from the first memory state to the second memory state. In some embodiments, at least one of the first and second materials may be carbon, W, TiN, TaN or TiAlN. In some embodiments, at least one of the first and second materials may be part of a structure having bands of two or more different compositions.

Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.

Abstract: Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a conductive material in a number of vias and on a substrate structure, the conductive material to serve as a number of conductive lines of the array and coupling the number of conductive lines to the array circuitry.

Abstract: A variable resistor, a nonvolatile memory device and methods of fabricating the same are provided. The variable resistor includes an anode electrode and a cathode electrode, a variable resistive layer including CdS nanoscale particles provided between the anode electrode and the cathode electrode, and an initial metal atom diffusion layer within the variable resistive layer. The variable resistor is a bipolar switching element and configured to be in a reset state when a positive voltage relative to a cathode electrode is applied to the anode electrode, and configured to be in a set state when a negative voltage relative to the cathode electrode is applied to the anode electrode.

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 ? and about 100 ?, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

Abstract: A wiring board includes a substrate having an opening portion, multiple electronic devices positioned in the opening portion, and an insulation layer formed on the substrate such that the insulation layer covers the electronic devices in the opening portion of the substrate. The substrate has a wall surface defining the opening portion and formed such that the opening portion is partially partitioned and the electronic devices are kept from making contact with each other.

Abstract: A method of forming a memory cell includes forming programmable material within an opening in dielectric material over an elevationally inner conductive electrode of the memory cell. Conductive electrode material is formed over the dielectric material and within the opening. The programmable material within the opening has an elevationally outer edge surface angling elevationally and laterally inward relative to a sidewall of the opening. The conductive electrode material is formed to cover over the angling surface of the programmable material within the opening. The conductive electrode material is removed back at least to an elevationally outermost surface of the dielectric material and to leave the conductive electrode material covering over the angling surface of the programmable material within the opening. The conductive electrode material constitutes at least part of an elevationally outer conductive electrode of the memory cell. Memory cells independent of method of manufacture are also disclosed.

Abstract: Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.

Abstract: Disclosed herein is a semiconductor memory device, including: a first electrode formed on a substrate; an ion source layer formed on an upper layer of the first electrode; and a second electrode formed on an upper layer of the ion source layer. Resistance change type memory cells in each of which either a surface of the first electrode or a surface of the ion source layer is oxidized to form a resistance change type memory layer in an interface between the first electrode and the ion source interface are arranged in a array.

Abstract: Low temperature bond balls connect two structures having disparate coefficients of linear thermal expansion. An integrated circuit is made to heat the device such that the low temperature bond balls melt. After melting, the bond balls solidify, and the device is operated with the bond balls solidified. In one example, one of the two structures is a semiconductor substrate, and the other structure is a printed circuit board. The integrated circuit is a die mounted to the semiconductor substrate. The bond balls include at least five percent indium, and the integrated circuit is an FPGA loaded with a bit stream. The bit stream configures the FPGA such that the FPGA has increased power dissipation, which melts the balls. After the melting, a second bit stream is loaded into the FPGA and the FPGA is operated in a normal user-mode using the second bit stream.

Abstract: According to an embodiment, a semiconductor device includes first and second memristors. The first memristor includes a first electrode made of a first material, a second electrode made of a second material, and a first resistive switching film arranged between the first and second electrodes. The first resistive switching film is connected to both the first and second electrodes. The second memristor includes a third electrode made of a third material, a fourth electrode made of the second material, and a second resistive switching film arranged between the third and fourth electrodes. The second resistive switching film is connected to both the third and fourth electrodes. The work function of the first material is smaller than that of the second material. The work function of the third material is larger than that of the second material.

Abstract: According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.

Abstract: A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.

Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.

Abstract: A storage element structure for phase change memory (PCM) cell and a method for forming such a structure are disclosed. The method of forming a storage element structure, comprises providing a multilayer stack comprising a chalcogenide layer (206), a metal cap layer (208), and a dielectric hard mask layer (210), depositing and patterning a photo resist layer (212) on top of the multilayer stack, etching the dielectric hard mask layer using the photo resist layer as etch mask, after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide, etching the chalcogenide layer using the dielectric hard mask layer as etch mask, depositing a spacer dielectric (214) over the multilayer stack and anisotropically etching the spacer dielectric to form sidewall spacers (216) for the multilayer stack.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.

Abstract: A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line and placed on both sides of the gate contact over a layer of insulating material. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars over an insulating material on the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material.

Abstract: According to one embodiment, there are provided a first electrode, a second electrode containing a 1B group element having an Al element added thereto, and a variable resistive layer disposed between the first electrode and the second electrode and having a silicon element.

Abstract: A nanostructure quick-switch memristor includes an upper electrode, a lower electrode and three layers of nanomembrane provided between the upper electrode and the lower electrode. The three layers of nanomembrane consist of an N-type semiconductor layer, a neutral semiconductor layer on the N-type semiconductor layer, and a P-type semiconductor layer on the neutral semiconductor layer. The nanostructure quick-switch memristor of the present invention has the quick switching speed, simple manufacturing method, and low manufacturing cost.

Abstract: A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line. Dielectric pillars are placed on both sides of the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars made of an insulating material over the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material.

Abstract: A variable resistance non-volatile storage device includes: a first line which includes a barrier metal layer and a main layer, and fills an inside of a line trench formed in a first interlayer insulating layer; a first electrode covering a top surface of the first line and comprising a precious metal; memory cell holes formed in a second interlayer insulating layer; a variable resistance layer formed in the memory cell holes and connected to the first electrode; and second lines covering the variable resistance layer and the memory cell holes, wherein in an area near the memory cell holes, the main layer is covered with the barrier metal layer and the first electrode in an arbitrary widthwise cross section of the first line.

Abstract: A method of manufacturing a semiconductor device and a semiconductor device made by the method is disclosed. The method comprises forming a buried N+ layer in an upper portion of a P-type substrate; performing ion implantation on the buried N+ layer; annealing the buried N+ layer; forming an epitaxial semiconductor layer on the buried N+ layer through epitaxial deposition, wherein, an upper portion of said epitaxial semiconductor layer and a portion underlying said P+ region of said epitaxial semiconductor layer are doped to form a P+ region and an N? region, respectively. Increasing the ion implant dosage of the BNL layer, adjusting the method of annealing the BNL layer to increase the width of the BNL layer, or increasing the thickness of the EPI layer, reduces the vertical BJT current gain and suppressed the substrate leakage current.

Abstract: A memory storage device includes: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 ? and about 100 ?, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

Abstract: A phase change structure includes a first phase change material layer pattern and a second phase change material layer pattern. The first phase change material layer pattern may partially fill a minute structure, and the second phase change material layer pattern may fully fill the minute structure. The first phase change material layer pattern may include a first phase change material, and the second phase change material layer pattern may include a second phase change material having a composition substantially different from a composition of the first phase change material.

Abstract: According to one embodiment, there are provided a first electrode, a second electrode, first and second variable-resistance layers that are arranged between the first electrode and the second electrode, and at least one non variable-resistance layer that is arranged so that positions of the first and second variable-resistance layers between the first electrode and the second electrode are symmetrical to each other.

Abstract: According to embodiments of the present invention, a memory component is provided. The memory component includes a storage component comprising a resistance changing material; and an electrical contact coupled to the storage component, wherein the electrical contact comprises silicide, wherein the memory component is free of a metal layer between the storage component and the electrical contact, and wherein the electrical contact is free of a metal layer.

Abstract: A technique used for a semiconductor device formed by stacking multiple structural bodies each having a semiconductor device, for preventing generation of thermal load on a structural body at a lower layer which is caused by a laser used in a step of forming a structural body at an upper layer. In a phase-change memory including multiple stacked memory matrices, a metal film is disposed between a memory matrix at a lower layer and a memory matrix at an upper layer formed over the memory matrix at the lower layer, in which the laser used for forming the memory matrix is reflected at the metal film and prevented from transmitting the metal film, thereby preventing the phase-change material layer, etc. in the memory matrix at the lower layer from being directly heated excessively by the laser.

Abstract: A method to form a voltage sensitive resistor (VSR) read only memory (ROM) device on a semiconductor substrate having a semiconductor device including depositing by chemical vapor deposition (CVD) a titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by at least an order of 102 when a predetermined voltage and current are applied to the VSR; and applying a predetermined voltage and current so as to make the CVD titanium nitride less resistive by at least an order of 102.

Abstract: Provided is a light emitting device, a method for manufacturing the light emitting device, a light emitting device package, and a lighting system. The light emitting device of the embodiment includes a first conductive semiconductor layer; a second conductive semiconductor layer; and a active layer including a quantum well and a quantum bather between the first conductive semiconductor layer and the second conductive semiconductor layer, wherein the energy band gap of the quantum well is gradually changed into parabolic toward a center of the quantum well.

Abstract: In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.

Abstract: A phase change memory may include a plurality of thin layers covering a stack including a chalcogenide and a heater. The thin layers may form a barrier to heat loss. The thin layers may be the same or different materials. The layers may also be chemically or morphologically altered to improve the adverse affect of the interface between the layers on heat transfer.

Abstract: A layout method for electronic components of a double-sided surface mount circuit board is presented, which includes the following steps. At least one first electronic component is fixed on a first side surface of a circuit board through a reflow soldering process. At least one second electronic component is inserted on the first side surface of the circuit board. The other first electronic component is placed on a second side surface of the circuit board, and the other second electronic component is inserted on the second side surface of the circuit board. Finally, a reflow soldering process is performed on the circuit board disposed with the first electronic components and the second electronic components, thereby completing a layout process for the electronic components on the two side surfaces of the circuit board at the same time.

Abstract: Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second electrodes, and a phase change material layer between the first and second electrodes. The phase change material layer has a first portion with a width less than a width of a second portion of the phase change material layer. The first electrode, second electrode and phase change material layer may be oriented at least partially along a same horizontal plane.

Abstract: A Bi—Se doped with Cu, p-type semiconductor, preferably used as an absorber material in a photovoltaic device. Preferably the semiconductor has at least 20 molar percent Cu. In a preferred embodiment, the semiconductor comprises at least 28 molar percent of Cu. In one embodiment, the semiconductor comprises a molar percentage of Cu and Bi whereby the molar percentage of Cu divided by the molar percentage of Bi is greater than 1.2. In a preferred embodiment, the semiconductor is manufactured as a thin film having a thickness less than 600 nm.

Abstract: A semiconductor device may include, but is not limited to: a first insulating film; a second insulating film over the first insulating film; a first memory structure between the first and second insulating films; and a third insulating film between the first and second insulating films. The first memory structure may include, but is not limited to: a heater electrode; and a phase-change memory element between the heater electrode and the second insulating film. The phase-change memory element contacts the heater electrode. The third insulating film covers at least a side surface of the phase-change memory element. Empty space is positioned adjacent to at least one of the heater electrode and the third insulating film.

Abstract: A method of forming a memory cell is provided that includes forming a steering element above a substrate, and forming a reversible resistance-switching element coupled to the steering element. The reversible resistance-switching element includes one or more of TiOx, Ta2O5, Nb2O5, Al2O3, HfO2, and V2O5, and the reversible resistance switching element is formed without being etched. Numerous other aspects are provided.

Abstract: A nonvolatile memory device and a method of fabricating the same are provided. The nonvolatile memory device includes a conductive pillar that extends from a substrate in a first direction, a variable resistor that surrounds the conductive pillar, a switching material layer that surrounds the variable resistor, a first conductive layer that extends in a second direction, and a first electrode that extends in a third direction and contacts the first conductive layer and the switching material layer. Not one of the first, second, and third directions is parallel to another one of the first, second, and third directions.

Abstract: An electrically actuated device includes a first electrode and a second electrode crossing the first electrode at a non-zero angle, thereby forming a junction therebetween. A material is established on the first electrode and at the junction. At least a portion of the material is a matrix region. A current conduction channel extends substantially vertically between the first and second electrodes, and is defined in at least a portion of the material positioned at the junction. The current conduction channel has a controlled profile of dopants therein.

Abstract: A method of fabricating a programmable memory microelectronic device includes depositing onto a first electrode an intermediate layer of a material having a chalcogenide; depositing an ionizable metallic layer on the intermediate layer; irradiating with ultraviolet radiation the ionizable metallic layer so that metallic ions from the ionizable metallic layer diffuse into the intermediate layer to form a chalcogenide material containing metallic ions, and depositing a second electrode on the layer of chalcogenide material containing metallic ions obtained in the prior step. The second and third steps are repeated at least n times, where n is an integer greater than or equal to 1. The ionizable metallic layer deposited during the second step has a sufficiently small thickness that the metallic ions may be diffused totally during the irradiation (third) step.

Abstract: A resistive random access memory (RRAM) includes a resistive memory layer of a transition metal oxide, such as Ni oxide, and is doped with a metal material. The RRAM may include at least one first electrode, a resistive memory layer on the at least one first electrode, the resistive memory layer including a Ni oxide layer doped with at least one element selected from a group consisting of Fe, Co, and Sn, and at least one second electrode on the resistive memory layer. The RRAM device may include a plurality of first electrodes and a plurality of second electrodes, and the resistive memory layer may be between the plurality of first electrodes and the plurality of second electrodes.

Abstract: A nonvolatile memory device includes a substrate, a lower electrode formed above said substrate, a second variable resistance layer formed above said lower electrode and comprising a second transitional metal oxide, a first variable resistance layer formed above said second variable resistance layer and comprising a first transitional metal oxide having an oxygen content that is lower than an oxygen content of the second transitional metal oxide, and an upper electrode formed above said first variable resistance layer. A step is formed in an interface between said lower electrode and said second variable resistance layer. The second variable resistance layer is formed covering the step and has a bend above the step.

Abstract: A method for forming a vertically stacked memory device includes forming a first dielectric material overlying a surface region of a semiconductor substrate, forming first memory cells overlying the first dielectric material including a first top metal wiring spatially extending in a first direction, a first bottom metal wiring spatially extending in a second direction orthogonal to the first direction, and first switching elements sandwiched in intersection regions between the first top metal wiring and the first bottom metal wiring, forming a second dielectric material overlying the first top metal wiring, forming second memory cells overlying the second dielectric material including a second top metal wiring extending in the first direction, a second bottom wiring spatially extending in the second direction, and second switching elements sandwiched in intersection regions of the second top metal wiring and the second bottom metal wiring.

Abstract: A nanostructure quick-switch memristor includes an upper electrode, a lower electrode and three layers of nanomembrane provided between the upper electrode and the lower electrode. The three layers of nanomembrane consist of an N-type semiconductor layer, a neutral semiconductor layer on the N-type semiconductor layer, and a P-type semiconductor layer on the neutral semiconductor layer. The nanostructure quick-switch memristor of the present invention has the quick switching speed, simple manufacturing method, and low manufacturing cost.

Abstract: Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed.

Abstract: A method of forming a MOSFET is provided. The method comprises forming a relatively thin layer of dielectric on a substrate. Depositing a gate material layer on the relatively thin layer of dielectric. Removing portions of the gate material layer to form a first and second gate material regions of predetermined lateral lengths. Introducing a first conductivity type dopant in the substrate to form a top gate using first edges of the first and second gate material regions as masks, Introducing a second conductivity dopant of high dopant density in the substrate to form a drain region adjacent the surface of the substrate using a second edge of the second gate material region as a mask to form a first edge of the drain region, wherein a spaced distance between the top gate and the drain region is determined by the lateral length of the second gate material region.