Abstract: This semiconductor device (100A) includes: an oxide layer (15) which includes a semiconductor region (5) and a conductor region (7) that contacts with the semiconductor region; a source electrode (6s) and a drain electrode (6d) which are electrically connected to the semiconductor region; an insulating layer (11) formed on the source and drain electrodes; a transparent electrode (9) arranged to overlap at least partially with the conductor region with the insulating layer interposed between them; a source line (6a) formed out of the same conductive film as the source electrode; and a gate extended line (3a) formed out of the same conductive film as a gate electrode (3). The source line is electrically connected to the gate extended line via a transparent connecting layer (9a) which is formed out of the same conductive film as the transparent electrode.

Abstract: The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide semiconductor film is processed to form an oxide semiconductor layer; immediately after that, side walls of the oxide semiconductor layer are covered with an insulating oxide; and in second heat treatment, the side surfaces of the oxide semiconductor layer are prevented from being exposed to a vacuum and defects (oxygen deficiency) in the oxide semiconductor layer are reduced.

Abstract: A semiconductor element includes a semiconductor layer, a first and a second conductive unit, a gate electrode, and a gate insulating film. The semiconductor layer includes a first portion, a second portion, and a third portion provided between the first portion and the second portion. The first conductive unit is electrically connected to the first portion. The second conductive unit is electrically connected to the second portion. The gate electrode is separated from the first conductive unit, the second conductive unit, and the third portion. The gate electrode opposes the third portion. The gate insulating film is provided between the third portion and the gate electrode. A concentration of nitrogen of the first portion is higher than a concentration of nitrogen of the third portion. A concentration of nitrogen of the second portion is higher than the concentration of nitrogen of the third portion.

Abstract: A thin film transistor, a manufacturing method thereof and an array substrate are provided. The thin film transistor includes: a gate electrode (102) formed on a substrate (101), a gate insulating layer (103) formed on the gate electrode (102) and covering at least a part of the substrate (101), and a semiconductor layer (105?), a source electrode (107a) and a drain electrode (107b) which are formed on the gate insulating layer (103). The material of the semiconductor layer (105?) is an oxide semiconductor; and the material of the source electrode (107a) and drain electrode (107b) is the oxide semiconductor which is doped. The source electrode (107a), the drain electrode (107b) and the semiconductor layer (105?) are disposed in the same layer.

Abstract: The present teachings relate to a method of enabling metal oxide film growth via solution processes at low temperatures (?350° C.) and in a time-efficient manner. The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices.

Abstract: A thin film transistor includes: a substrate; an oxide semiconductor layer disposed on the substrate; a source electrode and a drain electrode each connected to the oxide semiconductor layer and facing each other with respect to the oxide semiconductor layer; an insulating layer disposed on the oxide semiconductor layer; and a gate electrode disposed on the insulating layer. The insulating layer includes a first layer that includes silicon oxide (SiOx), a second layer that is a hydrogen blocking layer, and a third layer that includes silicon nitride (SiNx). The first, second and third layers are sequentially stacked.

Abstract: Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.

Abstract: A conductive bridge resistive memory device is provided, comprising a first electrode, a memory layer electrically coupled to the first electrode, an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer, a semiconductor layer disposed between the memory layer and the ion-supplying layer, and a second electrode electrically coupled to the ion-supplying layer.

Abstract: An object is to reduce the manufacturing cost of a semiconductor device. An object is to improve the aperture ratio of a semiconductor device. An object is to make a display portion of a semiconductor device display a higher-definition image. An object is to provide a semiconductor device which can be operated at high speed. The semiconductor device includes a driver circuit portion and a display portion over one substrate. The driver circuit portion includes: a driver circuit TFT in which source and drain electrodes are formed using a metal and a channel layer is formed using an oxide semiconductor; and a driver circuit wiring formed using a metal. The display portion includes: a pixel TFT in which source and drain electrodes are formed using an oxide conductor and a semiconductor layer is formed using an oxide semiconductor; and a display wiring formed using an oxide conductor.

Abstract: An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 ? and about 100 ?, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.

Abstract: Disclosed is a ceramic semiconductor capable of increasing the density of surrounding superoxide ions (O2?) after being heated and passing air. An oxide material capable of enhancing a space charge effect is doped when the ceramic semiconductor is formed, and the ceramic semiconductor has a plurality of through holes, such that after the ceramic semiconductor is electrically conducted to generate current and heat, outer shell electrons of the ceramic semiconductor are separated and remained in the through holes of the ceramic semiconductor and accumulated in the through holes to form an electron cloud. After air passes through the through holes, oxygen in the air collides with an electron and then they combine together to form a superoxide ion (O2?), so as to increase the density of surrounding superoxide ions (O2?).

Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract: An object is to provide a highly reliable semiconductor device having stable electric characteristics by using an oxide semiconductor film having stable electric characteristics. Another object is to provide a semiconductor device having higher mobility by using an oxide semiconductor film having high crystallinity. A crystalline oxide semiconductor film is formed over and in contact with an insulating film whose surface roughness is reduced, whereby the oxide semiconductor film can have stable electric characteristics. Accordingly, the highly reliable semiconductor device having stable electric characteristics can be provided. Further, the semiconductor device having higher mobility can be provided.

Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.

Abstract: The object of the present invention is to provide an etching solution composition for etching a metal oxide containing In and a metal oxide containing Zn and In used as a transparent electrode or an oxide semiconductor of an electronic device such as a semiconductor element or a flat panel display (FPD), the etching solution composition being controllable to give a practical etching rate, having high dissolving power toward Zn, and enabling a long solution life due to suppressed variation of the formulation during use. The object is solved by an etching solution composition that enables microfabrication to be carried out for a metal oxide containing In and a metal oxide containing Zn and In used as a transparent electrode or an oxide semiconductor of an electronic device such as a semiconductor element or an FPD, the composition containing water and at least one type of acid, excluding hydrohalic acids, perhalic acids, etc., having an acid dissociation constant pKan at 25° C.

Abstract: A method of preparing metal oxide nanoparticles is described herein. The method involves reacting nanoparticle precursors in the presence of a population of molecular cluster compounds. The molecular cluster compound may or may not contain the same metal as will be present in the metal oxide nanoparticle. Likewise, the molecular cluster compound may or may not contain oxygen. The molecular cluster compounds acts a seeds or templates upon which nanoparticle growth is initiated. As the molecular cluster compounds are all identical, the identical nucleation sites result in highly monodisperse populations of metal oxide nanoparticles.

Abstract: To provide a transistor having highly stable electric characteristics and also a miniaturized structure. Further, also high performance and high reliability of a semiconductor device including the transistor can be achieved. The transistor is a vertical transistor in which a first electrode having an opening, an oxide semiconductor layer, and a second electrode are stacked in this order, a gate insulating layer is provided in contact with side surfaces of the first electrode, the oxide semiconductor layer, and the second electrode, and a ring-shaped gate electrode facing the side surfaces of the first electrode, the oxide semiconductor layer, and the second electrode with the gate insulating layer interposed therebetween is provided. In the opening in the first electrode, an insulating layer in contact with the oxide semiconductor layer is embedded.

Abstract: A thin film transistor 100 according to the invention includes a gate electrode 20, a channel 44, and a gate insulating layer 34 provided between the gate electrode 20 and the channel 44 and made of oxide (possibly containing inevitable impurities; this applies to oxide hereinafter) containing lanthanum and zirconium. The channel 44 is made of channel oxide including first oxide containing indium, zinc, and zirconium (Zr) having an atomic ratio of 0.015 or more and 0.075 or less relative to indium assumed to be 1 in atomic ratio, second oxide containing indium and zirconium (Zr) having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio, or third oxide containing indium and lanthanum having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio.

Abstract: A method of manufacturing a thin film transistor (TFT) substrate in which a TFT including an oxide semiconductor layer is formed, the method including: forming an insulating layer to cover the oxide semiconductor layer; and forming an opening in the insulating layer, wherein the insulating layer includes a first film, a second film which is provided above the first film and is an aluminum oxide film, and a third film which is provided above the second film and is a film including silicon, and the forming of an opening includes: forming a resist pattern above the third film; processing the third film by dry etching; and processing the second film by wet etching.

Abstract: A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having low off-state current (current in an off state) is provided. Alternatively, a semiconductor device including the transistor is provided. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film over the oxide semiconductor film, and a conductive film overlapping with the oxide semiconductor film with the first insulating film or the second insulating film provided between the oxide semiconductor film and the conductive film. The composition of the oxide semiconductor film changes continuously between the first insulating film and the second insulating film.

Abstract: The invention relates to ammoniacal formulations comprising a) at least one hydroxozinc compound and b) at least one compound of an element of the 3rd primary group, to the use thereof, to a method using said formulations to produce layers comprising ZnO and to electronic components produced using same.

Abstract: Embodiments described herein provide improvements to indium-gallium-zinc oxide devices, such as amorphous IGZO thin film transistors, and methods for forming such devices. A relatively thin a-IGZO channel may be utilized. A plasma treatment chemical precursor passivation may be provided to the front-side a-IGZO interface. High-k dielectric materials may be used in the etch-stop layer at the back-side a-IGZO interface. A barrier layer may be formed above the gate electrode before the gate dielectric layer is deposited. The conventional etch-stop layer, typically formed before the source and drain regions are defined, may be replaced by a pre-passivation layer that is formed after the source and drain regions are defined and may include multiple sub-layers.

Abstract: A semiconductor device includes a gate electrode having higher Gibbs free energy for oxidation than a gate insulating film. An oxide semiconductor layer having a fin shape is formed over an insulating surface, a gate insulating film is formed over the oxide semiconductor layer, a gate electrode including an oxide layer and facing top and side surfaces of the oxide semiconductor layer with the gate insulating film located therebetween is formed, and then by performing heat treatment, a gate electrode is reduced and oxygen is supplied to the oxide semiconductor layer through the gate insulating film.

Abstract: Provided are an oxide semiconductor layer in which the number of defects is reduced and a highly reliable semiconductor device including the oxide semiconductor. A first oxide semiconductor layer containing a single metal element as a constituent element is formed over a substrate by a thermal chemical vapor deposition method. A second oxide semiconductor layer containing two or more metal elements as constituent elements is formed successively after the first oxide semiconductor layer is formed. The second oxide semiconductor layer is formed by epitaxial growth using the first oxide semiconductor layer as a seed crystal. A channel is formed in the second oxide semiconductor layer.

Abstract: A flat panel display device with oxide thin film transistors and a fabricating method thereof are disclosed. The flat panel display device includes: a substrate; gate lines and data lines formed to cross each other and define a plurality of pixel regions on the substrate; the thin film transistors each including an oxide channel layer which is formed at an intersection of the gate and data lines; a pixel electrode and a common electrode formed in the pixel region with having a passivation layer therebetween; and step coverage compensation patterns formed at a step portion formed by the gate line and a gate electrode of the thin film transistor.

Abstract: An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. An impurity such as hydrogen or moisture (e.g., a hydrogen atom or a compound containing a hydrogen atom such as H2O) is eliminated from an oxide semiconductor layer with use of a halogen element typified by fluorine or chlorine, so that the impurity concentration in the oxide semiconductor layer is reduced. A gate insulating layer and/or an insulating layer provided in contact with the oxide semiconductor layer can be formed to contain a halogen element. In addition, a halogen element may be attached to the oxide semiconductor layer through plasma treatment under an atmosphere of a gas containing a halogen element.

Abstract: To provide a transistor having high field effect mobility. To provide a transistor having stable electrical characteristics. To provide a transistor having low off-state current (current in an off state). To provide a semiconductor device including the transistor. The semiconductor device includes a semiconductor; a source electrode and a drain electrode including regions in contact with a top surface and side surfaces of the semiconductor; a gate insulating film including a region in contact with the semiconductor; and a gate electrode including a region facing the semiconductor with the gate insulating film provided therebetween. A length of a region of the semiconductor, which is not in contact with the source and drain electrodes, is shorter than a length of a region of the semiconductor, which is in contact with the source and drain electrodes, in a channel width direction.

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

Abstract: Provided are an oxide semiconductor layer in which the number of defects is reduced and a highly reliable semiconductor device including the oxide semiconductor. A first oxide semiconductor layer having a crystal part is formed over a substrate by a sputtering method. A second oxide semiconductor layer is formed by a thermal chemical vapor deposition method over the first oxide semiconductor layer. The second oxide semiconductor layer is formed by epitaxial growth using the first oxide semiconductor layer as a seed crystal. A channel is formed in the second oxide semiconductor layer.

Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

Abstract: A phase change memory cell, an array of the phase change memory cells, and a method for fabricating the phase change memory cells. The phase change memory cell includes a bottom electrode, a heating element, and a heat shield. During programming of the phase change memory cell, the bottom electrode passes current to the phase change memory cell. The heating element is electrically coupled to the bottom electrode and generates heat during the programming of the phase change memory cell. The heat shield is thermally conductive and surrounds at least a portion of the heating element. The heat shield conducts heat generated during programming of the phase change memory cell to the bottom electrode.

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.

Abstract: A thin film transistor includes: a gate electrode, a source electrode, and a drain electrode; an oxide semiconductor layer provided on one side of the gate electrode with an insulating film in between, the oxide semiconductor layer being provided in a region not facing the source electrode and the drain electrode and being electrically connected to the source electrode and the drain electrode; and a low resistance oxide layer provided in a region facing the source electrode and in a region facing the drain electrode, the regions being adjacent to the oxide semiconductor layer, and the low resistance oxide layer having an electric resistivity lower than an electric resistivity of the oxide semiconductor layer.

Abstract: A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (?fG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO2 interfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.

Abstract: An object is to provide a deposition technique for depositing an oxide semiconductor film. Another object is to provide a method for manufacturing a highly reliable semiconductor element using the oxide semiconductor film. A novel sputtering target obtained by removing an alkali metal, an alkaline earth metal, and hydrogen that are impurities in a sputtering target used for deposition is used, whereby an oxide semiconductor film containing a small amount of those impurities can be deposited.

Abstract: A display device includes: a substrate; a signal line on the substrate; a signal input line on the substrate and connected to a driver; a first insulating layer between the signal line and the signal input line; a second insulating layer on the signal line, the signal input line and the first insulating layer; an organic layer on the second insulating layer; a first contact hole defined in the organic layer, the first insulating layer and the second insulating layer and exposing the signal line; a second contact hole defined in the organic layer and the second insulating layer and exposing the signal input line; and a connecting member on the organic layer, and connecting the signal line and the signal input line to each other through the first contact hole and the second contact hole, respectively.

Abstract: Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.

Abstract: An organic light emitting diode display device and method of fabricating the device according to an embodiment includes a substrate; an oxide semiconductor layer over the substrate; a planarization layer over the oxide semiconductor layer; an emitting diode over the planarization layer; a passivation layer over the emitting diode; and a hydrogen blocking layer between the planarization layer and the passivation layer to block hydrogen diffusion from the passivation layer to the oxide semiconductor layer.

Abstract: A thin-film semiconductor substrate includes a top-gate first TFT, a top-gate second TFT, and a data line (source line), in which the first TFT has a first semiconductor layer, a first gate insulating film, a first gate electrode, a first source electrode, a first drain electrode, and a first protection layer, the second TFT has a second semiconductor layer, a second gate insulating film, a second gate electrode, a second source electrode, a second drain electrode, and a second protection layer, the data line is connected to the first source electrode, the first drain electrode is an extension of the second gate electrode, and the second gate electrode is thinner than the data line.

Abstract: A display apparatus includes: a substrate defining transistor and wiring areas; a thin film transistor in the transistor area and including a gate electrode, an active layer, and source and drain electrodes; an etch prevention layer in the transistor area, absent in the wiring area and covering the active layer, and first and second contact holes defined in the etch prevention layer and through which the active layer is electrically coupled to the source and drain electrodes; a first wiring layer in the wiring area; a first insulating layer which covers the gate electrode and the first wiring layer, and a third contact hole defined in the first insulating layer in the wiring area and exposing the first wiring layer; and a second wiring layer on the first insulating layer and in the wiring area, and electrically coupled to the first wiring layer via the third contact hole.

Abstract: A method for adjusting threshold of a semiconductor device is provided. In a plurality of semiconductor devices each including a semiconductor, a source or drain electrode electrically in contact with the semiconductor, a gate electrode, and a charge trap layer between a gate electrode and the semiconductor, a state where the potential of the gate electrode is set higher than the potential of the source or drain electrode while the semiconductor devices are heated at 150° C. or higher and 300° C. or lower is kept for one second or longer to trap electrons in the charge trap layer, so that the threshold is increased and Icut is reduced. Here, the potential difference between the gate electrode and the source or drain electrode is set so that it is different between the semiconductor devices, and the thresholds of the semiconductor devices are adjusted to be appropriate to each purpose.

Abstract: This semiconductor device (100A) includes: a gate electrode (3) formed on a substrate (2); a gate insulating layer (4) formed on the gate electrode; an oxide layer (50) which is formed on the gate insulating layer and which includes a semiconductor region (51) and a conductor region (55); source and drain electrodes (6s, 6d) electrically connected to the semiconductor region; a protective layer (11) formed on the source and drain electrodes; and a transparent electrode (9) formed on the protective layer. At least part of the transparent electrode overlaps with the conductor region with the protective layer interposed between them. The upper surface of the conductor region contacts with a reducing insulating layer (61) with the property of reducing an oxide semiconductor included in the oxide layer. The reducing insulating layer is out of contact with the channel region of the semiconductor region.

Abstract: A highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics, and a manufacturing method thereof. In the manufacturing method of the semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region is an oxide semiconductor layer, heat treatment which reduces impurities such as moisture to improve the purity of the oxide semiconductor layer and oxidize the oxide semiconductor layer (heat treatment for dehydration or dehydrogenation) is performed. Not only impurities such as moisture in the oxide semiconductor layer but also those existing in a gate insulating layer are reduced, and impurities such as moisture existing in interfaces between the oxide semiconductor layer and films provided over and under and in contact with the oxide semiconductor layer are reduced.

Abstract: A method for manufacturing a semiconductor device with adjusted threshold is provided. In a semiconductor device including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is provided, a charge trap layer provided between the first gate electrode and the semiconductor, and a gate insulating layer provided between the second gate electrode and the semiconductor, a threshold is increased by trapping electrons in the charge trap layer by keeping a potential of the first gate electrode at a potential higher than a potential of the source or drain electrode for 1 second or more while heating. After the threshold adjustment process, the first gate electrode is removed or insulated from other circuits. Alternatively, a resistor may be provided between the first gate electrode and other circuits.

Abstract: A thin film transistor includes a gate electrode on a substrate, a gate insulation layer which covers the gate electrode on the substrate, an oxide semiconductor pattern which is disposed on the gate insulation layer and includes a channel portion superimposed over the gate electrode, and low resistance patterns provided at edges of the channel portion, respectively, and including oxygen vacancies, a channel passivation layer on the oxide semiconductor pattern, a reaction layer which covers the oxide semiconductor pattern and the channel passivation layer, and includes a metal oxide, and a source electrode and a drain electrode which contact the oxide semiconductor pattern.

Abstract: Provided is a novel structure of a field effect transistor using a metal-semiconductor junction. The field effect transistor includes a wiring which is provided over a substrate and also functions as a gate electrode; an insulating film which is provided over the wiring, has substantially the same shape as the wiring, and also functions as a gate insulating film; a semiconductor layer which is provided over the insulating film and includes an oxide semiconductor and the like; an oxide insulating layer which is provided over the semiconductor layer and whose thickness is 5 times or more as large as the sum of the thickness of the insulating film and the thickness of the semiconductor layer or 100 nm or more; and wirings which are connected to the semiconductor layer through openings provided in the oxide insulating layer.

Abstract: A thin film transistor substrate includes a substrate, a data line disposed on the substrate and which extends substantially in a predetermined direction, a light blocking layer disposed on the substrate and including a metal oxide including zinc manganese oxide, zinc cadmium oxide, zinc phosphorus oxide or zinc tin oxide, a gate electrode disposed on the light blocking layer, a signal electrode including a source electrode and a drain electrode spaced apart from the source electrode, where the source electrode is connected to the data line, and a semiconductor pattern disposed between the source electrode and the drain electrode.