Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device Patents (Class 438/107)
-
Patent number: 12218037Abstract: A semiconductor device with front and back surfaces, and a side surface having first and second sides opposite to each other, and third and fourth sides opposite to each other. The semiconductor device includes a plurality of circuit boards surrounded by the first to fourth sides, the circuit boards each including an insulating board and a conductive plate, a first lead frame including a first terminal portion extending upward and being bent toward the first side, a second lead frame including a second terminal portion extending upward and being bent toward the second side, and a resin-filled portion provided in a first gap between the first terminal portion and the second terminal portion, the resin-filled portion having a concave portion recessed in a direction from the front surface toward the back surface so that an insulating insertion member is inserted into the concave portion.Type: GrantFiled: February 14, 2024Date of Patent: February 4, 2025Assignee: FUJI ELECTRIC CO., LTD.Inventor: Hisato Inokuchi
-
Patent number: 12219767Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.Type: GrantFiled: November 29, 2023Date of Patent: February 4, 2025Assignee: Kioxia CorporationInventor: Tomoya Sanuki
-
Patent number: 12218593Abstract: A physical arrangement of at least two power switches and at least one capacitor in a power loop. At least one of the switches is formed of at least two parallel electronic devices, such as transistors. The arrangement minimizes total power loop impedance and results in approximately equal impedance in each parallel branch of the switch formed of two parallel devices, thereby resulting in approximately equal currents in the switches.Type: GrantFiled: September 12, 2022Date of Patent: February 4, 2025Assignee: Efficient Power Conversion CorporationInventors: John S. Glaser, Yuanzhe Zhang, Michael A. de Rooij
-
Patent number: 12211830Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.Type: GrantFiled: March 6, 2023Date of Patent: January 28, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Chanho Kim, Dongku Kang, Daeseok Byeon
-
Patent number: 12191362Abstract: Problem: To reduce the likelihood of insufficient electrical continuity in wiring in a semiconductor device.Type: GrantFiled: March 9, 2022Date of Patent: January 7, 2025Assignee: AOI Electronics Co., LtdInventor: Takashi Suzuki
-
Patent number: 12148707Abstract: Homogeneous chiplets configurable both as a two-dimensional system or a three-dimensional system are described. An example chiplet system has a first homogeneous chiplet (HC) including a first integrated circuit (IC) die having a first logic block and a first memory that are interconnected via a first path for transfer of data signals between the first logic block and the first memory block. A second HC including a second IC die having a second logic block and a second memory block, interconnected via a second path for transfer of data signals between the second logic block and the second memory block, is stacked vertically on top of the first HC to provide a third path for transfer of data signals between the first logic block and the second memory block and a fourth path for transfer of data signals between the second logic block and the first memory block.Type: GrantFiled: April 25, 2022Date of Patent: November 19, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Haohua Zhou, Xiaoling Xu
-
Patent number: 12142588Abstract: A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.Type: GrantFiled: March 24, 2023Date of Patent: November 12, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joohee Jang, Seokho Kim, Hoonjoo Na, Jaehyung Park, Kyuha Lee
-
Patent number: 12136565Abstract: Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. Methods and systems for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die.Type: GrantFiled: August 19, 2022Date of Patent: November 5, 2024Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Michael G. Kelly, Ronald Patrick Huemoeller, Won Chul Do, David Jon Hiner
-
Patent number: 12136612Abstract: A package includes a building block. The building block includes a device die, an interposer bonded with the device die, and a first encapsulant encapsulating the device die therein. The package further includes a second encapsulant encapsulating the building block therein, and an interconnect structure over the second encapsulant. The interconnect structure has redistribution lines electrically coupling to the device die. A power module is over the interconnect structure. The power module is electrically coupled to the building block through the interconnect structure.Type: GrantFiled: April 4, 2022Date of Patent: November 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Tin-Hao Kuo
-
Patent number: 12119283Abstract: Provided are a heat dissipation structure, a method for forming a heat dissipation structure, and a semiconductor structure. The heat dissipation structure includes a first heat dissipation ring and a second heat dissipation ring. The first heat dissipation ring is formed in a dielectric layer around a Through Silicon Via (TSV) and in contact with the TSV. The TSV passes through a silicon substrate and the dielectric layer. The second heat dissipation ring is formed around the first heat dissipation ring, and in contact with the first heat dissipation ring. The second heat dissipation ring has a heat dissipation gap within it. A dimension of the second heat dissipation ring in a first direction is less than that of the first heat dissipation ring in the first direction. The first direction is a thickness direction of the silicon substrate.Type: GrantFiled: February 11, 2022Date of Patent: October 15, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Luguang Wang
-
Patent number: 12100665Abstract: The present invention provides a semiconductor package structure including a first stacked structure and a second stacked structure, which is stacked on the first stacked structure. The first stacked structure includes a first dielectric layer, a first power chip, a first conductive connecting element, a first conductive pillar and a first patterned conductive layer. The second stacked structure includes a second dielectric layer, a second power chip, a second conductive connecting element, a second conductive pillar, a second patterned conductive layer, and a third patterned conductive layer. The first power chip and the second power chip are stacked to provide a smaller volume semiconductor package structure, that the first power chip and the second power chip may be directly electrically connected through the circuit structure and may eliminate the related disadvantages of the lead frame. In addition, a manufacturing method of a semiconductor package structure is also disclosed.Type: GrantFiled: November 16, 2021Date of Patent: September 24, 2024Assignee: Phoenix Pioneer Technology Co., Ltd.Inventor: Che-Wei Hsu
-
Patent number: 12089406Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes providing a substrate, forming memory cells over the substrate, depositing a first dielectric layer to cover the memory cells, forming at least one contact pad over the substrate, depositing a second dielectric layer over the at least one contact pad, forming first connecting pads over the second dielectric layer, bonding the first connecting pads with second connecting pads of a peripheral structure, and exposing the at least one contact pad from a back side of the substrate.Type: GrantFiled: February 25, 2021Date of Patent: September 10, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yongqing Wang, Siping Hu
-
Patent number: 12082412Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.Type: GrantFiled: January 21, 2021Date of Patent: September 3, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Young Lim, Jongsoo Kim, Jesuk Moon, Dongwoo Kim, Sunil Shim, Wonseok Cho
-
Patent number: 12081192Abstract: A MEMS device may include: (i) a lower cavity, including a first island, formed within a first layer of the MEMS device; (ii) an upper cavity, including a second island, formed within a second layer of the MEMS device; (iii) a MEMS resonating element arranged in a device layer of the MEMS device and anchored via the first and second islands; (iv) a first set of electrodes for electrostatic actuation and sensing of the MEMS resonating element in an in-plane mode that is arranged in the device layer of the MEMS device; and (v) a second set of electrodes for electrostatic actuation and sensing of the MEMS resonating element in an out-of-plane mode that is electrically isolated from the first set of electrodes and located in the first or second layer of the MEMS device, and wherein the out-of-plane mode is a torsional mode or a saddle mode.Type: GrantFiled: May 26, 2023Date of Patent: September 3, 2024Assignee: Stathera IP Holdings, Inc.Inventors: Vamsy P. Chodavarapu, George Xereas
-
Patent number: 12080685Abstract: In a micro-device integration process, a donor substrate is provided on which to conduct the initial manufacturing and pixelation steps to define the micro devices, including functional, e.g. light emitting layers, sandwiched between top and bottom conductive layers. The microdevices are then transferred to a system substrate for finalizing and electronic control integration. The transfer may be facilitated by various means, including providing a continuous light emitting functional layer, breakable anchors on the donor substrates, temporary intermediate substrates enabling a thermal transfer technique, or temporary intermediate substrates with a breakable substrate bonding layer.Type: GrantFiled: October 29, 2020Date of Patent: September 3, 2024Assignee: VueReal Inc.Inventors: Gholamreza Chaji, Ehsanollah Fathi
-
Patent number: 12071342Abstract: MEMS based sensors, particularly capacitive sensors, potentially can address critical considerations for users including accuracy, repeatability, long-term stability, ease of calibration, resistance to chemical and physical contaminants, size, packaging, and cost effectiveness. Accordingly, it would be beneficial to exploit MEMS processes that allow for manufacturability and integration of resonator elements into cavities within the MEMS sensor that are at low pressure allowing high quality factor resonators and absolute pressure sensors to be implemented. Embodiments of the invention provide capacitive sensors and MEMS elements that can be implemented directly above silicon CMOS electronics.Type: GrantFiled: October 24, 2022Date of Patent: August 27, 2024Assignee: Stathera IP Holding, Inc.Inventors: Vamsy Chodavarapu, George Xereas
-
Patent number: 12068296Abstract: A method for wafer bonding includes: providing a semiconductor wafer having a first main face; fabricating at least one semiconductor device in the semiconductor wafer, wherein the semiconductor device is arranged at the first main face; generating trenches and a cavity in the semiconductor wafer such that the at least one semiconductor device is connected to the rest of the semiconductor wafer by no more than at least one connecting pillar; arranging the semiconductor wafer on a carrier wafer such that the first main face faces the carrier wafer; attaching the at least one semiconductor device to the carrier wafer; and removing the at least one semiconductor device from the semiconductor wafer by breaking the at least one connecting pillar.Type: GrantFiled: January 25, 2022Date of Patent: August 20, 2024Assignee: Infineon Technologies AGInventors: Stefan Hampl, Marco Haubold, Kerstin Kaemmer, Norbert Thyssen
-
Patent number: 12028986Abstract: A method for mounting an electronic component on a resin base material, the method including: (1) preparing the resin base material having a wiring pattern formed of a conductive paste; (2) supplying a solder paste which contains solder particles and a thermosetting resin in a state before curing to a predetermined portion of the resin base material; (3) placing the electronic component on the solder paste; and (4) heating the resin base material to heat the solder paste to a temperature in a range from 105° C. to 130° C., inclusive to melt the solder particles, and starting a curing exothermic reaction of the thermosetting resin, wherein a melting temperature of the solder particles is in a range from 90° C. to 130° C., inclusive, and a peak temperature of the curing exothermic reaction of the thermosetting resin is in a range from 135° C. to 165° C., inclusive.Type: GrantFiled: July 2, 2021Date of Patent: July 2, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Naomichi Ohashi, Yasuhiro Okawa, Koso Matsuno
-
Patent number: 12021042Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.Type: GrantFiled: March 21, 2023Date of Patent: June 25, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Ching, Shu-Shen Yeh, Chien-Hung Chen, Hui-Chang Yu, Yu-Min Cheng
-
Patent number: 12015433Abstract: A radio frequency module includes a module board, a transmission power amplifier, a first inductance element mounted on a first principal surface and connected to an output terminal of the transmission power amplifier, a reception low-noise amplifier, and a second inductance element mounted on a first principal surface connected to an input terminal of the reception low-noise amplifier. In a plan view of the module board, a conductive member mounted on the first principal surface is disposed between the first inductance element and the second inductance element.Type: GrantFiled: May 1, 2023Date of Patent: June 18, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Takanori Uejima
-
Patent number: 12009282Abstract: A memory device includes: a wiring substrate including a multilevel wiring layer and first and second surfaces at opposite sides; a control element embedded in the wiring substrate and having first and second element surfaces at opposite sides, with multiple electrode pads connected to the multilevel wiring layer at the first element surface; a first heat dissipation member at a region of the first surface overlapping the control element; a heat dissipation structure facing the second element surface and exposed at the second surface; and at least one memory element connected with the multilevel wiring layer at a first surface region not overlapping the control element. The multilevel wiring layer includes a signal pattern electrically connecting the control element with the memory element or the external connection terminal, and a heat dissipation conductor pattern forming a heat dissipation path between the control element and the first heat dissipation member.Type: GrantFiled: March 11, 2021Date of Patent: June 11, 2024Assignee: MEIKO ELECTRONICS CO., LTD.Inventor: Shuzo Akejima
-
Patent number: 11984386Abstract: A semiconductor device includes a semiconductor element, a substrate including an insulating board, and first conductive plate and second conductive plate on the insulating board, and a wiring unit including a first lead frame electrically connected to the first conductive plate and having a first wiring portion wired parallel to the insulating board, a second lead frame electrically connected to the second conductive plate, and having a second wiring portion above the first lead frame and overlapping the first wiring portion in a plan view at a superimposed area, a gap between the first and second lead frames being formed in the superimposed area, and a wiring holding portion holding the first and second lead frames. The wiring holding portion includes a wiring gap portion which fills in the gap, and a wiring surface portion disposed over the second wiring portion in the superimposed area.Type: GrantFiled: July 28, 2021Date of Patent: May 14, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventor: Hisato Inokuchi
-
Patent number: 11948930Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.Type: GrantFiled: November 13, 2020Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Chuan Chang, Szu-Wei Lu, Chen-Hua Yu
-
Patent number: 11942431Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.Type: GrantFiled: July 27, 2022Date of Patent: March 26, 2024Assignee: KIOXIA CORPORATIONInventors: Nobuyuki Momo, Keisuke Nakatsuka
-
Patent number: 11935774Abstract: Provided is an assembly jig set of semiconductor module having a plurality of semiconductor chips, the assembly jig set comprising: a first outer frame jig; and a plurality of inner piece jigs positioned by the first outer frame jig and each having a sectioned shape corresponding to the first outer frame jig, wherein one of the inner piece jigs has a plurality of opening portions for positioning the semiconductor chips. A manufacturing method of a semiconductor module using an assembly jig set is provided.Type: GrantFiled: May 23, 2022Date of Patent: March 19, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kazunaga Onishi, Takeshi Yokoyama, Masaki Maruyama
-
Patent number: 11915996Abstract: An integrated circuit structure that includes a first integrated circuit package and a second integrated circuit package is described. The two packages can be stacked above, for example, a printed circuit board. The top package is inverted, such that a first die of that top package is facing a second die of the bottom package. A cooling arrangement is in a gap between the first and second integrated circuit packages, and is thermally coupled to the first and second die. The cooling arrangement is to transfer heat generated by a first die of the first integrated circuit package and a second die of the second integrated circuit package. In some cases, structures comprising electrically conductive material (e.g., metal) are encapsulated by a molding compound or insulator, and extend between a first substrate of the first integrated circuit package and a second substrate of the second integrated circuit package.Type: GrantFiled: May 9, 2019Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Robert Sankman, Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
-
Patent number: 11901274Abstract: A packaged device (110) includes a substrate (114) and one or more contacts (118) disposed on a side of the substrate (114). Structures of the packaged device (110) define at least in part a recess region (120) that extends from the side of the substrate (114) and through the substrate (114), where one or more contacts (124) of a second hardware interface are disposed in the recess region (120). The one or more contacts (118) of the first hardware interface enable connection of the packaged device (110) to a printed circuit board. The one or more contacts (124) of the second hardware interface enable connection between one or more IC dies of the packaged device (110) and another IC die (150) that is a component of the packaged device (110) or of a different packaged device.Type: GrantFiled: September 25, 2015Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Bin Liu, John G. Meyers, Florence R. Pon
-
Patent number: 11871576Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.Type: GrantFiled: December 7, 2020Date of Patent: January 9, 2024Assignee: Kioxia CorporationInventors: Yoshiaki Fukuzumi, Hideaki Aochi, Mie Matsuo, Kenichiro Yoshii, Koichiro Shindo, Kazushige Kawasaki, Tomoya Sanuki
-
Patent number: 11837596Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.Type: GrantFiled: December 22, 2022Date of Patent: December 5, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
-
Patent number: 11805646Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.Type: GrantFiled: November 24, 2020Date of Patent: October 31, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Jifeng Zhu, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
-
Patent number: 11798861Abstract: Embodiments may relate to a microelectronic package that includes a lid coupled with a package substrate such that a die is positioned between the lid and the package substrate. The lid may include a heating element that is to heat an area between the lid and the die. Other embodiments may be described or claimed.Type: GrantFiled: July 8, 2019Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Peng Li, Kelly P. Lofgreen, Manish Dubey, Bamidele Daniel Falola, Ken Hackenberg, Shenavia S. Howell, Sergio Antonio Chan Arguedas, Yongmei Liu, Deepak Goyal
-
Patent number: 11791284Abstract: Provided is a method suitable for efficiently manufacturing a semiconductor device while preventing warpage of the wafer laminate in manufacturing a semiconductor device in which semiconductor elements are multilayered through laminating wafers in which the semiconductor elements are fabricated. The method includes at least: preparing a plurality of first wafer laminates each having a laminate configuration including a first and second wafers each having an element forming surface and a back surface opposite from the element forming surface, the laminate configuration wherein the element forming surface sides of the first and second wafers are bonded to each other; thinning the first wafer of the first wafer laminate to form a first wafer laminate having the thinned first wafer; and bonding the thinned first wafer sides of two first wafer laminates having undergone the thinning to each other to form a second wafer laminate.Type: GrantFiled: October 18, 2019Date of Patent: October 17, 2023Assignee: Daicel CorporationInventors: Naoko Tsuji, Akira Yamakawa, Katsuhiko Sumita
-
Patent number: 11776880Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.Type: GrantFiled: October 19, 2020Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
-
Patent number: 11769747Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a first pad provided in the first insulator, and including first and second layers provided on lateral and lower faces of the first insulator in order. The device further includes a second insulator provided on the first insulator. The device further includes a second pad provided on the first pad in the second insulator, and including third and fourth layers provided on lateral and upper faces of the second insulator in order. The device further includes a first portion provided between an upper face of the first pad and a lower face of the second insulator or between a lower face of the second pad and an upper face of the first insulator, and including a metal element same as a metal element included in the first layer or the third layer.Type: GrantFiled: June 17, 2021Date of Patent: September 26, 2023Assignee: Kioxia CorporationInventors: Genki Sawada, Masayoshi Tagami, Jun Iijima, Ippei Kume, Kiyomitsu Yoshida
-
Patent number: 11728306Abstract: A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.Type: GrantFiled: January 6, 2022Date of Patent: August 15, 2023Assignee: VueReal Inc.Inventors: Gholamreza Chaji, Ehsanollah Fathi
-
Patent number: 11715695Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.Type: GrantFiled: December 17, 2021Date of Patent: August 1, 2023Assignee: Intel CorporationInventors: Mathew J. Manusharow, Jonathan Rosenfeld
-
Patent number: 11705349Abstract: A transfer substrate is configured to transfer a plurality of micro components from a first substrate to a second substrate. The transfer substrate comprises a base and a plurality of transfer heads. The base includes an upper surface. The plurality of transfer heads is disposed on the upper surface of the base, wherein each transfer head includes a first surface and a second surface opposite to each other and the transfer heads contact the base with the first surfaces thereof. A plurality of adhesion lumps is separated from each other, wherein each adhesion lump is disposed on the second surface of one of the transfer heads. A CTE of the base is different from CTEs of the transfer heads.Type: GrantFiled: April 17, 2019Date of Patent: July 18, 2023Assignee: PlayNitride Inc.Inventors: Yu-Hung Lai, Tzu-Yang Lin, Yun-Li Li
-
Patent number: 11699640Abstract: A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/?30 ?m at the first side of the power module.Type: GrantFiled: June 21, 2021Date of Patent: July 11, 2023Assignee: Infineon Technologies AGInventors: Thomas Stoek, Frank Daeche, Chee Voon Tan
-
Patent number: 11688700Abstract: Methods and apparatus for providing an assembly including a base substrate, a lid substrate, and a ring frame between the base substrate and the lid substrate to define a protected volume, where the ring frame includes through vias. A die may be contained in the protected volume. Sensor circuitry can include conductive pillars in the protected volume and the die can include circuity to determine an impedance of the pad and the pillars for tamper detection. An edge cap can be coupled to at least one side of the assembly for tamper detection.Type: GrantFiled: June 11, 2021Date of Patent: June 27, 2023Assignee: RAYTHEON COMPANYInventors: Jason M. Kehl, Jason G. Milne, Steve F. Mayrose, Aaron George
-
Patent number: 11674721Abstract: A refrigerator according to an embodiment of the present invention includes: a compressor configured to compress a refrigerant; and an inverter module configured to control the compressor, wherein the inverter module includes: a heatsink provided with a cooling passage through which coolant passes; a coolant inlet connected to the heatsink to communicate with an inlet of the cooling passage; a coolant outlet connected to the heatsink to communicate with an outlet of the cooling passage; at least one insulated gate bipolar transistor (IGBT) disposed on a top surface of the heatsink; and at least one diode disposed to be spaced apart from the IGBT on the top surface of the heatsink, wherein the cooling passage includes: an IGBT cooling passage that is closer to the coolant inlet among the coolant inlet and the coolant outlet; and a diode cooling passage that is closer to the coolant outlet among the coolant inlet and the coolant outlet, wherein the diode cooling passage is disposed behind the IGBT cooling passaType: GrantFiled: July 10, 2019Date of Patent: June 13, 2023Assignee: LG ELECTRONICS INC.Inventors: Kiwook Lee, Namsoo Lee, Chanmyung Park
-
Patent number: 11676901Abstract: A semiconductor device includes a lower wafer including a first substrate, a first dielectric layer that is defined on the first substrate, and a first wiring line that is defined in the first dielectric layer; an upper wafer including a second substrate, an isolation layer that is defined in an upper surface of the second substrate, a second dielectric layer, bonded to an upper surface of the first dielectric layer, that covers a lower surface of the second substrate and that includes at least one portion defined in the lower surface of the second substrate below and in contact with the isolation layer, and a third dielectric layer that is defined on the upper surface of the second substrate, and a second wiring line that is defined on the third dielectric layer; and a through via passing through, under the second wiring line, the third dielectric layer, the isolation layer, the second dielectric layer under the isolation layer and the first dielectric layer, and coupling the second wiring line and the firstType: GrantFiled: January 13, 2021Date of Patent: June 13, 2023Assignee: SK hynix Inc.Inventor: Sung Lae Oh
-
Patent number: 11664781Abstract: MEMS based sensors, particularly capacitive sensors, potentially can address critical considerations for users including accuracy, repeatability, long-term stability, ease of calibration, resistance to chemical and physical contaminants, size, packaging, and cost effectiveness. Accordingly, it would be beneficial to exploit MEMS processes that allow for manufacturability and integration of resonator elements into cavities within the MEMS sensor that are at low pressure allowing high quality factor resonators and absolute pressure sensors to be implemented. Embodiments of the invention provide capacitive sensors and MEMS elements that can be implemented directly above silicon CMOS electronics.Type: GrantFiled: September 14, 2020Date of Patent: May 30, 2023Assignee: Stathera IP Holdings Inc.Inventors: Vamsy Chodavarapu, George Xereas
-
Patent number: 11664292Abstract: A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.Type: GrantFiled: June 7, 2021Date of Patent: May 30, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ae-Nee Jang, Seung-Duk Baek, Tae-Heon Kim
-
Patent number: 11658070Abstract: A method of forming a semiconductor structure includes following steps. A first wafer is bonded to a second wafer, in which the first wafer includes a first substrate and a first conductive pad above a first surface of the first substrate, and the second wafer comprises a second substrate and a second conductive pad above a second surface of the second substrate. A mask layer is formed above the first substrate. The mask layer and the first substrate are etched to form a first opening in the first substrate. A sacrificial spacer is formed in the first substrate at a sidewall of the first opening. The first conductive pad is etched to form a second opening communicated to the first opening. A conductive material is filled in the first opening and the second opening to form a conductive structure interconnecting the first and second conductive pads.Type: GrantFiled: December 8, 2021Date of Patent: May 23, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chiang-Lin Shih, Shing-Yih Shih
-
Patent number: 11658045Abstract: A method for producing an electronic arrangement includes providing an aluminium body and a power electronic unit. The power electronic unit includes a base plate and an electronic component. The method includes pre-treating a joining region of a main surface of the aluminium body; coating the pre-treated joining region with a sinter paste including at least one of copper particles and silver particles; positioning the power electronic unit with a second side of the base plate on the main surface of the aluminium body; joining the power electronic unit and the aluminium body in the joining region with supply of heat, wherein the aluminium body and the power electronic unit are connected via the sinter paste in a materially bonded and heat-transferring manner.Type: GrantFiled: November 10, 2020Date of Patent: May 23, 2023Inventor: Matthias Tuerpe
-
Patent number: 11651976Abstract: Optical packages and methods of fabrication are described. In an embodiment, a controller chip is embedded along with optical components, including a photodetector (PD) and one or more emitters, in a single package.Type: GrantFiled: June 24, 2020Date of Patent: May 16, 2023Assignee: Apple Inc.Inventors: Kishore N. Renjan, Bilal Mohamed Ibrahim Kani, Kyusang Kim, Manoj Vadeentavida, Pierpaolo Lupo, Prashanth S. Holenarsipur, Praveesh Chandran, Vinodh Babu, Yuta Kuboyama
-
Patent number: 11626376Abstract: A semiconductor device of an embodiment includes a first chip having a memory cell array, and a second chip having a control circuit. The first chip includes a substrate, a pad, a first structural body, and a second structural body. The substrate is arranged on the side opposite to a joined face of the first chip joined to the second chip, and includes a first face, a second face, and an opening extending from the second face to the first face in a first region. The memory cell array is provided between the first face and the opposed joined face. The pad is provided in the opening. The first structural body is provided between the first face and the joined face, and is electrically connected to the pad. The second structural body is provided between the first face and the joined face in the first region.Type: GrantFiled: June 17, 2021Date of Patent: April 11, 2023Assignee: Kioxia CorporationInventor: Yuji Setta
-
Patent number: 11605595Abstract: Disclosed is an apparatus and methods for making same. The apparatus includes a first insulating layer, a first metal layer disposed on a surface of the first insulating layer, and a metallization structure embedded in the first insulating layer. The metallization structure occupies only a portion of a volume of the first insulating layer. The metallization structure has a line density greater than a line density of the first metal layer.Type: GrantFiled: August 14, 2020Date of Patent: March 14, 2023Assignee: QUALCOMM INCORPORATEDInventors: Aniket Patil, Hong Bok We, Kuiwon Kang
-
Patent number: 11600607Abstract: A semiconductor module may include a system board including a top surface and a bottom surface, a module substrate provided on the top surface of the system board, a system semiconductor package mounted on the module substrate, and first and second power management semiconductor packages mounted on the module substrate. The first and second power management semiconductor packages may be spaced apart from each other in a first direction, which is parallel to a top surface of the module substrate, with the system semiconductor package interposed therebetween.Type: GrantFiled: January 16, 2020Date of Patent: March 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventor: Heungkyu Kwon
-
Patent number: 11581292Abstract: A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.Type: GrantFiled: June 10, 2020Date of Patent: February 14, 2023Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Dan Azeroual, Liav Ben Artsi