Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device Patents (Class 438/107)
  • Patent number: 11521931
    Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: Jason M. Gamba, Nitin A. Deshpande, Mohit Bhatia, Omkar G. Karhade, Bai Nie, Gang Duan, Kristof Kuwawi Darmawikarta, Wei-Lun Jen
  • Patent number: 11521925
    Abstract: A semiconductor module, including a board that has first and second conductive plates located side by side on a first insulating plate, a first external connection terminal located on the first conductive plate, first and second semiconductor chips respectively disposed on the first and second conductive plates, and a printed-circuit board including a second insulating plate and first and second wiring boards located on a first principal plane of the second insulating plate. The first wiring board electrically connects an upper surface electrode of the first semiconductor chip and a relay area on the second conductive plate. The second wiring board is electrically connected to an upper surface electrode of the second semiconductor chip. The semiconductor module further includes a second external connection terminal electrically connected to an end portion of the second wiring board and formed on the second principal plane of the second insulating plate.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: December 6, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akira Hirao, Yoshinari Ikeda, Motohito Hori
  • Patent number: 11515241
    Abstract: A semiconductor device package includes a first dielectric layer, a conductive pad and an electrical contact. The first dielectric layer has a first surface and a second surface opposite to the first surface. The conductive pad is disposed within the first dielectric layer. The conductive pad includes a first conductive layer and a barrier. The first conductive layer is adjacent to the second surface of the first dielectric layer. The first conductive layer has a first surface facing the first surface of the first dielectric layer and a second surface opposite to the first surface. The second surface of the first conductive layer is exposed from the first dielectric layer. The barrier layer is disposed on the first surface of the first conductive layer. The electrical contact is disposed on the second surface of the first conductive layer of the conductive pad.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 29, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Teck-Chong Lee
  • Patent number: 11502055
    Abstract: Discussed is an assembly apparatus for assembling a semiconductor light emitting diode to a display panel, the assembly apparatus including an assembly module including at least one magnetic member and a magnetic member accommodator having at least one magnetic member accommodation hole, and a rotary module connected to the assembly module to rotate the assembly module along an orbit.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: November 15, 2022
    Assignee: LG ELECTRONICS INC.
    Inventors: Hyunwoo Cho, Bongchu Shim, Dohee Kim
  • Patent number: 11462487
    Abstract: A semiconductor package includes a frame, a semiconductor chip, a through via, a connection pad, a lower redistribution layer on the bottom surfaces of the frame and the semiconductor chip, a connection terminal on the lower redistribution layer, an encapsulant covering the top surfaces of the frame and the semiconductor chip, and an upper redistribution layer on the encapsulant. The lower redistribution layer includes a lower insulating layer, a lower redistribution pattern, and an under-bump metal (UBM). The upper redistribution layer includes an upper insulating layer, an upper redistribution pattern, an upper via, and an upper connection pad. The lower insulating layer includes an inner insulating pattern surrounding the side surface of the UBM and an outer insulating pattern surrounding the side surface of the inner insulating pattern. The cyclization rate of the inner insulating pattern is higher than the cyclization rate of the outer insulating pattern.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: October 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yuseon Heo
  • Patent number: 11456240
    Abstract: A semiconductor device and method of manufacture are presented in which a first semiconductor device and second semiconductor device are bonded to a first wafer and then singulated to form a first package and a second package. The first package and second package are then encapsulated with through interposer vias, and a redistribution structure is formed over the encapsulant. A separate package is bonded to the through interposer vias.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Tzuan-Horng Liu
  • Patent number: 11450535
    Abstract: A semiconductor package comprising a fan-out structure and a manufacturing method therefor are disclosed. A semiconductor package according to an embodiment of the present invention comprises: a wiring unit comprising an insulation layer and a wiring layer; a semiconductor chip mounted on the wiring unit and coupled to the wiring layer by flip-chip bonding; a filling member for filling a gap between the semiconductor chip and the wiring unit; and a film member for performing coating so as to cover one surface of each of the semiconductor chip, the filling member, and the wiring unit.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: September 20, 2022
    Assignee: NEPES CO., LTD.
    Inventors: Yong-Tae Kwon, Jun-Kyu Lee, Si Woo Lim, Dong-Hoon Oh, Jun-Sung Ma, Tae-Won Kim
  • Patent number: 11444051
    Abstract: A semiconductor device, and method of making the same, comprising a plurality of conductive studs formed over an active surface of a semiconductor die. The plurality of conductive studs may be disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs. An encapsulant may be disposed around the semiconductor die and the conductive studs. A portion of the conductive studs may be exposed from the encapsulant at a planar surface. A build-up interconnect structure comprising one or more layers may be disposed over and coupled to the planar surface, the conductive studs, and the conductive interconnect. A device may be coupled to the conductive interconnects of the device mount site.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: September 13, 2022
    Assignee: Deca Technologies USA, Inc.
    Inventors: Clifford Sandstrom, Benedict San Jose, Timothy L. Olson, Craig Bishop
  • Patent number: 11444067
    Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Chan H. Yoo
  • Patent number: 11437303
    Abstract: A microelectronic device has a substrate attached to a substrate pad on a first face of the substrate, and a component attached to the substrate on the first face. The substrate has a component placement guide on the first face. The substrate has a singulation guide on a second face of the substrate, located opposite from the first face. The microelectronic device is formed by attaching the component to a substrate sheet which contains the substrate. The substrate sheet with the component is mounted on a singulation film so that the component contacts the singulation film. The singulation guide on the second face of the substrate is located opposite from the singulation film. The substrate is singulated from the substrate sheet. The substrate with the component is attached to the substrate pad on the first face of the substrate, adjacent to the component.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: September 6, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chang-Yen Ko, J K Ho
  • Patent number: 11437348
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
  • Patent number: 11437302
    Abstract: Provided are a semiconductor module capable of easily connecting extraction pin with a wiring board and having reliable connections, and a method for manufacturing the same. A semiconductor module includes: a multilayer board having a semiconductor device mounted thereon, the multilayer board electrically connecting to the semiconductor device; an extraction pin electrically connecting to one of the semiconductor device and the multilayer board; and a wiring board bonded to the extraction pin for electrical connection. The extraction pin has a press-fit. The wiring board has a hole portion bonded with the press-fit of the extraction pin. The base materials of the press-fit of the extraction pin and the hole portion of the wiring board are copper (Cu). A bonded portion between the base materials of press-fit and the corresponding hole portion of the wiring board includes a CuSnNi alloy layer.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: September 6, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Kanai, Yuichiro Hinata
  • Patent number: 11439050
    Abstract: A mark recognition device is applied to a substrate including a marked region. The mark recognition device includes; an image collecting mechanism and a first light source. The first light source emits a light beam, the light beam includes a first light beam and a second light beam. The first light beam is irradiated to the marked region of the substrate and blocked by a mark of the marked region to generate a marked orthographic projection on the image collecting mechanism. The second light beam is transmitted to the image collecting mechanism to form transmitted light. The image collecting mechanism recognizes the mark according to the marked orthographic projection of the mark and the second light beam. Recognition accuracy of the mark is effectively improved in embodiments of the present application.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: September 6, 2022
    Assignee: KunShan Go-Visionox Opto-Electronics Co., Ltd.
    Inventors: Yateng Wang, Peilin Xiong, Dong Han
  • Patent number: 11424248
    Abstract: The invention involves a method of manufacturing a bonded semiconductor structure, comprising providing a support substrate which carries a transistor, and providing an interconnect region earned by the support substrate. The interconnect region includes a first multiple bypass bitline having an upper bypass interconnect and upper bypass via. The method includes providing a first conductive bonding layer carried by the interconnect region, wherein the first conductive bonding layer is connected to the upper bypass interconnect through the upper bypass via, and providing a vertical transistor carried by the first conductive bonding layer, the vertical transistor being in communication with the transistor through the interconnect region. The first multiple bypass bitline reduces the impedance experienced by the vertical transistor.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 23, 2022
    Assignee: BeSang Inc.
    Inventor: Sang-Yun Lee
  • Patent number: 11417620
    Abstract: A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Feng-Cheng Hsu
  • Patent number: 11404341
    Abstract: A package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The conductive structures include elliptical columns. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is over the active surface of the die and the encapsulant. The redistribution structure is electrically connected to the die and the conductive structures.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Patent number: 11404345
    Abstract: A semiconductor package is described. The semiconductor package includes a passive substrate and a first integrated passive device (IPD) in a first interlayer-dielectric (ILD) layer on the passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package also includes a thermal mitigation structure on inductive elements of the second IPD.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: August 2, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Lan, Jonghae Kim, Ranadeep Dutta
  • Patent number: 11393947
    Abstract: The present application provides a method of fabricating a light-emitting diode (LED) display panel, including the following steps: forming an LED substrate including a first substrate, an LED chip disposed on the first substrate, and a first electrode disposed on the LED chip; forming a driving substrate including a second substrate and a second electrode disposed on the second substrate; activating surfaces of the first electrode and the second electrode; aligning and pre-bonding the first electrode with the second electrode; and bonding the first electrode and the second electrode.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: July 19, 2022
    Inventor: Yang Sun
  • Patent number: 11373969
    Abstract: An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
  • Patent number: 11373938
    Abstract: A structure of a substrate is provided for application in an electric power module. The substrate includes element regions, on which a plurality of semiconductor elements are arranged, a center region that defines a space among the element regions, an input terminal region, on which an input terminal for applying an electric current to the substrate is disposed, and one or more slit insulation portions that are defined to face toward sides, respectively, of the element regions adjacent to the input terminal region, which are among the element regions. The slit insulation portions extend toward the center region in such a manner that an electric current applied through the input terminal region flows into the center region.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: June 28, 2022
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventor: Young Seok Kim
  • Patent number: 11367689
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: June 21, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
  • Patent number: 11355358
    Abstract: Embodiments of methods for processing a semiconductor substrate are described herein. In some embodiments, a method of processing a semiconductor substrate includes removing material from a backside of a reconstituted substrate having a plurality of dies to expose at least one die of the plurality of dies; etching the backside of the reconstituted substrate to remove material from the exposed at least one die; and depositing a first layer of material on the backside of the reconstituted substrate and the exposed at least one die.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: June 7, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Guan Huei See, Prayudi Lianto, Yu Gu
  • Patent number: 11348854
    Abstract: A semiconductor package structure includes a package substrate, an encapsulant, at least one passage and at least one semiconductor element. The encapsulant is disposed on the package substrate and has a peripheral surface, and includes a first encapsulant portion and a second encapsulant portion spaced apart from the first encapsulant portion. The at least one passage is defined by the first encapsulant portion and the second encapsulant portion, and the passage has at least one opening in the peripheral surface of the encapsulant. The at least one semiconductor element is disposed on the package substrate and exposed in the passage.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: May 31, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: I-Chia Lu, Mao-Sung Hsu
  • Patent number: 11335866
    Abstract: A display device includes a substrate, a thin film transistor disposed on the substrate, and a display element electrically connected to the thin film transistor. The substrate includes a first substrate layer, a second substrate layer disposed on the first substrate layer, a first barrier layer disposed between the first substrate layer and the second substrate layer, and a first ultraviolet light blocking layer disposed between the first substrate layer and the second substrate layer.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: May 17, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seong Min Wang, Beohmrock Choi, Yongho Yang
  • Patent number: 11322670
    Abstract: A pixel array substrate has a plurality of sub-pixel regions, wherein a pixel structure of an individual sub-pixel region includes a first signal line, a second signal line, a first contact pad, a second contact pad, a light-emitting diode, a first conductive structure, and a flux structure layer. The first contact pad and the second contact pad are respectively electrically connected with the first signal line and the second signal line. The light-emitting diode is disposed on the first contact pad. A portion of the first conductive structure is disposed between the first contact pad and a first electrode of the light-emitting diode. The flux structure layer partially surrounds the first conductive structure and the light-emitting diode. A top portion of the flux structure layer is higher than a top surface of the first electrode and is lower than a bottom surface of a light-emitting layer of the light-emitting diode.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 3, 2022
    Assignee: Au Optronics Corporation
    Inventors: Fang-Cheng Yu, Cheng-Yeh Tsai
  • Patent number: 11302671
    Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Zhijun Xu, Bin Liu, Yong She, Zhicheng Ding
  • Patent number: 11289400
    Abstract: Forming aluminum circuit layers forming an aluminum circuit layers on one surface of a ceramic substrate and forming copper circuit layers are included. The copper circuit layers are formed by laminating copper boards for the circuit layers on the respective aluminum circuit layers, arranging the laminate between a pair of support boards having a convex curved surface at least on one surface so as to face to each other, moving the support boards in a facing direction to press the laminate in a lamination direction, and heating in this pressing state so that the copper boards for the circuit layers are bonded on the aluminum circuit layers respectively by solid phase diffusion. In the step of forming the copper circuit layers, the support boards are arranged so that either one of the convex curved surface is in contact with the adjacent copper boards for the circuit layers in the laminate.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: March 29, 2022
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Ryohei Yumoto, Tomoya Oohiraki, Takeshi Kitahara, Yoshiyuki Nagatomo
  • Patent number: 11276646
    Abstract: An electronic component module includes a first substrate mounted on an upper surface of a second substrate such that at least a portion of a lower surface of the first substrate is exposed externally of the second substrate and electronic devices mounted on the first substrate and the second substrate, including at least one electronic device mounted on the upper surface of the second substrate.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: March 15, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong Yun Kim, Chang Ju Lee, Gye Won Lee, Hee Sun Oh, Hong Seok Lee
  • Patent number: 11264334
    Abstract: The present disclosure provides a package device and a method of manufacturing the same. The package device includes a supporting member, a main component, a sealant, and a conductive encapsulant. The supporting member includes a plurality of grounding contacts. The main component is mounted on the supporting member. The sealant covers the main component. The conductive encapsulant encases the sealant and the grounding contacts exposed through the sealant for EMI shielding.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: March 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Han-Ning Pei
  • Patent number: 11257933
    Abstract: A method for manufacturing a semiconductor device is provided. A first substrate and at least one second substrate are provided. A single crystal lamination structure is formed on the first substrate. The single crystal lamination structure includes at least one hetero-material layer and at least one channel material layer that are alternately laminated, each of the at least one hetero-material layer is bonded to an adjacent one of the at least one channel material layer at a side away from the first substrate, and each of the at least one channel material layer is formed from one of the at least one second substrate. At least one layer of nanowire or nanosheet is formed from the single crystal lamination structure. A gate dielectric layer and a gate which surround each of the at least one layer of nanowire or nanosheet is formed. A semiconductor device is also provided.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 22, 2022
    Assignee: Institute of Microelectronics, Chinese Academy
    Inventors: Huaxiang Yin, Qingzhu Zhang, Renren Xu
  • Patent number: 11251099
    Abstract: A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
  • Patent number: 11244894
    Abstract: A semiconductor package includes a semiconductor device having a through silicon via, a lower redistribution structure on the semiconductor device, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the through silicon via, a package connection terminal on the lower redistribution structure and electrically connected to the lower redistribution pattern, an upper redistribution structure on the semiconductor device and including an upper redistribution insulating layer and an upper redistribution pattern electrically connected to the through silicon via, a conductive via in contact with the upper redistribution pattern and on the upper redistribution insulating layer, a connection pad on the conductive via, and a passive element pattern on the upper redistribution structure and electrically connected to the conductive via.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: February 8, 2022
    Inventors: Seunghoon Yeon, Wonil Lee, Yonghoe Cho
  • Patent number: 11239199
    Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Klaus Reingruber, Christian Geissler, Sven Albers, Andreas Wolter, Marc Dittes, Richard Patten
  • Patent number: 11239217
    Abstract: A semiconductor package includes a first sub-package and a second sub-package. The first sub-package is stacked atop the second sub-package. Each of the first sub-package and the second sub-package includes at least two first semiconductor dies, a second semiconductor die, a plurality of molding pieces, a bond-pad layer, a plurality of redistribution layers (RDLs) and a plurality of bumps. The bumps of the first sub-package are attached to the bond-pad layer of the second sub-package.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: February 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 11235969
    Abstract: The integrated CMOS-MEMS device includes a CMOS structure, a cap structure, and a MEMS structure. The CMOS structure, fabricated on a first substrate, includes at least one conducting layer. The cap structure, including vias passing through the cap structure, has an isolation layer deposited on its first side and has a conductive routing layer deposited on its second side. The MEMS structure is deposited between the first substrate and the cap structure. The integrated CMOS-MEMS device also includes a conductive connector that passes through one of the vias and through an opening in the isolation layer on the cap structure. The conductive connector conductively connects a conductive path in the conductive routing layer on the cap structure with the at least one conducting layer of the CMOS structure.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Wen Cheng Kuo, Wei-Jhih Mao
  • Patent number: 11205598
    Abstract: A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Patent number: 11205738
    Abstract: A back plate for rapid and fluid-assisted assembly of micro light emitting elements thereon includes a substrate with a driving circuit, and blocking walls made to protrude from a top surface of the substrate. The top surface of the substrate defines grooves for accommodating and powering micro light emitting elements. Each of the blocking walls semi-surrounds one groove and defines a notch. The notches defined by each blocking wall all face a single direction and the blocking walls and notches impede and gather micro light emitting elements which are made to flow in a fluid suspension and render them much more likely to tumble into the groove. A method for fluid-assisted assembly is also disclosed.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: December 21, 2021
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: Shiue-Lung Chen, Cheng-Kuo Feng
  • Patent number: 11205600
    Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: December 21, 2021
    Assignee: Invensas Corporation
    Inventors: Hong Shen, Charles G. Woychik, Sitaram R. Arkalgud
  • Patent number: 11183462
    Abstract: A substrate having an electronic component embedded therein includes a core structure including a first insulating body and a plurality of core wiring layers disposed on or in the first insulating body, and having a cavity penetrating at least a portion of the first insulating body in a thickness direction of the substrate and including a stopper layer as a bottom surface of the cavity, and an electronic component disposed in the cavity and attached to the stopper layer, and a surface of the stopper layer connected to the electronic component has a composite including at least two among a metal material, an inorganic particle, a filler, and an insulating resin.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: November 23, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Mi Sun Hwang, Dae Jung Byun, Chang Hwa Park, Sang Ho Jeong, Jun Hyeong Jang, Ki Ho Na, Je Sang Park, Yong Duk Lee, Yoo Rim Cha, Yeo Il Park
  • Patent number: 11177197
    Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 16, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan Almeria Noquil, Satyendra Singh Chauhan, Lance Cole Wright, Osvaldo Jorge Lopez
  • Patent number: 11173478
    Abstract: The disclosure relates to a photocatalytic structure. The photocatalytic structure includes a carbon nanotube structure, a photocatalytic active layer coated on the carbon nanotube structure, and a metal layer including a plurality of nanoparticles located on the surface of the photocatalytic active layer. The carbon nanotube structure comprises a plurality of intersected carbon nanotubes and defines a plurality of openings, and the photocatalytic active layer is coated on the surface of the plurality of carbon nanotubes. The metal layer includes a plurality of nanoparticles located on the surface of the photocatalytic active layer.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: November 16, 2021
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ying-Cheng Wang, Yuan-Hao Jin, Xiao-Yang Xiao, Tian-Fu Zhang, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 11177139
    Abstract: The electronic card with printed circuit (1) comprises at least one antenna with slots (AT) including a cavity (15) and a metal conductive layer (17) covering the cavity and having a plurality of slots (S17). The slots form openings in the metal conductive layer. In accordance with the invention, the cavity is formed, by removal of material, in the thickness of the printed circuit. The cavity also comprises a metallisation layer (16) on the walls and the metal conductive layer is formed in a plate attached on the electronic card with printed circuit and closes the cavity.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: November 16, 2021
    Assignee: INSTITUT VEDECOM
    Inventor: Friedbald Kiel
  • Patent number: 11152534
    Abstract: The present invention relates to a transfer head and a method of manufacturing a micro LED display using the same. In particular, the present invention relates to a transfer head and a method of manufacturing a micro LED display using the same, the transfer head mounting normal micro LEDs on a display substrate without performing a complicated process of sorting out defective micro LEDs from the micro LEDs mounted on the display substrate and replacing the defective micro LEDs with normal micro LEDs.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: October 19, 2021
    Assignee: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo Ahn, Seung Ho Park, Tae Hwan Song
  • Patent number: 11133274
    Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
  • Patent number: 11119962
    Abstract: An apparatus includes: a semiconductor die including a first I/O (input/output) pad, a second I/O pad, a switch, and an internal processor, wherein the switch is configured to short the first I/O pad to the second I/O pad when a control signal is asserted; and a semiconductor package including a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a first port configured to electrically connect to a high-speed pin of a multi-mode connector, a second port configured to electrically connect to an external processor, a first routing path configured to electrically connect the first port to the first bond pad, and a second routing path configured to electrically connect the second port to the second bond pad.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 14, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chi-Kung Kuan, Chia-Liang (Leon) Lin
  • Patent number: 11096269
    Abstract: A printed circuit board assembly includes a first printed circuit board, a second printed circuit board disposed on the first printed circuit board and including an antenna pattern, a third printed circuit board disposed on the first printed circuit board, one or more first electronic components disposed between the first and the second printed circuit board and electrically connected to at least one of the first and the second printed circuit board, one or more second electronic components disposed between the first and the third printed circuit board, and electrically connected to at least one of the first and the third printed circuit board, a first interposer substrate electrically connecting the first printed circuit board and the second printed circuit board to each other, and a second interposer substrate electrically connecting the first printed circuit board and the third printed circuit board to each other.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Won Wook So, Doo Il Kim, Young Sik Hur
  • Patent number: 11088046
    Abstract: In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 10, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Maria Cristina Estacio, Elsie Agdon Cabahug, Romel N. Manatad
  • Patent number: 11069735
    Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 20, 2021
    Assignee: SONY CORPORATION
    Inventors: Kengo Kotoo, Kaoru Koike
  • Patent number: 11037877
    Abstract: A package structure includes a first die, a second die, a bridge, an encapsulant and a redistribution layer (RDL) structure. The bridge is arranged side by side with the first die and the second die. The encapsulant laterally encapsulates the first die, the second die and the bridge. The RDL structure is disposed on the first die, the second die, the bridge and the encapsulant. The first die and the second die are electrically connected to each other through the bridge and the RDL structure.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Hung-Jui Kuo, Ming-Tan Lee
  • Patent number: 11031372
    Abstract: A semiconductor device is disclosed including a stack of semiconductor die on a substrate, wherein a semiconductor die in the stack is wire bonded to the substrate using dummy wire bonds. Each dummy wire bond has a stiffness so that together, the dummy wire bonds effectively pull and/or hold down the die stack against the substrate.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 8, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Han-Shiao Chen, Chih-Chin Liao, Chin-Tien Chiu