Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device Patents (Class 438/107)
  • Patent number: 11133274
    Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
  • Patent number: 11119962
    Abstract: An apparatus includes: a semiconductor die including a first I/O (input/output) pad, a second I/O pad, a switch, and an internal processor, wherein the switch is configured to short the first I/O pad to the second I/O pad when a control signal is asserted; and a semiconductor package including a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a first port configured to electrically connect to a high-speed pin of a multi-mode connector, a second port configured to electrically connect to an external processor, a first routing path configured to electrically connect the first port to the first bond pad, and a second routing path configured to electrically connect the second port to the second bond pad.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 14, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chi-Kung Kuan, Chia-Liang (Leon) Lin
  • Patent number: 11096269
    Abstract: A printed circuit board assembly includes a first printed circuit board, a second printed circuit board disposed on the first printed circuit board and including an antenna pattern, a third printed circuit board disposed on the first printed circuit board, one or more first electronic components disposed between the first and the second printed circuit board and electrically connected to at least one of the first and the second printed circuit board, one or more second electronic components disposed between the first and the third printed circuit board, and electrically connected to at least one of the first and the third printed circuit board, a first interposer substrate electrically connecting the first printed circuit board and the second printed circuit board to each other, and a second interposer substrate electrically connecting the first printed circuit board and the third printed circuit board to each other.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Won Wook So, Doo Il Kim, Young Sik Hur
  • Patent number: 11088046
    Abstract: In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 10, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Maria Cristina Estacio, Elsie Agdon Cabahug, Romel N. Manatad
  • Patent number: 11069735
    Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 20, 2021
    Assignee: SONY CORPORATION
    Inventors: Kengo Kotoo, Kaoru Koike
  • Patent number: 11037877
    Abstract: A package structure includes a first die, a second die, a bridge, an encapsulant and a redistribution layer (RDL) structure. The bridge is arranged side by side with the first die and the second die. The encapsulant laterally encapsulates the first die, the second die and the bridge. The RDL structure is disposed on the first die, the second die, the bridge and the encapsulant. The first die and the second die are electrically connected to each other through the bridge and the RDL structure.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Hung-Jui Kuo, Ming-Tan Lee
  • Patent number: 11031372
    Abstract: A semiconductor device is disclosed including a stack of semiconductor die on a substrate, wherein a semiconductor die in the stack is wire bonded to the substrate using dummy wire bonds. Each dummy wire bond has a stiffness so that together, the dummy wire bonds effectively pull and/or hold down the die stack against the substrate.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 8, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Han-Shiao Chen, Chih-Chin Liao, Chin-Tien Chiu
  • Patent number: 11024581
    Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first dielectric layer, a first conductive pattern and a barrier layer. The first conductive pattern is disposed in a second dielectric layer over the first dielectric layer. The barrier layer is disposed at an interface between the first conductive pattern and the second dielectric layer and an interface between the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Wen Wu, Hung-Jui Kuo, Ming-Che Ho
  • Patent number: 11024561
    Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: June 1, 2021
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Il Kwon Shim, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Yu Gu
  • Patent number: 11001078
    Abstract: An apparatus including a dot matrix transfer head that includes an impact wire housing. A plurality of impact wires are disposed within the impact wire housing and extend out of the impact wire housing. A splaying element attached to a bottom surface of the impact wire housing. The plurality of impact wires extend into and through the splaying element. A guide head attached to a bottom surface of the splaying element. The guide head includes multiple holes that arrange the plurality of impact wires in a matrix configuration. The splaying element is designed to direct the plurality of impact wires toward the multiple holes in the guide head.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 11, 2021
    Assignee: Rohinni, LLC
    Inventor: Andrew Huska
  • Patent number: 10999923
    Abstract: Described are various configurations of high-speed via structures. Various embodiments can reduce or entirely eliminate insertion loss in high-speed signal processing environments by using impedance compensation structures that decrease a mismatch in components of a circuit. An impedance compensation structure can include a metallic structure placed near a via to lower an impedance difference between the via and a conductive pathway connected to the via.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: May 4, 2021
    Assignee: Juniper Networks, Inc.
    Inventor: Christopher Paul Wyland
  • Patent number: 10998316
    Abstract: A method for fabricating a vertical memory device includes: forming a memory cell array that includes a vertical thyristor and a word line over a first substrate; forming a peripheral circuit unit in a second substrate; bonding the memory cell array with the peripheral circuit unit; removing the first substrate to expose one side of the vertical thyristor; and forming a bit line that is coupled to the one side of the vertical thyristor and the peripheral circuit unit.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventor: Nam-Jae Lee
  • Patent number: 10985146
    Abstract: A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 20, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Bora Baloglu, Ron Huemoeller, Curtis Zwenger
  • Patent number: 10985208
    Abstract: There is provided a display device. The display device includes a plurality of semiconductor elements disposed on a substrate; a plurality of LEDs disposed on the plurality of semiconductor elements and electrically connected to the plurality of semiconductor elements, respectively; and a plurality of reflectors disposed above the semiconductor elements and each located between every two of the LEDs. The plurality of LEDs may include a plurality of light-emitting layers disposed on the plurality of semiconductor elements, and a common electrode disposed on the plurality of light-emitting layers. The reflectors are disposed between the LEDs, so that light emitted from LEDs does not travel toward the side portions of the LEDs but toward the above of the substrate, thereby improving the light extraction efficiency and suppressing color mixture.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 20, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Joonyeong Park, Taeil Jung, Il-Soo Kim
  • Patent number: 10976872
    Abstract: To provide a novel display panel that is highly convenient or reliable. To provide a novel input and output device that is highly convenient or reliable. To provide a novel data processing device that is highly convenient or reliable. To provide a method for manufacturing a novel display panel that is highly convenient or reliable. The display panel includes a pixel, a third conductive film electrically connected to the pixel, an insulating film including an opening portion overlapping with the third conductive film, and an electrode including a first region in contact with the third conductive film and a second region functioning as a contact point.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: April 13, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Jinbo, Shingo Eguchi, Hisao Ikeda, Tetsuji Ishitani, Taisuke Kamada
  • Patent number: 10978382
    Abstract: In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hui Lai, Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10950550
    Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Jianyong Xie, Kemal Aygun
  • Patent number: 10950557
    Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: March 16, 2021
    Assignee: Powertech Technology Inc.
    Inventors: Li-Chih Fang, Ji-Cheng Lin, Che-Min Chu, Chun-Te Lin, Chien-Wen Huang
  • Patent number: 10944023
    Abstract: A micro-LED transfer method and manufacturing method. The micro-LED (303) transfer method comprises: bringing pickup units (305) of a transfer head in contact with micro-LEDs (303) on a carrier substrate (301), wherein the pickup units (305) are able to apply current to the micro-LEDs (303); applying current to the micro-LEDs (303) via the pickup units (305) to heat up bonding layers (302) between the micro-LEDs (303) and the carrier substrate (301) to be melted; picking up the micro-LEDs (303) from the carrier substrate (301) with the transfer head; bonding the micro-LEDs (303) onto a receiving substrate (307); and removing the transfer head from the micro-LEDs.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: March 9, 2021
    Assignee: GOERTEK. INC
    Inventor: Quanbo Zou
  • Patent number: 10923449
    Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising five different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: February 16, 2021
    Assignee: Compass Technology Company Limited
    Inventors: Kelvin Po Leung Pun, Chee Wah Cheung
  • Patent number: 10910354
    Abstract: A semiconductor device die transfer apparatus includes a first frame to hold a wafer tape having a plurality of semiconductor device die disposed on a side of the wafer tape and a second frame to secure a product substrate having a circuit trace thereon. The second frame is configured to secure the product substrate such that the circuit trace is disposed facing the plurality of semiconductor device die on the wafer tape. Additionally, a rotary transfer collet is disposed between the wafer tape and the product substrate. The rotary transfer collet has a rotational axis allowing rotation from a first position facing the wafer tape to pick a die of the plurality of semiconductor device die to a second position facing the circuit trace on the product substrate to release the die, thereby applying the die directly on the product substrate during a transfer operation.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: February 2, 2021
    Assignee: Rohinni, LLC
    Inventors: Cody Peterson, Clinton Adams, Sean Kupcow, Andrew Huska
  • Patent number: 10886238
    Abstract: A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 10880991
    Abstract: Embodiments described herein provide an electronic device having an integrated circuit disposed in a surface mount package. The surface mount integrated circuit package comprises a first pin and a second pin of the integrated circuit configured to couple the integrated circuit to a first terminal and a second terminal disposed on a circuit board. The first pin and second pin define a first connector and a second connector of a differential connector pair in the surface mount integrated circuit package for transferring differential signals from the integrated circuit to the circuit board. The surface mount integrated circuit package comprises an isolation stud disposed between the first pin and the second pin. The isolation stud is disconnected from the integrated circuit and configured to enlarge a gap between the first pin and the second pin relative to respective gaps of other pins coupling the electronic device to the circuit board.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: December 29, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Thomas T. Ngo, Xinlei Ding, Dance Wu, Chengchih Shih, Zhiqiang Li
  • Patent number: 10879183
    Abstract: A device includes a redistribution structure, a semiconductor device on the redistribution structure, a top package over the semiconductor device, the top package including a second semiconductor device, a molding compound interposed between the redistribution structure and the top package, a set of through vias between and electrically connecting the top package to the redistribution structure, and an interconnect structure disposed within the molding compound and electrically connecting the top package to the redistribution structure, the interconnect structure including a substrate and a passive device formed in the substrate, wherein the interconnect structure is free of active devices.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu
  • Patent number: 10872865
    Abstract: A package includes a device die, a molding material molding the device die therein, and a through-via penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. A metal ring is close to edges of the package, wherein the metal ring is coplanar with the redistribution line.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
  • Patent number: 10867960
    Abstract: A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The device package also includes an interconnect structure over the die. The interconnect structure includes a redistribution layer extending onto the molding compound and conformal to the non-planar surface of the molding compound. The device package further includes a first connector disposed over the die and bonded to the interconnect structure.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Meng-Tse Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10854665
    Abstract: A semiconductor wafer has a plurality of non-rectangular semiconductor die with an image sensor region. The non-rectangular semiconductor die has a circular, elliptical, and shape with non-linear side edges form factor. The semiconductor wafer is singulated with plasma etching to separate the non-rectangular semiconductor die. A curved surface is formed in the image sensor region of the non-rectangular semiconductor die. The non-rectangular form factor effectively removes a portion of the base substrate material in a peripheral region of the semiconductor die to reduce stress concentration areas and neutralize buckling in the curved surface of the image sensor region. A plurality of openings or perforations can be formed in a peripheral region of a rectangular or non-rectangular semiconductor die to reduce stress concentration areas and neutralize buckling. A second semiconductor die can be formed in an area of the semiconductor wafer between the non-rectangular semiconductor die.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: December 1, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Ulrich Boettiger, Marc Allen Sulfridge, Andrew Eugene Perkins
  • Patent number: 10847301
    Abstract: An electronic component includes an element body, a conductor provided on the element body, a plating layer provided on the conductor, and a glass layer provided on the conductor along an outer edge of the plating layer.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK CORPORATION
    Inventors: Shunji Aoki, Yuya Ishima, Masaki Takahashi, Yuki Okazaki, Takeshi Sasaki
  • Patent number: 10797009
    Abstract: A method for transferring a micro device is provided. The method includes: forming a liquid layer on the micro device attached on a transfer plate; placing the micro device over a receiving substrate such that the liquid layer is between the micro device and a contact pad of the receiving substrate and contacts the contact pad; and evaporating the liquid layer such that the micro device is bound to and in contact with the contact pad.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: October 6, 2020
    Assignee: MIKRO MESA TECHNOLOGY CO., LTD.
    Inventor: Li-Yi Chen
  • Patent number: 10784244
    Abstract: A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: September 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Gil Han, Seung-Lo Lee, Yong-Je Lee, Sung-Il Cho
  • Patent number: 10784229
    Abstract: Wafer level package structures and packaging methods are provided. An exemplary method includes providing a device wafer having a first front surface and a first back surface opposing the first front surface, wherein at least one first chip is integrated in the first front surface; forming a first oxide layer on the first front surface of the device wafer; providing at least one second chip having a to-be-bonded surface; forming a second oxide layer on the to-be-bonded surface of each second chip; providing a carrier wafer; temporally bonding a surface of the second chip opposing the second oxide layer to the carrier wafer; forming an encapsulation layer on the carrier wafer between adjacent second chips of the at least one second; and bonding the device wafer and the second chip by bonding the first oxide layer with the second oxide layer by a low-temperature fusion bonding process.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 22, 2020
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Hailong Luo, Clifford Ian Drowley
  • Patent number: 10770394
    Abstract: The present application provides a fan-out semiconductor packaging structure with an antenna module and a method making the same. The fan-out semiconductor packaging structure with the antenna module comprises: a semiconductor chip; a plastic packaging material layer enclosing a periphery of the semiconductor chip; a filling structure disposed in the plastic packaging material layer and disposed on the periphery of the semiconductor chip, a loss caused by the filling structure to an antenna signal is smaller than a loss caused by the plastic packaging material layer to an antenna signal; an antenna module disposed on the first surface of the plastic packaging material layer, an orthographic projection of the antenna module on the filling structure is disposed on the filling structure; a redistribution layer disposed on the second surface of the plastic packaging material layer; and a solder bump disposed on a surface of the redistribution layer.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 8, 2020
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yenheng Chen, Chengtar Wu, Jangshen Lin, Chengchung Lin
  • Patent number: 10766769
    Abstract: A semiconductor element includes a processed substrate arrangement including a processed semiconductor substrate and a metallization layer arrangement on a main surface of the processed semiconductor substrate. The semiconductor element further includes a passivation layer arranged at an outer border of the processed substrate arrangement.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: September 8, 2020
    Assignee: Infineon Technologies AG
    Inventors: Christian Bretthauer, Dirk Meinhold
  • Patent number: 10770614
    Abstract: A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device. A light emitting diode is formed on the textured surface of the photovoltaic device.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 10756052
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Grant
    Filed: July 28, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Patent number: 10734367
    Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: August 4, 2020
    Assignee: Sansumg Electronics Co., Ltd.
    Inventors: Seung-Kwan Ryu, Yonghwan Kwon, Yun Seok Choi, Chajea Jo, Taeje Cho
  • Patent number: 10720401
    Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
  • Patent number: 10720339
    Abstract: A fan-out wafer-level packaging method and the package produced thereof are provided in the present application.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 21, 2020
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Masaya Kawano, Ka Fai Chang
  • Patent number: 10720462
    Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: July 21, 2020
    Assignee: Sony Corporation
    Inventors: Kengo Kotoo, Kaoru Koike
  • Patent number: 10692796
    Abstract: A semiconductor package (1, 1?, 1?), the package (1, 1?, 1?) comprising a first substrate (2) comprising at a front cavity side (5?) a plurality of cavities (6, 6?), each of the cavities (6, 6?) having a bottom wall (7) and side walls (8), and having a conductive path (10) forming an electric contact surface (9) located at the inner side of the bottom wall (7) of the cavity (6, 6?), a plurality of semiconductor elements (16, 7), each of the semiconductor elements (16, 17) comprising a first electric contact surface (9) on a first side (26) and a second electric contact surface (9) on a second side (28) opposite to the first side (26), wherein at least one of the semiconductor elements (16, 17) is placed within a corresponding cavity (6, 6?) at the front cavity side (5?) of the first substrate (2), wherein the first electric contact (27) of the semiconductor element (16, 17) and the electric contact surface (9) at the inner side of the bottom wall (7) of the corresponding cavity (6, 6?) are electrically conduc
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 23, 2020
    Assignee: Technische Hochschule Ingolstadt
    Inventors: Gordon Elger, Johannes Pforr
  • Patent number: 10685896
    Abstract: An integrated circuit package including an integrated circuit component, a patterned dielectric liner, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component includes an active surface and conductive vias distributed on the active surface. The patterned dielectric liner conformally covers the active surface of the integrated circuit component and sidewalls of the conductive vias. The insulating encapsulation encapsulates sidewalls of the integrated circuit component and covers the patterned dielectric liner. The insulating encapsulation includes a planar top surface. The planar top surface of the insulating encapsulation is substantially coplanar with top surfaces of the conductive vias. The insulating encapsulation and the conductive vias are spaced apart by the patterned dielectric liner.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zi-Jheng Liu, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 10685945
    Abstract: A luminous panel includes a substrate having electric connections and an array of microchips secured to the substrate and connected to the electric connections in order to be driven. Each microchip includes control circuit based on transistors formed in a silicon volume, the circuit being connected to the substrate connections, and a micro-LED secured to the control circuit and connected thereto in order to be controlled.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 16, 2020
    Assignee: Commissariat a l'Energie Atomique et aux Energies
    Inventors: Ivan-Christophe Robin, Bruno Mourey
  • Patent number: 10672821
    Abstract: A sensor device includes a first wafer structure and a second wafer structure bonded to the first wafer structure. The first wafer structure includes a first substrate, an integrated circuit layer integrated with the first substrate, and a three-dimensional (3D) NAND memory cell array integrated with the integrate circuit layer. The integrated circuit layer and the 3D NAND memory cell array are located at the same side of the first substrate. The second wafer structure includes a second substrate and a sensing module of a sensor integrated with the second substrate. A manufacturing method of the sensor device includes bonding the second wafer structure to the first wafer structure. A side of the first wafer structure where the 3D NAND memory cell array is located is bonded to a side of the second wafer structure where the sensing module is located.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 2, 2020
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Liang Shen, Wenjing Cheng
  • Patent number: 10672741
    Abstract: In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM chip, and a first via on the first side of the TEM chip and adjacent to the first die, the first via being electrically coupled to the TEM chip. The device also includes a first molding layer surrounding the TEM chip, the first die and the first via, where an upper surface of the first die and an upper surface of the first via are level with an upper surface of the first molding layer. The device further includes a first redistribution layer over the upper surface of the first molding layer and electrically coupled to the first via and the first die.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Hsien Huang, Yueh-Ting Lin, Wei-Yu Chen, An-Jhih Su
  • Patent number: 10665571
    Abstract: A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kunsil Lee
  • Patent number: 10658554
    Abstract: An LED lamp is formed from a die substrate wherein the substrate has formed thereon a semiconductor material, an electrode for the application of a bias across the semiconductor material for causing light to be emitted therefrom, and an adhesive that bonds the die substrate to a support substrate, wherein the adhesive is a polymerized siloxane polymer having a thermal conductivity of greater than 0.1 watts per meter kelvin (W/(m·K)) wherein the adhesive is not light absorbing, wherein the siloxane polymer has silicon and oxygen in the polymer backbone, as well as aryl or alky groups bound thereto, and wherein the adhesive further comprises particles having an average particle size of less than 100 microns.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: May 19, 2020
    Assignee: Inkron Oy
    Inventors: Juha Rantala, Jarkko Heikkinen, Janne Kylmä
  • Patent number: 10651131
    Abstract: A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 10641911
    Abstract: Disclosed herein is a method for making an apparatus suitable for detecting X-ray, the method comprising: bonding a plurality of chips to a substrate; wherein the substrate comprises an X-ray absorption layer comprising a first plurality of electrical contacts; wherein each of the plurality of chips comprises an electronic layer comprising a second plurality of electrical contacts and an electronic system configured to process or interpret signals generated by X-ray photons incident on the X-ray absorption layer; aligning the first plurality of electrical contacts to the second plurality of electrical contacts; mounting the chips to the substrate such that the first plurality of electrical contacts are electrically connected to the second plurality of electrical contacts; wherein the second plurality of electrical contacts are configured to feed the signals to the electronic system.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: May 5, 2020
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 10632727
    Abstract: A method of transferring micro devices is provided. A carrier substrate including a buffer layer and a plurality of micro devices is provided. The buffer layer is located between the carrier substrate and the micro devices. The micro devices are separated from one another and positioned on the carrier substrate through the buffer layer. A receiving substrate contacts the micro devices disposed on the carrier substrate. A temperature of at least one of the carrier substrate and the receiving substrate is changed after the micro devices contact the receiving substrate. At least a portion of the micro devices are transferred from the carrier substrate onto the receiving substrate after changing the temperature of at least one of the carrier substrate and the receiving substrate.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 28, 2020
    Assignee: PlayNitride Inc.
    Inventors: Yun-Li Li, Tzu-Yang Lin, Yu-Hung Lai, Pei-Hsin Chen
  • Patent number: 10622346
    Abstract: A method for manufacturing an electronic device includes: providing a semiconductor carrier including first and second vertically integrated electronic structures laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier and electrically connecting the first and second vertically integrated electronic structures with each other; mounting the semiconductor carrier on a support carrier with the first side of the semiconductor carrier facing the support carrier; thinning the semiconductor carrier from a second side opposite the first side; and removing material of the semiconductor carrier in a separation region between the first and second vertically integrated electronic structures to separate a first semiconductor region of the first vertically integrated electronic structure from a second semiconductor region of the second vertically integrated electronic structure with the first and second vertically integrated electronic structures remain
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 14, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Andre Schmenn, Stefan Pompl, Damian Sojka, Katharina Umminger