Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device Patents (Class 438/107)
  • Patent number: 10797009
    Abstract: A method for transferring a micro device is provided. The method includes: forming a liquid layer on the micro device attached on a transfer plate; placing the micro device over a receiving substrate such that the liquid layer is between the micro device and a contact pad of the receiving substrate and contacts the contact pad; and evaporating the liquid layer such that the micro device is bound to and in contact with the contact pad.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: October 6, 2020
    Assignee: MIKRO MESA TECHNOLOGY CO., LTD.
    Inventor: Li-Yi Chen
  • Patent number: 10784244
    Abstract: A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: September 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Gil Han, Seung-Lo Lee, Yong-Je Lee, Sung-Il Cho
  • Patent number: 10784229
    Abstract: Wafer level package structures and packaging methods are provided. An exemplary method includes providing a device wafer having a first front surface and a first back surface opposing the first front surface, wherein at least one first chip is integrated in the first front surface; forming a first oxide layer on the first front surface of the device wafer; providing at least one second chip having a to-be-bonded surface; forming a second oxide layer on the to-be-bonded surface of each second chip; providing a carrier wafer; temporally bonding a surface of the second chip opposing the second oxide layer to the carrier wafer; forming an encapsulation layer on the carrier wafer between adjacent second chips of the at least one second; and bonding the device wafer and the second chip by bonding the first oxide layer with the second oxide layer by a low-temperature fusion bonding process.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 22, 2020
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Hailong Luo, Clifford Ian Drowley
  • Patent number: 10770614
    Abstract: A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device. A light emitting diode is formed on the textured surface of the photovoltaic device.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 10770394
    Abstract: The present application provides a fan-out semiconductor packaging structure with an antenna module and a method making the same. The fan-out semiconductor packaging structure with the antenna module comprises: a semiconductor chip; a plastic packaging material layer enclosing a periphery of the semiconductor chip; a filling structure disposed in the plastic packaging material layer and disposed on the periphery of the semiconductor chip, a loss caused by the filling structure to an antenna signal is smaller than a loss caused by the plastic packaging material layer to an antenna signal; an antenna module disposed on the first surface of the plastic packaging material layer, an orthographic projection of the antenna module on the filling structure is disposed on the filling structure; a redistribution layer disposed on the second surface of the plastic packaging material layer; and a solder bump disposed on a surface of the redistribution layer.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 8, 2020
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yenheng Chen, Chengtar Wu, Jangshen Lin, Chengchung Lin
  • Patent number: 10766769
    Abstract: A semiconductor element includes a processed substrate arrangement including a processed semiconductor substrate and a metallization layer arrangement on a main surface of the processed semiconductor substrate. The semiconductor element further includes a passivation layer arranged at an outer border of the processed substrate arrangement.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: September 8, 2020
    Assignee: Infineon Technologies AG
    Inventors: Christian Bretthauer, Dirk Meinhold
  • Patent number: 10756052
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Grant
    Filed: July 28, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Patent number: 10734367
    Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: August 4, 2020
    Assignee: Sansumg Electronics Co., Ltd.
    Inventors: Seung-Kwan Ryu, Yonghwan Kwon, Yun Seok Choi, Chajea Jo, Taeje Cho
  • Patent number: 10720401
    Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
  • Patent number: 10720339
    Abstract: A fan-out wafer-level packaging method and the package produced thereof are provided in the present application.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 21, 2020
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Masaya Kawano, Ka Fai Chang
  • Patent number: 10720462
    Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: July 21, 2020
    Assignee: Sony Corporation
    Inventors: Kengo Kotoo, Kaoru Koike
  • Patent number: 10692796
    Abstract: A semiconductor package (1, 1?, 1?), the package (1, 1?, 1?) comprising a first substrate (2) comprising at a front cavity side (5?) a plurality of cavities (6, 6?), each of the cavities (6, 6?) having a bottom wall (7) and side walls (8), and having a conductive path (10) forming an electric contact surface (9) located at the inner side of the bottom wall (7) of the cavity (6, 6?), a plurality of semiconductor elements (16, 7), each of the semiconductor elements (16, 17) comprising a first electric contact surface (9) on a first side (26) and a second electric contact surface (9) on a second side (28) opposite to the first side (26), wherein at least one of the semiconductor elements (16, 17) is placed within a corresponding cavity (6, 6?) at the front cavity side (5?) of the first substrate (2), wherein the first electric contact (27) of the semiconductor element (16, 17) and the electric contact surface (9) at the inner side of the bottom wall (7) of the corresponding cavity (6, 6?) are electrically conduc
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 23, 2020
    Assignee: Technische Hochschule Ingolstadt
    Inventors: Gordon Elger, Johannes Pforr
  • Patent number: 10685896
    Abstract: An integrated circuit package including an integrated circuit component, a patterned dielectric liner, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component includes an active surface and conductive vias distributed on the active surface. The patterned dielectric liner conformally covers the active surface of the integrated circuit component and sidewalls of the conductive vias. The insulating encapsulation encapsulates sidewalls of the integrated circuit component and covers the patterned dielectric liner. The insulating encapsulation includes a planar top surface. The planar top surface of the insulating encapsulation is substantially coplanar with top surfaces of the conductive vias. The insulating encapsulation and the conductive vias are spaced apart by the patterned dielectric liner.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zi-Jheng Liu, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 10685945
    Abstract: A luminous panel includes a substrate having electric connections and an array of microchips secured to the substrate and connected to the electric connections in order to be driven. Each microchip includes control circuit based on transistors formed in a silicon volume, the circuit being connected to the substrate connections, and a micro-LED secured to the control circuit and connected thereto in order to be controlled.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 16, 2020
    Assignee: Commissariat a l'Energie Atomique et aux Energies
    Inventors: Ivan-Christophe Robin, Bruno Mourey
  • Patent number: 10672741
    Abstract: In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM chip, and a first via on the first side of the TEM chip and adjacent to the first die, the first via being electrically coupled to the TEM chip. The device also includes a first molding layer surrounding the TEM chip, the first die and the first via, where an upper surface of the first die and an upper surface of the first via are level with an upper surface of the first molding layer. The device further includes a first redistribution layer over the upper surface of the first molding layer and electrically coupled to the first via and the first die.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Hsien Huang, Yueh-Ting Lin, Wei-Yu Chen, An-Jhih Su
  • Patent number: 10672821
    Abstract: A sensor device includes a first wafer structure and a second wafer structure bonded to the first wafer structure. The first wafer structure includes a first substrate, an integrated circuit layer integrated with the first substrate, and a three-dimensional (3D) NAND memory cell array integrated with the integrate circuit layer. The integrated circuit layer and the 3D NAND memory cell array are located at the same side of the first substrate. The second wafer structure includes a second substrate and a sensing module of a sensor integrated with the second substrate. A manufacturing method of the sensor device includes bonding the second wafer structure to the first wafer structure. A side of the first wafer structure where the 3D NAND memory cell array is located is bonded to a side of the second wafer structure where the sensing module is located.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 2, 2020
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Liang Shen, Wenjing Cheng
  • Patent number: 10665571
    Abstract: A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kunsil Lee
  • Patent number: 10658554
    Abstract: An LED lamp is formed from a die substrate wherein the substrate has formed thereon a semiconductor material, an electrode for the application of a bias across the semiconductor material for causing light to be emitted therefrom, and an adhesive that bonds the die substrate to a support substrate, wherein the adhesive is a polymerized siloxane polymer having a thermal conductivity of greater than 0.1 watts per meter kelvin (W/(m·K)) wherein the adhesive is not light absorbing, wherein the siloxane polymer has silicon and oxygen in the polymer backbone, as well as aryl or alky groups bound thereto, and wherein the adhesive further comprises particles having an average particle size of less than 100 microns.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: May 19, 2020
    Assignee: Inkron Oy
    Inventors: Juha Rantala, Jarkko Heikkinen, Janne Kylmä
  • Patent number: 10651131
    Abstract: A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 10641911
    Abstract: Disclosed herein is a method for making an apparatus suitable for detecting X-ray, the method comprising: bonding a plurality of chips to a substrate; wherein the substrate comprises an X-ray absorption layer comprising a first plurality of electrical contacts; wherein each of the plurality of chips comprises an electronic layer comprising a second plurality of electrical contacts and an electronic system configured to process or interpret signals generated by X-ray photons incident on the X-ray absorption layer; aligning the first plurality of electrical contacts to the second plurality of electrical contacts; mounting the chips to the substrate such that the first plurality of electrical contacts are electrically connected to the second plurality of electrical contacts; wherein the second plurality of electrical contacts are configured to feed the signals to the electronic system.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: May 5, 2020
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 10632727
    Abstract: A method of transferring micro devices is provided. A carrier substrate including a buffer layer and a plurality of micro devices is provided. The buffer layer is located between the carrier substrate and the micro devices. The micro devices are separated from one another and positioned on the carrier substrate through the buffer layer. A receiving substrate contacts the micro devices disposed on the carrier substrate. A temperature of at least one of the carrier substrate and the receiving substrate is changed after the micro devices contact the receiving substrate. At least a portion of the micro devices are transferred from the carrier substrate onto the receiving substrate after changing the temperature of at least one of the carrier substrate and the receiving substrate.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 28, 2020
    Assignee: PlayNitride Inc.
    Inventors: Yun-Li Li, Tzu-Yang Lin, Yu-Hung Lai, Pei-Hsin Chen
  • Patent number: 10622346
    Abstract: A method for manufacturing an electronic device includes: providing a semiconductor carrier including first and second vertically integrated electronic structures laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier and electrically connecting the first and second vertically integrated electronic structures with each other; mounting the semiconductor carrier on a support carrier with the first side of the semiconductor carrier facing the support carrier; thinning the semiconductor carrier from a second side opposite the first side; and removing material of the semiconductor carrier in a separation region between the first and second vertically integrated electronic structures to separate a first semiconductor region of the first vertically integrated electronic structure from a second semiconductor region of the second vertically integrated electronic structure with the first and second vertically integrated electronic structures remain
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 14, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Andre Schmenn, Stefan Pompl, Damian Sojka, Katharina Umminger
  • Patent number: 10604358
    Abstract: A system for aligning an electronic component including a substrate having an aligning structure and an aligning device for aligning the electronic component with the aligning structure. The aligning structure defines a first and a second edge, which are at an angle relative to one another and are complementary to two sides of the electronic component to be aligned. The aligning device aligns the electronic component on the aligning structure by bringing sides of the electronic component into contact with both the first edge and also the second edge of the aligning structure. A dispensing unit dispensing the electronic component at a dispensing point by the device for aligning the electronic component close to the aligning structure. A receiving unit receives the electronic component aligned on the aligning structure in the device.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: March 31, 2020
    Assignee: Muehlbauer GmbH & Co. KG
    Inventors: Franz Brandl, Hans-Peter Monser, Sigmund Niklas
  • Patent number: 10591510
    Abstract: The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: March 17, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10593637
    Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shih-Fan Kuan, Yi-Jen Lo
  • Patent number: 10586746
    Abstract: Disclosed herein is a method for forming a semiconductor package. The method includes providing a first releasable chip carrier attached to a conductive layer. A circuit layer is formed on a surface of the conductive layer and a dielectric layer is applied over a surface of the circuit layer. A second releasable chip carrier is attached to a surface of the dielectric layer and the first releasable chip carrier is released from the conductive layer via facilitation of a first activating source. The circuitry of the circuit layer is operationally tested.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: March 10, 2020
    Assignee: Chip Solutions, LLC
    Inventor: Sukianto Rusli
  • Patent number: 10586780
    Abstract: Semiconductor device modules may include a semiconductor die and posts located laterally adjacent to the semiconductor die. A first encapsulant may laterally surround the semiconductor die and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on an active surface of the semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may cover the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
  • Patent number: 10553570
    Abstract: In an embodiment, an apparatus includes a packaging substrate and a die on the packaging substrate. The die includes an integrated passive device and a contact providing an electrical connection to the integrated passive device. A conductive trace of the packaging substrate is in an electrical path between the contact of the die and a ground potential. Such an integrated passive device and conductive trace can be included in a matching network configured to receive an amplified radio frequency signal from a power amplifier, for example. The packaging substrate can be, for example, a laminate substrate.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: February 4, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: David Penunuri, Weimin Sun, Russ Alan Reisner
  • Patent number: 10546833
    Abstract: A method of forming a plurality of electronic component packages includes attaching electronic components to a carrier, wherein high aspect ratio spaces exist between the electronic components. A dielectric sheet is laminated around the electronic components thus filling the spaces and forming a package body. The spaces are completely and reliably filled by the dielectric sheet and thus the package body has an absence of voids. Further, an upper surface of the package body is planar, i.e., has an absence of ripples or other non-uniformities. Further, lamination of the dielectric sheet is performed with a low cost lamination system.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: January 28, 2020
    Assignee: Amkor Technology, Inc.
    Inventor: Brett Arnold Dunlap
  • Patent number: 10538452
    Abstract: Surface modification layers and associated heat treatments, that may be provided on a sheet, a carrier, or both, to control both room-temperature van der Waals (and/or hydrogen) bonding and high temperature covalent bonding between the thin sheet and carrier. The room-temperature bonding is controlled so as to be sufficient to hold the thin sheet and carrier together during vacuum processing, wet processing, and/or ultrasonic cleaning processing, for example. And at the same time, the high temperature covalent bonding is controlled so as to prevent a permanent bond between the thin sheet and carrier during high temperature processing, as well as maintain a sufficient bond to prevent delamination during high temperature processing.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: January 21, 2020
    Assignee: CORNING INCORPORATED
    Inventors: Robert Alan Bellman, Dana Craig Bookbinder, Theresa Chang, Jeffrey John Domey, Robert George Manley, Prantik Mazumder, Alan Thomas Stephens, II
  • Patent number: 10535634
    Abstract: Embodiments herein relate to a system in package (SiP). The SiP may have a first layer of one or more first functional components with respective first active sides and first inactive sides opposite the first active sides. The SiP may further include a second layer of one or more second functional components with respective second active sides and second inactive sides opposite the second active sides. In embodiments, one or more of the first active sides are facing and electrically coupled with one or more of the second active sides through a through-mold via or a through-silicon via.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: January 14, 2020
    Assignee: INTEL CORPORATION
    Inventors: Vijay K. Nair, Chuan Hu, Thorsten Meyer
  • Patent number: 10535633
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a substrate, a first chip stack attached to the substrate, and a second chip stack attached to the substrate. The first chip stack and the second chip stack being attached to a same side of the substrate. The chip package further includes a molding compound layer surrounding the first chip stack and the second chip stack. The molding compound layer covers a topmost surface of the first chip stack. A topmost surface of the molding compound layer is substantially coplanar with a topmost surface of the second chip stack.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou
  • Patent number: 10535638
    Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
  • Patent number: 10529673
    Abstract: A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes a dielectric layer disposed over the contact pad, the dielectric layer including a first opening over the contact pad, and an insulator layer disposed over the dielectric layer, the insulator layer including a second opening over the contact pad. The packaged semiconductor device also includes a molding material disposed around the substrate, the dielectric layer, and the insulator layer and a wiring over the insulator layer and extending through the second opening, the wiring being electrically coupled to the contact pad.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 10529949
    Abstract: A lighting apparatus using an organic light-emitting diode and a method of fabricating the same are characterized in that an organic emissive material and a conductive film used as a cathode are deposited on the entire surface of a substrate, and then an organic emissive layer in a lighting area and contact areas becomes separated (disconnected or cut) by laser ablation, simultaneously with the formation of a contact hole for contact with an anode. Next, cathode contact and encapsulation processes are performed using an adhesive containing conductive particles and a metal film. This simplifies the fabrication process of the lighting apparatus without using an open mask (metal mask), which is a complicated tool, thus making it useful especially in roll-to-roll manufacturing.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: January 7, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Taejoon Song, Namkook Kim, Shinbok Lee, Soonsung Yoo, Hwankeon Lee
  • Patent number: 10510650
    Abstract: A semiconductor device and method of manufacture are presented in which a first semiconductor device and second semiconductor device are bonded to a first wafer and then singulated to form a first package and a second package. The first package and second package are then encapsulated with through interposer vias, and a redistribution structure is formed over the encapsulant. A separate package is bonded to the through interposer vias.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Tzuan-Horng Liu
  • Patent number: 10497687
    Abstract: Configurable semiconductor packages and processes to attain a defined configuration are provided. A configurable semiconductor package includes a base semiconductor package including a semiconductor die mounted on a surface of a package substrate. An expansion package can be mechanically coupled to a mounting member. The expansion package includes a second package substrate and one or more second semiconductor dies that can be surface mounted to the second package substrate. The second package substrate include an array of interconnects that permit coupling (mechanically and/or electrically) the second semiconductor die(s) to the package substrate of the base semiconductor package. The mounting member can mechanically attach to the base semiconductor package, resulting in a package assembly that has the array of interconnects adjacent to another array of interconnects in the package substrate of the base semiconductor package.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Russell S. Aoki, Casey G. Thielen
  • Patent number: 10468380
    Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 5, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Kyong-Mo Bang
  • Patent number: 10468381
    Abstract: A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: November 5, 2019
    Assignee: Apple Inc.
    Inventor: Jun Zhai
  • Patent number: 10466041
    Abstract: There is described a method for referencing a composite structure within an online vision inspection system. Referencing is performed independently from a positioning accuracy of an automated tool with which the composite structure is manufactured. Reference targets provided on a contour of a lay-up surface are used to correlate an image reference system with a mold reference system.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: November 5, 2019
    Assignee: BOMBARDIER INC.
    Inventor: Octavian Ioachim
  • Patent number: 10461069
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a bonding structure formed between a first substrate and a second substrate. The bonding structure includes a first polymer bonded to a second polymer, and a first conductive material bonded to a second conductive material. The semiconductor device includes a first TSV formed in the first substrate and an interconnect structure formed over the first TSV. The first TSV is between the interconnect structure and the bonding structure.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jing-Cheng Lin
  • Patent number: 10431569
    Abstract: A method of transferring micro devices is provided. A carrier substrate including a buffer layer and a plurality of micro devices is provided. The buffer layer is located between the carrier substrate and the micro devices. The micro devices are separated from one another and positioned on the carrier substrate through the buffer layer. A receiving substrate contacts the micro devices disposed on the carrier substrate. A temperature of at least one of the carrier substrate and the receiving substrate is changed, so that at least a portion of the micro devices are released from the carrier substrate and transferred onto the receiving substrate. A number of the at least a portion of the micro devices is between 1000 and 2000000.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: October 1, 2019
    Assignee: PlayNitride Inc.
    Inventors: Yun-Li Li, Tzu-Yang Lin, Yu-Hung Lai, Pei-Hsin Chen
  • Patent number: 10424531
    Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Bradley R. Bitz, Xiao Li, Jaspreet S. Gandhi
  • Patent number: 10403669
    Abstract: The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: September 3, 2019
    Assignee: Sony Corporation
    Inventors: Masaya Nagata, Kaori Takimoto
  • Patent number: 10366966
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer and a core material layer are sequentially formed on a first carrier. A portion of the core material layer is removed to form a core layer having a plurality of cavities. The first carrier, the dielectric layer, and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. The first carrier is removed from the dielectric layer. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Patent number: 10366941
    Abstract: Provided is a package structure including a substrate, a metal pad, a first polymer layer, a second polymer layer, a redistribution layer (RDL), and a third polymer layer. The metal pad is located on the substrate. The first polymer layer is located on the substrate. The first polymer layer has a first opening which exposes a portion of a top surface of the metal pad. The second polymer layer is located on the first polymer layer. The second polymer layer has a second opening which exposes the portion of the top surface of the metal pad and a first top surface of the first polymer layer. The RDL covers the portion of the top surface of the metal pad and extends onto a portion of the first top surface of the first polymer layer and the second polymer layer. The third polymer layer is located on the RDL.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: July 30, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Chen-Heng Liu, Yung-Fu Chang
  • Patent number: 10361160
    Abstract: This disclosure provides a package structure and its fabrication method. The package structure includes: a conductive pattern layer having a bump region and a wiring region, the bump region comprising a plurality of conductive bumps and a first dielectric material surrounding the plurality of conductive bumps, the wiring region comprising a plurality of first conductive wires and a second dielectric material covering and surrounding the plurality of first conductive wires; a circuit device with a plurality of connecting terminals disposed on the bump region, each of the connecting terminals corresponding with one of the conductive bumps; an insulation sealant formed on the second dielectric material and around sidewalls of the circuit device; and a third dielectric material covering the circuit device and the wiring region.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 23, 2019
    Assignee: PHOENIX & CORPORATION
    Inventor: Shih-Ping Hsu
  • Patent number: 10361033
    Abstract: A multilayer ceramic electronic component includes a laminated body, a first external electrode, a pair of second external electrodes, and a pair of insulating coating portions. The pair of insulating coating portions extends in a laminating direction between each of the pair of second external electrodes and the first external electrode on a second principal surface, from the second principal surface to respective portions of a first side surface and a second side surface. A maximum thickness of the first external electrode on the second principal surface is larger than a maximum thickness of the pair of second external electrodes on the second principal surface. The maximum thickness of the pair of second external electrodes on the second principal surface is larger than a maximum thickness of the pair of insulating coating portions on the second principal surface.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: July 23, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Kayatani, Takashi Sawada, Yasuo Fujii
  • Patent number: 10355039
    Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 16, 2019
    Assignee: Sony Corporation
    Inventors: Kengo Kotoo, Kaoru Koike
  • Patent number: 10319639
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: June 11, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh Krishnan, Sw Wang, CH Chew, How Kiat Liew, Fui Fui Tan