Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device Patents (Class 438/107)
  • Patent number: 10355039
    Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 16, 2019
    Assignee: Sony Corporation
    Inventors: Kengo Kotoo, Kaoru Koike
  • Patent number: 10319639
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: June 11, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh Krishnan, Sw Wang, CH Chew, How Kiat Liew, Fui Fui Tan
  • Patent number: 10318859
    Abstract: A card having a metal layer and an opening or cut-out region in the metal layer, with a dual-interface integrated circuit (IC) module disposed in the opening or cut-out region. A ferrite layer is disposed below the metal layer and a booster antenna is attached to the ferrite layer. A vertical hole extends beneath the IC module through the ferrite layer. The booster antenna may be physically connected to the IC module or may be configured to inductively couple to the IC module. In some embodiments, the IC may be disposed in or on a non-conductive plug disposed within the opening or cut-out region, or the vertical hole may have a non-conductive lining, or a connector may be disposed between the booster antenna and the IC module in the vertical hole.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: June 11, 2019
    Assignee: COMPOSECURE, LLC
    Inventors: Adam Lowe, John Herslow, Luis Dasilva, Brian Nester
  • Patent number: 10301171
    Abstract: A microelectromechanical system (MEMS) device is disclosed. The MEMS device includes a device substrate with a top device surface and a bottom device surface having a MEMS component in a device region. A top device bond ring is disposed on the top device surface surrounding the device region and a bottom device bond ring is disposed on the bottom device surface surrounding the device region. A top cap with a top cap bond ring is bonded to the top device bond ring by a top eutectic bond and a bottom cap with a bottom cap bond ring is bonded to the bottom device bond ring by a bottom eutectic bond. The eutectic bonds encapsulate the MEMS device.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: May 28, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Siddharth Chakravarty, Pradeep Yelehanka, Sharath Poikayil Poikayil Satheesh, Chun Hoe Yik, Rakesh Kumar, Natarajan Rajasekaran
  • Patent number: 10289944
    Abstract: A dual interface smart card having a metal layer includes an SC module, with contacts and RF capability, mounted on a plug, formed of non RF impeding material, between the top and bottom surfaces of the metal layer. The plug provides support for the IC module and a degree of electrical insulation and isolation from the metal layer. The resultant card can have contact and contactless operating capability and an entirely smooth external metal surface except for the contacts of the IC module.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: May 14, 2019
    Assignee: COMPOSECURE, LLC
    Inventors: John Herslow, Adam Lowe, Luis Dasilva, Brian Nester
  • Patent number: 10269583
    Abstract: The embodiments of the present disclosure relate to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a die attachment pad; a stud bump located on the die attachment pad and in direct contact with the die attachment pad; a first die located on the stud bump and electrically coupled to the stud bump; and a conductive attachment material located between the die attachment pad and the first die.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 23, 2019
    Assignee: STMicroelectronics Pte Ltd
    Inventor: Jing-En Luan
  • Patent number: 10269497
    Abstract: An electronic component includes a laminated body including dielectric layers and internal electrode layers, a first external electrode, a pair of second external electrodes, and a pair of insulating coating portions. The internal electrode layers include first and second internal electrode layers, the second internal electrode layers each include first and second extended electrode portions. A relationship of L1/L2>1.0 is satisfied when a length of a first contact portion with one second external electrode in contact with the first extended electrode portion in the length direction is L1, and a length of a second contact portion with the other second external electrode in contact with the second extended electrode portion in the length direction is L2.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: April 23, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuo Fujii, Takashi Sawada, Takayuki Kayatani
  • Patent number: 10261007
    Abstract: Disclosed herein are a microchip provided with a titanium oxide film between a glass substrate and a metal thin film; and a method for forming the metal thin film and the titanium oxide film on the glass substrate of the microchip. The microchip has a second microchip substrate that has the metal thin film inside a channel, and the titanium oxide film, which has a low extinction coefficient, is provided as a buffer layer between the substrate and the metal thin film such as a gold film.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: April 16, 2019
    Assignee: USHIO DENKI KABUSHIKI KAISHA
    Inventors: Kinichi Morita, Toshikazu Kawaguchi
  • Patent number: 10256215
    Abstract: A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kunsil Lee
  • Patent number: 10249436
    Abstract: A multilayer ceramic electronic component includes a laminated body, a first external electrode, a pair of second external electrodes, and a pair of insulating coating portions. The insulating coating portions extend in a laminating direction between each of the second external electrodes and the first external electrode on a second principal surface, and from the second principal surface to respective portions of first and second side surfaces. A maximum thickness of the first external electrode on the second principal surface is larger than a maximum thickness for each of the second external electrodes on the second principal surface. A maximum thickness for each of the insulating coating portions on the second principal surface is larger than the maximum thickness of the first external electrode on the second principal surface.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: April 2, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Kayatani, Takashi Sawada, Yasuo Fujii
  • Patent number: 10236273
    Abstract: A packaging structure and a packaging method are provided. The packaging structure includes a carrier semiconductor structure including a carrier substrate, a carrier dielectric layer, and a carrier top conductive layer inside the carrier dielectric layer and having a top exposed by the carrier dielectric layer. The packaging structure also includes a top semiconductor structure including a top substrate, a first dielectric layer, a zeroth conductive layer, and a second dielectric layer, wherein a position of the zeroth conductive layer corresponds to a position of the carrier top conductive layer. Further, the packaging structure includes a conductive plug formed on one side of the zeroth conductive layer, and penetrating through the top substrate, the first dielectric layer, and the second dielectric layer, wherein the conductive plug is electrically connected to each of the zeroth conductive layer and the carrier top conductive layer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: March 19, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Chong Wang, Hai Fang Zhang, Xuan Jie Liu
  • Patent number: 10217724
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: February 26, 2019
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao
  • Patent number: 10199351
    Abstract: Method and device for improved die bonding. In some embodiments, a bonding device includes a heating element configured to heat air. The bonding device also includes an application element having a plurality of holes configured to apply the heated air to a die, the application element is characterized by an arrangement of the plurality of holes that satisfies one or more directionality criteria. The bonding device further includes a controller configured to control the heating element and to set the temperature of the heated air expelled through the plurality of holes of the application element in order to satisfy one or more bonding criteria.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 5, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: José Manuel Flores, Rogelio Eduardo Estrada, Daniel Orozco Mariscal
  • Patent number: 10192094
    Abstract: The present disclosure discloses a package for an ultrasonic fingerprint sensor comprising: a substrate comprising a top surface and a plurality of first connecting electrodes formed on the top surface; a control chip arranged on the substrate and comprising a periphery-stepped upper surface facing away from the substrate, the periphery-stepped upper surface comprising a central upper surface and a peripheral lower surface surrounding and being lower than the central upper surface, the control chip comprising a plurality of second connecting electrodes formed on the central upper surface, and a plurality of third connecting electrodes formed on the peripheral lower surface connected to the second connecting electrodes; bonding wires configured to bond the first connecting electrodes to the third connecting electrodes; an ultrasonic transducer arranged on the control chip; and packing material configured to package the substrate, the bonding wires and the ultrasonic transducer as one module.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: January 29, 2019
    Assignee: NANCHANG O-FILM BIO-IDENTIFICATION TECHNOLOGY CO., LTD
    Inventors: Wensi Sun, Anpeng Bai
  • Patent number: 10192093
    Abstract: The present disclosure discloses an ultrasonic fingerprint sensor package. The ultrasonic fingerprint sensor package includes a substrate, a control chip, bonding wires, an ultrasonic probe, and packaging material. The control chip is arranged on the substrate. The control chip is connected to the substrate by the bonding wires using a wire bonding technology. The ultrasonic probe is arranged on the control chip and is configured to emit ultrasonic wave and receive ultrasonic wave reflected by an object. The packaging material covers the substrate, the control chip, and the bonding wires and fixing the ultrasonic probe using a molding technology.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: January 29, 2019
    Assignee: NANCHANG O-FILM BIO-IDENTIFICATION TECHNOLOGY CO., LTD.
    Inventors: Wensi Sun, Anpeng Bai
  • Patent number: 10192843
    Abstract: Methods of making semiconductor device modules may involve forming holes in a sacrificial material and placing an electrically conductive material in the holes. The sacrificial material may be removed to expose posts of the electrically conductive material. A stack of semiconductor dice may be placed between at least two of the posts after removing the sacrificial material, one of the semiconductor dice of the stack including an active surface facing in a direction opposite a direction in which another active surface of another of the semiconductor dice of the stack. The posts and the stack of semiconductor dice may be at least laterally encapsulated in an encapsulant. Bond pads of the one of the semiconductor dice may be electrically connected to corresponding posts after at least laterally encapsulating the posts and the stack of semiconductor dice.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ashok Pachamuthu, Chan H. Yoo, Szu-Ying Ho, John F. Kaeding
  • Patent number: 10186484
    Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.
    Type: Grant
    Filed: September 27, 2014
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Donald W. Nelson, Patrick Morrow, Kimin Jun
  • Patent number: 10186499
    Abstract: IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be reduced relative to its thickness during the molding process. Another IC chip, heat spreader, etc. may then occupy the resultant recess framed by the molding compound to achieve a fine stacking pitch. In some embodiments, a package-on-package (PoP) assembly includes a center-molded IC chip flip-chip-bonded to a first package substrate. A second substrate to which a second IC chip is flip-chip bonded is then electrically coupled to the first substrate by through-molding vias. Within the PoP assembly, the second IC chip may be disposed back-to-back with the center-molded IC chip so as to occupy the recess framed by the molding compound.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 22, 2019
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Klaus Reingruber
  • Patent number: 10163832
    Abstract: A redistribution circuit structure electrically connected to a die underneath is provided. The redistribution circuit structure includes a dielectric layer and a conductive layer. The dielectric layer partially covers the die, so that a conductive pillar of the die is exposed by the dielectric layer. The conductive layer is disposed over the dielectric layer and electrically connected to the die by the conductive pillar. The conductive layer includes a multilayer structure, wherein an average grain size of one layer of the multilayer structure is less than or equal to 2 ?m. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Yun Huang, Ming-Che Ho
  • Patent number: 10157909
    Abstract: A 3D semiconductor device, the device including: a first layer including first transistors each including a silicon channel; a second layer including second transistors each including a silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer underlying the first transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistor is a junction-less transistor.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: December 18, 2018
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 10155659
    Abstract: A vacuum sealed MEMS and CMOS package and a process for making the same may include a capping wafer having a surface with a plurality of first cavities, a first device having a first surface with a second plurality of second cavities, a hermetic seal between the first surface of the first device and the surface of the capping wafer, and a second device having a first surface bonded to a second surface of the first device. The second device is a CMOS device with conductive through vias connecting the first device to a second surface of the second device, and conductive bumps on the second surface of the second device. Conductive bumps connect to the conductive through vias and wherein a plurality of conductive bumps connect to the second device. The hermetic seal forms a plurality of micro chambers between the capping wafer and the first device.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Yi-Chuan Teng, Hung-Chia Tsai, Chia-Hua Chu
  • Patent number: 10154592
    Abstract: The invention provides transient devices, including active and passive devices that electrically and/or physically transform upon application of at least one internal and/or external stimulus. Materials, modeling tools, manufacturing approaches, device designs and system level embodiments of transient electronics are provided.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: December 11, 2018
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John A. Rogers, Chi Hwan Lee, Lan Yin, Xian Huang, Cecilia Maria das Neves Barbosa Leal, Daniel Vincent Harburg
  • Patent number: 10153219
    Abstract: A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-jun Jeon, Nae-in Lee, Byung-Iyul Park
  • Patent number: 10147710
    Abstract: Embodiments of the invention include multi-die package and methods of making such multi-die packages. In an embodiment a mold layer has a first surface and a second surface that is opposite from the first surface. One or more first electrical components that each have a solderable terminal that is oriented to face the first surface of the mold layer. The mold layer may also have one or more second electrical components that each have a second type of terminal that is oriented to face the second surface of the mold layer. Embodiments may also include one or more conductive through vias formed between the first surface of the mold layer and the second surface of the mold layer. Accordingly an electrical connection may be made from the second surface of the mold layer to the first electrical components that are oriented to face the first surface of the mold layer.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Vijay K. Nair, Thorsten Meyer
  • Patent number: 10125014
    Abstract: Integrated circuit packages and methods of forming same are provided. A method includes attaching a first die and a second die to a carrier, the first die having a first contact pad, the second die having a second contact pad, the first contact pad and the second contact pad having different structures. A release layer is formed over the first die and the second die. An encapsulant is injected between the carrier and the release layer. One or more redistribution layers (RDLs) are formed over the first die, the second die and the encapsulant, the first contact pad and the second contact pad being in electrical contact with the one or more RDLs.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo Lung Pan, Chung-Shi Liu, Hao-Yi Tsai, Yu-Feng Chen, Yu-Jen Cheng
  • Patent number: 10103106
    Abstract: The present disclosure relates to an integrated circuit module with electromagnetic shielding. The integrated circuit module includes a die with an input/output (I/O) port at a bottom surface of the die, a mold compound partially encapsulating the die and leaving the bottom surface of the die exposed, a first dielectric pattern over the bottom surface of the die, a redistribution structure over the first dielectric pattern, and a shielding structure. The I/O port at the bottom surface of the die is exposed through the first dielectric pattern. The redistribution structure includes a shield connected element that is coupled to the I/O port and extends laterally beyond the die. The shielding structure resides over a top surface of the mold compound, extends along side surfaces of the mold compound, and is in contact with the shield connected element. Herein, the shielding structure does not extend vertically beyond the shield connected element.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: October 16, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Thong Dang, Dan Carey, Ma Shirley Asoy
  • Patent number: 10096552
    Abstract: A fan-out semiconductor package includes: a first semiconductor chip; a first encapsulant; a connection member including first vias and a first redistribution layer; a second semiconductor chip; a second encapsulant; a second redistribution layer; second vias; and third vias. A length of the longest side of a first cut surface of the second via is less than that of the longest side of a second cut surface of the third via, the first cut surface of the second via and the second cut surface of the third via being cut by a plane on any level parallel to the second active surface.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 9, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Han Kim, Eun Jung Jo, Jung Ho Shim
  • Patent number: 10089908
    Abstract: The disclosure provides a micro light-emitting diode display panel. The array substrate is arranged with a plurality of pixels in an array. Each of the pixels at least includes a subpixel of three colors. Each of the subpixels is disposed with at least one ?LED chip corresponding to color of the subpixel. Bin levels of the ?LED chips of the subpixels with the same color in two adjacent pixels are different and a difference of peak wavelengths >2 nm. The disclosure further provides a manufacturing method, the ?LED chips with the corresponding color in the subpixel of the array substrate are transfer printed from the transfer printing plate to corresponding subpixels. The color and the bin level of the ?LED chips in each transfer printing are identical. Bin levels of the ?LED chips in the sub-pixels with the same color in two adjacent pixels are different.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: October 2, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Lixuan Chen, Hsiao Hsien Chen, Yung-jui Lee
  • Patent number: 10083949
    Abstract: A method includes forming a dielectric layer over a radiation de-bondable coating. The radiation de-bondable coating is over a carrier, and the radiation de-bondable coating includes metal particles therein. Metal posts are formed over the dielectric layer. A device die is attached to the dielectric layer. The device die and the metal posts are encapsulated in an encapsulating material. A plurality of redistribution lines is formed on a first side of the encapsulating material, and is electrically coupled to the device die and the metal posts. The carrier is de-bonded by projecting a radiation source on the radiation de-bondable coating to decompose the radiation de-bondable coating. Electrical connections are formed on a second side of the encapsulating material. The electrical connections are electrically coupled to the metal posts.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu, Yi-Jou Lin
  • Patent number: 10068868
    Abstract: A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Liang Shao, Chih-Hang Tung, Wen-Lin Shih, Hsiao-Yun Chen, Chen-Hua Yu
  • Patent number: 10062662
    Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 10037969
    Abstract: An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Nan Shih
  • Patent number: 10014429
    Abstract: A method of fabricating a semiconductor structure includes the formation of a first bonding layer at least substantially comprised of a first III-V material on a major surface of a first element, and formation of a second bonding layer at least substantially comprised of a second III-V material on a major surface of a second element. The first bonding layer and the second bonding layer are disposed between the first element and the second element, and the first element and the second element are attached to one another at a bonding interface disposed between the first bonding layer and the second bonding layer. Semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: July 3, 2018
    Assignee: SOITEC
    Inventors: Fred Newman, Frank Reinhardt, Chantal Arena
  • Patent number: 10008478
    Abstract: The present disclosure discloses a fabrication method for wafer-level packaging, comprising: forming a first photoresist on a first chip and a plurality of first openings at the first photoresist to expose a functional surface of the first chip, forming an under-bump metal layer on the functional surface exposed through the plurality of first openings, and removing the first photoresist; connecting a functional solder bump of a second chip to the under-bump metal layer on the first chip; forming a filling layer between the first chip, and the second chip; and forming a connecting member on the first chip, wherein a solder ball is disposed at a top surface of the connecting member, and an apex of the solder ball is higher than a top surface of the second chip.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: June 26, 2018
    Assignee: TONGFU MICROELECTRONICS CO., LTD.
    Inventor: Wanchun Ding
  • Patent number: 9997413
    Abstract: A semiconductor structure containing a plurality of stacked vertical field effect transistor (FETs) is provided. After forming a first vertical FET of a first conductivity type at a lower portion of a semiconductor fin, a second vertical FET of a second conductivity type is formed on top of the first vertical FET. The second conductivity type can be opposite to, or the same as, the first conductivity type. A source/drain region of the first vertical FET is electrically connected to a source/drain region of the second vertical FET by a conductive strip structure.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 9991149
    Abstract: A transfer substrate with a compliant resin is used to bond one or more chips to a target wafer. An implant region is formed in a transfer substrate. A portion of the transfer substrate is etched to form a riser. Compliant material is applied to the transfer substrate. A chip is secured to the compliant material, wherein the chip is secured to the compliant material above the riser. The chip is bonded to a target wafer while the chip is secured to the compliant material. The transfer substrate and compliant material are removed from the chip. The transfer substrate is opaque to UV light.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: June 5, 2018
    Assignee: SKORPIOS TECHNOLOGIES, INC.
    Inventors: Damien Lambert, John Spann, Stephen Krasulick
  • Patent number: 9991244
    Abstract: Method for forming a semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a first polymer material and a second conductive material embedded in a second polymer material. The first conductive material is bonded to the second conductive material and the first polymer material is bonded to the second polymer material. The semiconductor device also includes at least one through silicon via (TSV) extending from a bottom surface of the first semiconductor wafer to a metallization structure of the first semiconductor wafer. The semiconductor device structure also includes an interconnect structure formed over the bottom surface of the first semiconductor wafer, and the interconnect structure is electrically connected to the metallization structure via the TSV.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jing-Cheng Lin
  • Patent number: 9978629
    Abstract: A method of transferring micro devices is provided. A carrier substrate including a plurality of first electrodes and a plurality of micro devices is provided. The micro devices are separated from each other and respectively electrically connected to the first electrodes. A receiving substrate is made to relatively close to the carrier substrate. The receiving substrate includes a plurality of second electrodes, and the second electrodes and the first electrodes are opposite in electrical property. A first voltage and a second voltage are applied to a portion of the adjacent two first electrodes, so that the micro devices are released from the carrier substrate to the receiving substrate and bonded to the receiving substrate. The first voltage is different from the second voltage. In addition, a micro devices transfer apparatus is also provided.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: May 22, 2018
    Assignee: Acer Incorporated
    Inventors: Jui-Chieh Hsiang, Chih-Chiang Chen
  • Patent number: 9960145
    Abstract: A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound residing on the top surface. A first mold compound is disposed on the top surface of the carrier. A first thinned flip chip die resides over a first portion of the first mold compound with interconnects extending through the first portion to the top surface wherein the first portion of the mold compound fills a region between the first flip chip die and the top surface. A second mold compound resides over the substrate and provides a first recess over the first flip chip die wherein the first recess extends to a first die surface of the first flip chip die. A third mold compound resides in the first recess and covers an exposed surface of the flip chip die.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 1, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Thomas Scott Morris, Jonathan Hale Hammond, David Jandzinski, Stephen Parker, Jon Chadwick
  • Patent number: 9953907
    Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Nai-Wei Liu, Wan-Ting Shih
  • Patent number: 9953933
    Abstract: A semiconductor package includes a substrate, a die, an insulating die attach film, a dummy die, a conductive layer, and an electrically conductive molding compound or encapsulant. The first surface of the substrate includes a plurality of internal leads, and the second surface of the substrate includes a plurality of external electrically conductive pads and an electrically conductive ground terminal. A non-conductive flow over wire die attach film is placed to surround and encase the die. The dummy die overlies the die and a conductive layer overlies the dummy die. The electrically conductive molding compound is formed to encase the various components of the semiconductor device. The electrically conductive molding compound is electrically coupled to the electrically conductive ground terminal and the conductive layer forming an EMI shield for the die in the package.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 24, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Aaron Cadag, Rennier Rodriguez, Ela Mia Cadag
  • Patent number: 9953955
    Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 9953946
    Abstract: A die-bonding layer formation film to be used for fixing a processed product to an adherend, includes an adhesive layer, wherein, the storage elastic modulus has a local minimum value at a temperature within a range of 80° C. to 150° C., wherein the adhesive layer has a shear strength to a peeling strength test substrate of 20 N/2 mm? [N/(2 mm×2 mm)] or more and 50 N/2 mm? [N/(2 mm×2 mm)] or less, wherein the shear strength is measured after the processed product is placed above the peeling strength test substrate via the die-bonding layer formation film and the die-bonding layer formation film on the peeling strength test substrate is heated at 175° C. for 1 hour and then further maintained under an environment of 250° C. for 30 seconds. Bubbles (voids) are unlikely to grow at the boundary between the adhesive layer and an adherend even when subjected to thermal history.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: April 24, 2018
    Assignee: LINTEC CORPORATION
    Inventors: Yuichiro Azuma, Hideaki Suzuki, Naoya Saiki, Yuta Sagawa
  • Patent number: 9945030
    Abstract: Provided is a free-standing silicon oxide film that is under tensile stress. Also, provided are methods of making a free-standing silicon oxide film that is under tensile stress. The methods use low-power PECVD deposition of silicon oxide. Methods of imaging one or more objects (e.g., cells) using a free-standing silicon oxide film that is under tensile stress is also provided.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: April 17, 2018
    Assignee: SiMPore Inc.
    Inventors: Jon-Paul DesOrmeaux, Christopher C. Striemer
  • Patent number: 9947632
    Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on the major surface and an encapsulant covering at least the major surface. A peripheral edge of each contact defines a contact area on the major surface. The device also includes one or more bond pads located outside the encapsulant. Each bond pad is electrically connected to a respective contact located on the major surface of the substrate by a respective metal filled via that passes through the encapsulant. A sidewall of each respective metal filled via, at the point at which it meets the respective contact, falls inside the contact area defined by the respective contact when viewed from above the major surface of the substrate, whereby none of the metal filling each respective via extends outside the contact area of each respective contact.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: April 17, 2018
    Assignee: Nexperia B.V.
    Inventors: Chi Ho Leung, Pompeo V Umali, Shun Tik Yeung, Wai (Kan Wae) Lam
  • Patent number: 9938134
    Abstract: A microelectromechanical systems (MEMS) package with high gettering efficiency is provided. A MEMS device is arranged over a logic chip, within a cavity that is hermetically sealed. A sensing electrode is arranged within the cavity, between the MEMS device and the logic chip. The sensing electrode is electrically coupled to the logic chip and is a conductive getter material configured to remove gas molecules from the cavity. A method for manufacturing the MEMS package is also provided.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shiang-Chi Lin, Jung-Huei Peng, Yu-Chia Liu, Yi-Chien Wu, Wei Siang Tan
  • Patent number: 9941235
    Abstract: A power module substrate with a Ag underlayer of the invention includes: a circuit layer that is formed on one surface of an insulating layer; and a Ag underlayer that is formed on the circuit layer, in which the Ag underlayer is composed of a glass layer that is formed on the circuit layer side and a Ag layer that is formed by lamination on the glass layer, and regarding the Ag underlayer, in a Raman spectrum obtained by a Raman spectroscopy with incident light made incident from a surface of the Ag layer on a side opposite to the glass layer, when a maximum value of intensity in a wavenumber range of 3,000 cm?1 to 4,000 cm?1 indicated by IA, and a maximum value of intensity in a wavenumber range of 450 cm?1 to 550 cm?1 is indicated by IB, IA/IB is 1.1 or greater.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: April 10, 2018
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Shuji Nishimoto, Yoshiyuki Nagatomo
  • Patent number: 9929125
    Abstract: A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound residing on the top surface. A first mold compound is disposed on the top surface of the carrier. A first thinned flip chip die resides over a first portion of the first mold compound with interconnects extending through the first portion to the top surface wherein the first portion of the mold compound fills a region between the first flip chip die and the top surface. A second mold compound resides over the substrate and provides a first recess over the first flip chip die wherein the first recess extends to a first die surface of the first flip chip die. A third mold compound resides in the first recess and covers an exposed surface of the flip chip die.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: March 27, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Thomas Scott Morris, Jonathan Hale Hammond, David Jandzinski, Stephen Parker, Jon Chadwick
  • Patent number: 9905549
    Abstract: The present disclosure provides a semiconductor apparatus having a plurality of semiconductor dies stacked in a face-to-face manner and a method for preparing the same. By stacking dies having different functions vertically in a face-to-face manner, a face-to-face communication is implemented between the dies having different functions. In addition, stacking the dies having different functions vertically in a face-to-face manner reduces the occupied area of the semiconductor apparatus, as compared to a semiconductor apparatus with dies having different functions arranged in a laterally adjacent manner. Furthermore, the signal path of the dies having different functions vertically stacked in the face-to-face manner is shorter than the signal path of the dies having different functions arranged in a laterally adjacent manner; consequently, the dies having different functions vertically stacked in the face-to-face manner of the present disclosure can be applied to high-speed electronic devices.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: February 27, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 9898567
    Abstract: A method (and system) of automatically legalizing a circuit layout with layout objects in a presence of a plurality of non-uniform grids is disclosed. The method comprises generating a set of layout constraints comprising design rule constraints and gridding requirements based on the plurality of non-uniform grids. In addition, the method comprises processing the set of layout constraints to a feasible form using Boolean variables by determining infeasibility of the set of layout constraints, identifying infeasible layout constraints from the set of layout constraints, and resolving the infeasibility by a constraint relaxation process. Additionally, the method comprises generating an output circuit layout, for display to a user, by solving the set of layout constraints in the feasible form with standard linear program solvers.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: February 20, 2018
    Assignee: Synopsys, Inc.
    Inventors: Nitin Dileep Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir Husain Batterywala