Abstract: A semiconductor device includes a via electrode penetrating a substrate and a back-side molding layer covering a back-side surface of the substrate. The back-side molding layer contacts a sidewall of a back-side end portion of the via electrode, which is a portion of the via electrode that protrudes from the back-side surface of the substrate.

Abstract: A first cavity-down ball grid array (BGA) package includes a substrate member and an array of bond balls. The array of bond balls includes a pair of parallel extending rows of outer mesh bond balls and a row of inner signal bond balls that is parallel to the pair of rows of outer mesh bond balls. A surface-mount blocking element is disposed between the row of inner signal bond balls and the pair of rows of outer mesh bond balls. The surface-mount blocking element is either a passive or an active component of the BGA package. In one example, the first cavity-down BGA package is surface-mounted to a second cavity-down BGA package to form a package-on-package (POP) security module. The surface-mount blocking element provides additional physical barrier against the probing of the inner signal bond balls. Sensitive data is therefore protected from unauthorized access.

Abstract: Provided is a semiconductor device including a flexible circuit board which includes a first external electrode provided on a first face and second and third external electrodes provided on a second face; a plurality of memory devices and passive components; a supporter which is provided with a groove on one face; and a computing processor device. The memory devices and the passive components are connected to the first external electrode, the one face of the supporter is bonded on the first face of the flexible circuit board so that the groove houses the memory devices and the passive components. The flexible circuit board is bent along a perimeter of the supporter to be wrapped around a side face and another face of the supporter. On the flexible circuit board, the second external electrode is provided on the second face which is opposite to the first external electrode, and the third external electrode is provided on the second face which is bent to the another face of the supporter.

Abstract: A package substrate includes a core layer, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core layer. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded pads are located on an upper surface of the insulating layer.

Abstract: A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.

Abstract: A semiconductor package is disclosed, which includes: a first substrate; a first semiconductor component disposed on the first substrate; a second substrate disposed on the first semiconductor component and electrically connected to the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate and encapsulating the first semiconductor component and the conductive elements. The present invention can control the height and volume of the conductive elements since the distance between the first substrate and the second substrate is fixed by bonding the second substrate to the first semiconductor component.

Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.

Abstract: A method for forming a reduced thickness semiconductor package is disclosed and may include providing a first die with an active layer, a through-silicon via (TSV), and a pattern and an under bump metal (UBM) in a dielectric layer on the active layer. A carrier may be bonded to the dielectric layer and the UBM. The first die may be thinned to expose the TSV. A bump pad may be formed on the exposed TSV and a second die may be bonded to the bump pad. The first die, the second die, and an outer surface of the dielectric layer may be encapsulated utilizing a first encapsulant. The carrier may be removed from the dielectric layer and the UBM, and a solder ball may be formed on the UBM. A groove may be formed through the dielectric layer and into the first die.

Abstract: A semiconductor module includes a case including a receiving space that is formed by a frame portion and a pair of wall portions disposed to face each other with the frame portion therebetween. The wall portion includes a heat-dissipation portions and a support wall that supports the heat-dissipation portions at the frame portion, and the wall portion includes a heat-dissipation portion and a support wall that supports the heat-dissipation portion at the frame portion. The heat-dissipation portions provided at the wall portion are separately provided by being disposed to face a plurality of semiconductor device blocks respectively. A plurality of separate heat-dissipation portions is surrounded by the support wall, the support wall is deformed to recessed from the frame portion through the separate heat-dissipation portions inside the case such that a plurality of insulating sheets is closely joined to a plurality of lead frames and the plurality of heat-dissipation portions.

Abstract: Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer.

Abstract: A semiconductor package includes a semiconductor chip, an inductor applied to the semiconductor chip. The inductor includes at least one winding. A space within the at least one winding is filled with a magnetic material.

Abstract: A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers.

Abstract: A semiconductor package including a lower package including a lower package substrate and a lower semiconductor chip, the lower package substrate including an interconnection part and a core part, the core part including connection vias exposed by openings, the lower semiconductor chip buried in the core part, an upper package including an upper package substrate, an upper semiconductor chip provided on the upper package substrate, and solder balls provided on a bottom surface of the upper package substrate, and an intermetallic compound layer at an interface between the connection vias and the solder balls in the openings may be provided.

Abstract: A through package vias (TPV), a package including a plurality of the TPVs, and a method of forming the through package via are provided. Embodiments of a through package via (TPV) for a package include a build-up film layer, a metal pad disposed over the build-up film layer, a polymer ring disposed over the metal pad, and a solder feature electrically coupled with the metal pad.

Abstract: Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

Abstract: A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

Abstract: A power electronic device includes first and second electronic switches, each integrated on a package having a low parasitic inductance, a supply terminal and a ground terminal. The first conduction terminal of the first switch may be coupled with the supply terminal, and the second conduction terminal of the second electronic switch may be coupled with the ground terminal. The corresponding control terminals of the switches may be coupled to corresponding pilot drivers. The package may include first and second electric terminals, wherein the second conduction terminal of the first switch is coupled to the first electric terminal, and the first conduction terminal of the second switch is coupled to the second electric terminal. A first inductance may be interposed between the first electric terminal and the output terminal and/or a second inductance interposed between the second electric terminal and the output terminal.

Abstract: A semiconductor package including an internal package including at least one semiconductor chip sealed with an internal seal, an external substrate on which the internal package is mounted, and an external seal sealing the internal package is provided. Also provided is a method of manufacturing the semiconductor package including forming an internal package including at least one semiconductor chip sealed with an internal seal, mounting the internal package on an external substrate, and sealing the internal package with an external seal. The internal seal and the external seal have different Young's moduli, for example, a Young's modulus of the internal seal is smaller than a Young's modulus of the external seal. Accordingly, the semiconductor package is less susceptible to warpage and can be handled with relative ease in subsequent semiconductor package processes.

Abstract: A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder treatment improves the adhesion between the exposed traces (e.g., the non-BOT traces) and a solder resist layer.

Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.

Abstract: Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip.

Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.

Abstract: A semiconductor device can reduce the number of bonding wires. The semiconductor device includes two or more semiconductor elements each of which has electrodes on a first main surface and a second main surface, an electrode plate that has one surface which is bonded to electrodes on the first main surfaces of the semiconductor elements, with a first bonding material layer interposed therebetween, and extends over the electrodes on the first main surfaces of the two or more semiconductor elements, and a conductive plate that includes a first lead terminal and a semiconductor element bonding portion which is bonded to electrodes on the second main surfaces of the semiconductor elements. A second bonding material layer is interposed therebetween, and is connected to the electrodes on the second main surfaces of the two or more semiconductor elements.

Abstract: A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion.

Abstract: A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.

Abstract: Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate.

Abstract: A stacked integrated circuit package and a method for manufacturing the same are provided. The stacked integrated circuit package includes a first integrated circuit package comprising a first substrate, a first semiconductor chip, and a first molding portion, an interposer mounted on the first substrate to be electrically connected to the circuit pattern of the first substrate by a first solder bump, the interposer being provided with an opening to accommodate the first semiconductor chip, and a second integrated circuit package stacked on the first integrated circuit package and the interposer and electrically connected to the interposer by a second solder bump, the second integrated circuit package comprising a second substrate, a second semiconductor chip, and a second molding portion.

Abstract: A method for forming a multi junction photovoltaic device includes providing a germanium layer and etching pyramidal shapes in the germanium layer such that (111) facets are exposed to form a textured surface. A first p-n junction is formed on or over the textured surface from III-V semiconductor materials. Another p-n junction is formed over the first p-n junction from III-V semiconductor materials and follows the textured surface.

Abstract: A semiconductor device has a first semiconductor die and an encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and encapsulant. A thermal interface material is formed over the first semiconductor die and encapsulant. A stiffening layer is formed over the first semiconductor die and an edge portion of the encapsulant. Alternatively, an insulating layer is formed adjacent to the first semiconductor die and a stiffening layer is formed over the insulating layer. The stiffening layer includes metal, ferrite, ceramic, or semiconductor material. A heat spreader is disposed over the first semiconductor die and a central portion of the encapsulant. Openings are formed in the heat spreader. A recess is formed in the heat spreader along an edge of the heat spreader. A coefficient of thermal expansion (CTE) of the stiffening layer is less than a CTE of the heat spreader.

Abstract: A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package.

Abstract: A stacked package includes a substrate, and a first structure bonded to the substrate. The first structure has a plurality of bumps, and a first hydrophilic coating is on sidewalls of the first structure. The stacked package further includes a second structure bonded to the plurality of bumps. The first hydrophilic coating is on sidewalls of the second structure. The first structure is between the second structure and the substrate. The stacked package further includes a housing, wherein the housing defines a volume enclosing the first structure and the second structure. A second hydrophilic coating is on sidewalls of an inner surface of the housing. The stacked package further includes a cooling fluid within the volume enclosing the first structure and the second structure. A top surface of the cooling fluid is above a top surface of the second structure.

Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

Abstract: An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable metallic layer deposited over the first side of the substrate and in the via. A through via may be formed through the substrate aligned with the via in the molding with an electrically conductive liner deposited in the through via in electrical contact with the conformable metallic layer. The integrated circuit structure may further include a connector element such as a solder ball on an end of the through via on a second side of the substrate opposite the first side. The integrated circuit structure may further include a die on the first side of the substrate in electrical contact with another through via or with a redistribution layer.

Abstract: Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated.

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

Abstract: A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure.

Abstract: A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer

Abstract: A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.

Abstract: A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Abstract: The invention relates to a method for producing chip stacks with the following method sequence: applying an especially dielectric and/or photostructurable base layer to one carrier side of a carrier which on its carrier side is provided with an adhesively acting adhesion zone and a less adhesively acting support zone, the base layer being applied largely over the entire surface at least to the support zone, building up the chip stacks on the base layer, potting of the chip stacks, detaching the carrier from the base layer. Moreover the invention relates to a carrier for executing this method.

Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.

Abstract: A method for fabricating packaged semiconductor devices in panel format; placing a panel-sized metallic grid with openings on an adhesive tape (292); attaching semiconductor chips—coated with a polymer layer having windows for chip terminals —face-down onto the tape (293); laminating low CTE insulating material to fill gaps between chips and grid (294); turning over assembly to place carrier under backside of chips and lamination and to remove tape (295); plasma-cleaning assembly front side, sputtering uniform metal layer across assembly (296); optionally plating metal layer (297); and patterning sputtered layer to form rerouting traces and extended contact pads for assembly (298).

Abstract: The disclosure relates to a stacked package and a method for manufacturing the same. The stacked package includes: a lower package including a substrate formed with ball lands in a periphery of an upper surface thereof, a semiconductor chip mounted over the upper surface, first solder balls formed over the ball lands and each having a side surface cut along an edge of the substrate and a polished upper surface, and a mold part for molding the upper surface including the semiconductor chip and the first solder balls, the cutted side surfaces and polished upper surfaces being exposed by the mold part; and an upper package stacked over the lower package and provided with second solder balls bonded to the first solder balls.

Abstract: A method for making a microelectronic package includes the steps of providing a microelectronic assembly that further includes a substrate with a plurality of conductive elements thereon, a carrier, and a plurality of substantially rigid metal elements extending from the carrier and joined to the conductive elements; and removing the carrier from the microelectronic assembly to expose contact surfaces of the respective ones of the plurality of metal elements remote from the first conductive pads.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

Abstract: A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.

Abstract: It is intended to provide an electronic component mounting device and an operation performing method for mounting electronic components so that both the operation quality and the productivity can be improved. In operation performing procedures, when an electronic component belongs to the first division, an operating head is made to move up and down based on an approximate operation position height derived from an approximate curved surface of the top surface of a board which is calculated by using the height measurement result obtained by measuring a plurality of height measuring points on the surface of the board, and when the electronic component belongs to the second division, the operating head is made to move up and down based on an individual operation position height obtained by individually measuring the board height at the operation position.

Abstract: A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.

Abstract: In accordance with certain embodiments, an electric device includes a flexible substrate having first and second conductive traces on a first surface thereof and separated by a gap therebetween, an electronic component spanning the gap, and a stiffener configured to substantially prevent flexing of the substrate proximate the gap during flexing of the substrate.

Abstract: A mechanism is provided by which signal travel distance within and between semiconductor device packages is reduced and substrate size and complexity can be reduced. This capacity is provided by virtue of a conductive via that intersects a wire bond molded within a package substrate. The via provides a direct electrical connection between an external signal transmitter or receiver and the points connected by the wire bond, and thereby avoiding the need for the signal to transit built up interconnects in the semiconductor device package. Conductive vias can provide connectivity through or to a package substrate, and can be through vias or blind vias. The conductive via is formed by either mechanical or laser drilling, and is filled using standard fill techniques, and is therefore readily incorporated into a package production flow.