Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-hole vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.

Abstract: A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a second semiconductor layer having a second circuit surface facing the first wiring layer and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface and connected to a first wiring layer of the first chip, and a second electrode extending through the second semiconductor layer and connected to the second wiring layer. The third chip includes a third semiconductor layer having a third circuit surface and a third rear surface facing the second chip, a third wiring layer provided on the third circuit surface, and a third electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second electrode through bumps.

Abstract: An electronic device includes an electronic part including a first substrate having a group of first terminals over a first front surface and having a concavity in a back surface, a filler placed in the concavity, and a flat plate placed over the back surface with the filler therebetween, and further includes a second substrate disposed on the first front surface side of the first substrate and having a group of second terminals bonded to the group of first terminals over a second front surface opposite the first front surface. The filler and flat plate minimize deformation of the first substrate and variation in the distance between the group of first terminals and the group of second terminals caused by the deformation of the first substrate, which thereby reduces the occurrence of a failure in bonding together the group of first terminals and the group of second terminals.

Abstract: A laminated semiconductor device includes: three or more semiconductor chips that are laminated; resins that are disposed among the semiconductor chips, the resins softening by heating; and support members that are disposed among the semiconductor chips and that contacts the adjacent semiconductor chips, the support members deforming by external force when a temperature of the support members reaching a predetermined temperature.

Abstract: A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

Abstract: An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

Abstract: Wafers include multiple bulk redistribution layers. A terminal contact pad is on a surface of one of the bulk redistribution layers. A final redistribution layer is formed on the surface and in contact with the terminal contact pad. The final redistribution layer is formed from a material other than a material of the plurality of bulk redistribution layers. A solder ball is formed on the terminal contact pad.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member.

Abstract: A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.

Abstract: There is provided a method of manufacturing a stack package. The method includes vertically stacking core dies on a base die wafer to provide a stack structure, forming partition walls on the base die wafer to surround the stack structure, and forming an underfill material layer that includes under-filling portions filling gaps between the core dies, and filling fillet portions covering side surfaces of the core dies. The fillet portions are formed to have a width confined by the partition walls. The partition walls are removed, and a mold layer is formed to cover the fillet portions. Related stack packages are also provided.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member.

Abstract: A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.

Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.

Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.

Abstract: A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.

Abstract: Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.

Abstract: An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

Abstract: An image sensor. Implementations may include: a first die including a plurality of pixels; a second die including a plurality of transistors, capacitors, or both transistors and capacitors; a third die including analog circuitry, logic circuitry, or analog and logic circuitry. The first die may be hybrid bonded to the second die, and the second die may be fusion bonded to the third die. The plurality of transistors, capacitors or transistors and capacitors of the second die may be adapted to enable operation of the plurality of pixels of the first die. The analog circuitry, logic circuitry, and analog circuitry and logical circuitry may be adapted to perform signal routing.

Abstract: Methods and apparatus for an interposer with a dam used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

Abstract: A method for processing a wafer including a plurality of chips is provided. The method may include: forming a trench in the wafer between the plurality of chips; forming a diffusion barrier layer at least over the sidewalls of the trench; forming encapsulation material over the plurality of chips and in the trench; and singularizing the plurality of chips from a side opposite the encapsulation material.

Abstract: In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant.

Abstract: A method of manufacturing a semiconductor device according to one embodiment includes: preparing a semiconductor water which is partitioned into a plurality of first semiconductor chips, the plurality of first semiconductor chips including a first group of first semiconductor chips and a second group of first semiconductor chips; providing a second semiconductor chip over at least one of first semiconductor chips of the first group; providing a sealer on the first semiconductor chips of the second group; and grinding one face of the semiconductor wafer which is on the opposite side from a face on which the second semiconductor chip and the sealer are provided.

Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.

Abstract: A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.

Abstract: The present description relates to the field of fabricating microelectronic packages, wherein a microelectronic device may be attached to a microelectronic substrate with a compensator to control package warpage. The warpage compensator may be a low coefficient of thermal expansion material, including but not limited to silicon or a ceramic material, which is positioned on a land-side of the microelectronic device to counteract the thermal expansion effects of the microelectronic device.

Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.

Abstract: A package apparatus comprises a first conductive wiring layer, a first conductive pillar layer, a dielectric material layer, a second conductive wiring layer, a second conductive pillar layer, and a first molding compound layer. The first conductive wiring layer has a first surface and a second surface opposite to the first surface. The first conductive pillar layer is disposed on the first surface of the first conductive wiring layer, wherein the first conductive wiring layer and the first conductive pillar layer are disposed inside the dielectric material layer. The second conductive wiring layer is disposed on the first conductive pillar layer and the dielectric material layer. The second conductive pillar layer is disposed on the second conductive wiring layer, wherein the second conductive wiring layer and the second conductive pillar layer are disposed inside the first molding compound layer.

Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.

Abstract: A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.

Abstract: A method for mounting and embedding a thinned integrated circuit within a substrate is provided. In one embodiment, the thinned integrated circuit can receive one or more biasing substrate layers on a first surface of the thinned integrated circuit. When the thinned integrated circuit is embedded within a supporting substrate, such as a printed circuit board, the biasing substrate layers can position the thinned integrated circuit toward a centerline of the printed circuit board. Positioning the thinned integrated circuit toward the centerline can increase the resistance to breakage.

Abstract: A method of forming a semiconductor device package includes bonding a first connector to a first conductive structure on a first package. The method includes bonding a die to a surface of the first package, wherein a top surface of the first connector extends above a top surface of the die. The method includes surrounding the first connector with a molding compound. The method includes removing a portion of the first connector and a portion of the molding compound. The top surface of the remaining first conductor is below the top surface of the die. A first top surface of the remaining molding compound is below the top surface of the die. A second top surface of the remaining molding compound is level with the top surface of the die. The method includes bonding a second connector to the remaining portion of the first connector.

Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. In one aspect, the method includes: forming a barrier layer on a base substrate of a mother panel, forming a plurality of display units in units of cell panels on the barrier layer and forming an encapsulation layer on each of the plurality of display units of the cell panels. The method further includes applying an organic film to an interface portion between the cell panels and cutting along the interface portion applied with the organic film. Accordingly, cracks are prevented from occurring in the barrier layer when the mother panel is cut in units of the cell panels, thereby reducing a defect rate of a product and stabilizing its quality.

Abstract: Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.

Abstract: A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad.

Abstract: An embodiment is a method including forming a first package and a second package. The first package includes packaging a first die, forming a plurality of solder balls on the first die, and coating the plurality of solder balls with an epoxy flux. The second package includes forming a first electrical connector, attaching a second die adjacent the first electrical connector, forming a interconnect structure over the first die and the first electrical connector, the interconnect structure being a frontside of the second package, forming a second electrical connector over the interconnect structure, and the second electrical connector being coupled to both the first die and the first electrical connector. The method further includes bonding the first package to the backside of the second package with the plurality of solder balls forming a plurality of solder joints, each of the plurality of solder joints being surrounded by the epoxy flux.

Abstract: A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected.

Abstract: A non-polished glass wafer, a thinning system, and a method for using the non-polished glass wafer to thin a semiconductor wafer are described herein. In one embodiment, the glass wafer has a body (e.g., circular body) including a non-polished first surface and a non-polished second surface substantially parallel to each other. In addition, the circular body has a wafer quality index which is equal to a total thickness variation in micrometers plus one-tenth of a warp in micrometers that is less than 6.0.

Abstract: A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulating layer and semiconductor die while mounted to the carrier. A plurality of second vias is formed through the insulating layer and encapsulant in the same direction as the first vias while the semiconductor die is mounted to the carrier. An electrically conductive material is deposited in the first vias to form conductive TSV and in the second vias to form conductive TMV. A first interconnect structure is formed over the insulating layer and electrically connected to the TSV and TMV. The carrier is removed. A second interconnect structure is formed over the semiconductor die and encapsulant and electrically connected to the TSV and TMV.

Abstract: Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.

Abstract: The stacked package includes: a substrate having an upper surface formed with connection pads, a lower surface, and four side surfaces; a first semiconductor chip mounted over the upper surface of the substrate; a first adhesive member that covers a portion of the substrate including the first semiconductor chip; and a second semiconductor chip formed with bumps on edges of a first surface and mounted over the substrate with interposition of the first semiconductor chip and the first adhesive member such that a center of the first surface is attached over the first adhesive member and the bumps are bonded onto the connection pads, with a second surface opposing to the first surface being polished evenly.

Abstract: The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.

Abstract: Provided herein are electronic devices assembled with thermally insulating layers.

Abstract: Provided herein are electronic devices assembled with thermally insulating layers.

Abstract: A method and structure for stabilizing an array of micro devices is disclosed. A stabilization layer includes an array of stabilization cavities and array of stabilization posts. Each stabilization cavity includes sidewalls surrounding a stabilization post. The array of micro devices is on the array of stabilization posts. Each micro device in the array of micro devices includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Abstract: A stacked wafer structure includes a substrate; dams provided on the substrate and having protrusions on a surface thereof; and a wafer with recesses provided on the dam. The protrusions on the surface of the dams are wedged into the recesses of the wafer, preventing air chambers from forming between the recesses of the wafer and the dams, so that the wafer is not separated from the dams due to the presence of air chambers during subsequent packaging process. A method for stacking a wafer is also provided.

Abstract: A method for producing a semiconductor module includes providing an adhesion carrier and a plurality of circuit carriers. The adhesion carrier has an adhesive upper side and a lower side opposite the adhesive upper side. Each of the circuit carriers includes a ceramic carrier and an upper conductor layer applied to the ceramic carrier, and a circuit carrier lower side. By placing the circuit carriers onto the adhesive upper side, the circuit carrier lower side of the circuit carriers contacts and adheres to the adhesive upper side, so that a quasi-panel is formed, in which the circuit carriers are processed while preserving the quasi-panel and can then be removed from the adhesive upper side.

Abstract: Various embodiments include apparatuses, stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths.

Abstract: 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.