Abstract: A semiconductor package includes a circuit substrate, a semiconductor chip on the circuit substrate, an inner solder ball between the circuit substrate and the semiconductor chip, and dummy solder filling a dummy opening in at least one of an substrate insulation layer of the circuit substrate and a chip insulation layer. The dummy solder does not electrically connect the semiconductor chip with the substrate. The circuit substrate may include a base substrate, a substrate connection terminal on the base substrate, and the substrate insulation layer covering the base substrate. The semiconductor chip may include a chip connection terminal and the chip insulation layer exposing the chip connection terminal. The inner solder ball may be interposed between the substrate connection terminal and the chip connection terminal to electrically connect the circuit substrate to the semiconductor chip.

Abstract: An apparatus includes a dielectric slab having first and opposing second major surfaces. A planar antenna element is located on the first major surface. A via formed through the dielectric slab is conductively connected to the antenna element. A plurality of solder bump pads is located on the second major surface and is configured to attach the dielectric slab to an integrated circuit.

Abstract: A semiconductor device includes: a wiring board which includes a first face and a second face and in which a conductor pattern and a through part are provided; an electronic component which includes an electrode pad forming face where an electrode pad is formed and which is housed in the through part so that the electrode pad forming face is provided on the first face side; a seal resin which is provided in the through part and the electrode pad forming face, seals the electronic component and includes a first plane exposing a connection face of the electrode pad; and a wiring pattern which is provided in the first face of the wiring board and the first plane of the seal resin and electrically connects the connection face of the electrode pad with a first connected face of the conductor pattern, and which includes a pad part.

Abstract: A method comprises forming semiconductor flip chip interconnects where the flip chip comprises a wafer and a substrate having electrical connecting pads and electrically conductive posts operatively associated with the pads and extending away from the pads to terminate in distal ends. Solder bumping the distal ends by injection molding solder onto the distal ends produces a solder bumped substrate. Another embodiment comprises providing the substrate having the posts on the pads with a mask having a plurality of through hole reservoirs and aligning the reservoirs in the mask to be substantially concentric with the distal ends. This is followed by injecting liquid solder into the reservoirs to provide a volume of liquid solder on the distal ends, cooling the liquid solder in the reservoirs to solidify the solder, removing the mask to expose the solidified solder after the cooling and thereby provide a solder bumped substrate.

Abstract: A package assembly comprises a package base, a sensor die, an isolation plate, and a package interface plate. The isolation plate is bonded to the sensor die and has a plurality of flexible beams. Each flexible beam is configured to deflect under stress such that effects on the sensor die of a thermal mismatch between the package base and the sensor die are reduced. The package interface plate is bonded to the isolation plate and the package base. The package interface plate is configured to limit the maximum distance each flexible beam is able to deflect.

Abstract: This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact.

Abstract: The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure.

Abstract: A semiconductor device has a semiconductor chip and a first interconnection tape. The semiconductor chip has a plurality of first electrode pads arranged on a first surface. The first interconnection tape is in contact with each of the plurality of first electrode pads such that the plurality of first electrode pads are electrically connected with each other.

Abstract: A manufacturing method for a mounting structure of a semiconductor package component, including: applying a first adhesive with viscosity ?1 and a thixotropy index T1 at a position on the substrate, which is on an outer side of the mounted semiconductor package component; applying, on the first adhesive, a second adhesive with viscosity ?2 and a thixotropy index T2 so that the second adhesive gets in contact with an outer periphery part of the semiconductor package component; and forming, through a subsequent reflow process, a first adhesive part of the hardened first adhesive and a second adhesive part of the hardened second adhesive, wherein the first and second adhesives satisfy 30??2??1?300 (Pa·s) and 3?T2?T1?7, and sectional area S1 of the first adhesive part and sectional area S2 of the second adhesive part with respect to a direction perpendicular to a mounting surface of the substrate satisfy a relation S1?S2.

Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.

Abstract: A method includes placing a mold chase over a bottom package, wherein the bottom package has a connector at a top surface of the bottom package. The mold chase includes a cover, and a pin under and connected to the cover. The pin occupies a space extending from a top surface of the connector to the cover. A polymer is filled into a space between the cover of the mold chase and the bottom package. The polymer is then cured. After the step of curing the polymer, the mold chase is removed, and the connector is exposed through an opening in the polymer, wherein the opening is left by the pin of the mold chase.

Abstract: The present invention relates to an interconnect substrate with an embedded device, a built-in stopper and dual build-up circuitries and a method of making the same. In accordance with one preferred embodiment of the present invention, the method includes: forming a stopper on a dielectric layer; mounting a semiconductor device on the dielectric layer using the stopper as a placement guide for the semiconductor device; attaching a stiffener to the dielectric layer; forming a first build-up circuitry and a second build-up circuitry that cover the semiconductor device, the stopper and the stiffener at both sides; and providing a plated through-hole that provides an electrical connection between the first and second build-up circuitries. Accordingly, the stopper can accurately confine the placement location of the semiconductor device and avoid the electrical connection failure between the semiconductor device and the build-up circuitry.

Abstract: The present invention relates to a thermally enhanced interconnect substrate and a method of making the same. In accordance with one preferred embodiment, the method includes: forming a stopper on a metal layer of a laminate substrate; removing a selected portion of the metal layer to form a paddle layer; mounting a semiconductor device on the paddle layer using the stopper as a placement guide for the semiconductor device; attaching a stiffener to the laminate substrate; forming first and second build-up circuitries that cover the semiconductor device, the paddle layer and the stiffener at both sides; and providing a plated through-hole that provides an electrical connection between the first and second build-up circuitries. Accordingly, the paddle layer can provide excellent heat spreading, and the stopper can accurately confine the placement location of the semiconductor device and avoid the electrical connection failure between the semiconductor device and the build-up circuitry.

Abstract: A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

Abstract: A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.

Abstract: To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device. A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.

Abstract: In one embodiment, a lead frame package structure includes a lead frame having sides that surround a die paddle and on which a plurality of leads are formed. An electronic chip is attached to the die paddle and a case is attached to the lead frame to seal the leads and the electronic chip. One or more discharge holes are formed on and extending through one or more specific leads and/or on and extending through a predetermined position of the die paddle. The discharge holes are configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the packaged electronic chip.

Abstract: A semiconductor package is provided, which includes: a soft layer having opposite first and second surfaces and first conductive through hole vias; a chip embedded in the soft layer and having an active surface exposed from the first surface of the soft layer; a support layer formed on the second surface of the soft layer and having second conductive through hole vias in electrical connection with the first conductive through hole vias; a first RDL structure formed on the first surface of the soft layer and electrically connected to the active surface of the chip; and a second RDL structure formed on the support layer and electrically connected to the first RDL structure through the first and second conductive through hole vias. The invention prevents package warpage by providing the support layer, and allows disposing of other packages or electronic elements by electrically connecting the RDL structures through the conductive through hole vias.

Abstract: A method for bonding a first copper element onto a second copper element including forming a crystalline copper layer enriched in oxygen on each of surfaces of each of the first and second elements through which the elements will be in contact, the total thickness of both layers being less than 6 nm, which includes: a) polishing the surfaces so as to obtain a roughness of less than 1 nm RMS, and hydrophilic surfaces, b) cleaning the surfaces to suppress presence of particles due to the polishing and the major portion of corrosion inhibitors, and c) putting both crystalline copper layer enriched in oxygen in contact with each other.

Abstract: A method for temporary wafer bonding employs a curable adhesive composition and a degradation agent combined with the curable adhesive composition. The adhesive composition may include (A) a polyorganosiloxane containing an average of at least two silicon-bonded unsaturated organic groups per molecule, (B) an organosilicon compound containing an average of at least two silicon-bonded hydrogen atoms per molecule in an amount sufficient to cure the composition, (C) a catalytic amount of a hydrosilylation catalyst, and (D) a base. The film prepared by curing the composition is degradable and removable by heating.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of first integrated circuits on the surface side of a first semiconductor substrate; forming a plurality of second integrated circuits in a semiconductor layer that is formed on a release layer provided on a second semiconductor substrate; bonding the two semiconductor substrates so that electrically bonding portions are bonded to each other to form a bonded structure; separating the second semiconductor substrate from the bonded structure at the release layer to transfer, to the first semiconductor substrate, the semiconductor layer in which the plurality of second integrated circuits are formed; and dicing the first semiconductor substrate to obtain stacked chips each including the first integrated circuit and the second integrated circuit.

Abstract: The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device.

Abstract: An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board. A method of fabricating an integrated circuit assembly includes coupling a handle wafer to the active layer of a semiconductor-on-insulator wafer, removing the substrate of the semiconductor-on-insulator, forming a bond pad connecting to the active layer on the exposed insulator surface, bonding the bond pad to a printed circuit board using a solder bump, and removing the handle wafer.

Abstract: An embodiment is a package-on-package (PoP) device comprising a first package on a first substrate and a second package over the first package. A plurality of wire sticks disposed between the first package and the second package and the plurality of wire sticks couple the first package to the second package. Each of the plurality of wire sticks comprise a conductive wire of a first height affixed to a bond pad on the first substrate and each of the plurality of wire sticks is embedded in a solder joint.

Abstract: Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

Abstract: Encapsulated radio frequency identification (RFID) articles having enhanced break strength and/or temperature resistance and methods of making these articles. The RFID articles include an RFID tag embedded within a thermoplastic substrate to form the RFID article. In one embodiment, the RFID article includes an over-molded barrier material that enables the RFID article to have enhanced temperature resistance such that the articles are able top sustain repeated exposure to high temperatures and/or sterilization procedures, thereby enabling the RFID articles to be utilized in applications heretofore unavailable. In other embodiments, the RFID articles are made using an injection molding process that provides very thin encapsulated RFID tags that also exhibit an increased level of temperature resistance.

Abstract: A technique to fabricate a package. A thin wafer supported by a wafer support substrate (WSS) is formed. The WSS-supported thin wafer layer is diced into a plurality of WSS-supported thin dice. A WSS-supported thin die is bonded to a first heat spreader (HS) to form a HS-reinforced thin die.

Abstract: Organic-adhesive tapes are often used to secure and protect the bumps during wafer processing after bump formation. While residual organic-adhesive tape may remain on the wafer after tape de-lamination, applying a bump template layer on the bumps before laminating the tape allows any residue to be removed afterwards and results in a residue-free wafer.

Abstract: A method of forming, on a surface of a substrate, at least one hydrophilic attachment area for the purpose of self-assembling a component or a chip, in which a hydrophobic area, which delimits the hydrophilic attachment area, is produced.

Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.

Abstract: There is reduced the difference in inductance between bonding wires to be coupled to two semiconductor chips stacked one over another. A semiconductor device includes external terminals, lower and upper semiconductor chips, and first and second bonding wires. The lower semiconductor chip has first bonding pads, and the upper semiconductor chip has second bonding pads. The first bonding wire couples the first bonding pad of the lower semiconductor chip and the external terminal, and the second bonding wire couples the second bonding pad of the upper semiconductor chip and the external terminal. The diameter of the second bonding wire is larger than the diameter of the first bonding wire.

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract: Provided is a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package body including a plurality of sheets; semiconductor chips mounted in the package body; and an external connection terminal provided on a first side of the package body, wherein the sheets are stacked in a parallel direction to the first side.

Abstract: Integrated circuit structures and methods are provided. According to an embodiment, a circuit structure includes a die and an anisotropic conducting film (ACF). The die comprises a through via, and the through via protrudes from a surface of the die. A cross-sectional area of the through via in the surface of the die is equal to a cross-sectional area of a protruding portion of the through via in a plane parallel to the surface of the die. The ACF adjoins the surface of the die, and the protruding portion of the through via penetrates the ACF.

Abstract: An adhesive includes an epoxy resin and a hardener. The hardener includes trioxdiamine, diaminodicyclohexylmethane, toluene diamine, and bisphenol-A dianhydride.

Abstract: To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.

Abstract: An adhesive/spacer structure (52, 52A, 60) is used to adhere first and second die (14, 18) to one another at a chosen separation in a multiple-die semiconductor chip package (56). The first and second die define a die bonding region (38) therebetween. The adhesive/spacer structure may comprise a plurality of spaced-apart adhesive/spacer islands (52, 52A) securing the first and second die to one another at a chosen separation (53). The adhesive/spacer structure may also secure the first and second die to one another to occupy about 1-50% of the die bonding region.

Abstract: A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.

Abstract: A semiconductor device has a semiconductor die mounted over a surface of a substrate. A mold underfill dispensing needle has a width substantially equal to a width of the semiconductor die. The dispensing needle is placed in fluid communication with a side of the semiconductor die. A mold underfill is deposited from an outlet of the dispensing needle evenly across a width of the semiconductor die into an area between the semiconductor die and substrate without motion of the dispensing needle. The dispensing needle has a shank and the outlet in a T-configuration. The dispensing needle can have a plurality of pole portions between a shank and the outlet. The dispensing needle has a plate between a shank and the outlet. The outlet has an upper edge with a length substantially equal to or greater than a length of a lower edge of the outlet.

Abstract: A method for producing an encapsulating layer-covered semiconductor element includes the steps of preparing a support sheet including a hard support board; disposing a semiconductor element at one side in a thickness direction of the support sheet; disposing an encapsulating layer formed from an encapsulating resin composition containing a curable resin at the one side in the thickness direction of the support sheet so as to cover the semiconductor element; curing the encapsulating layer to encapsulate the semiconductor element by the encapsulating layer that is flexible; cutting the encapsulating layer that is flexible corresponding to the semiconductor element to produce an encapsulating layer-covered semiconductor element; and peeling the encapsulating layer-covered semiconductor element from the support sheet.

Abstract: A resin sealing method for a plurality of semiconductor chips. The resin sealing method includes a chip holding sheet attaching step of attaching a chip holding sheet through an adhesive ring to a support substrate, a semiconductor chip attaching step of attaching the front side of each semiconductor chip to an adhesive layer constituting the chip holding sheet in an area corresponding to the inside of the adhesive ring, a resin sealing step of sealing all of the semiconductor chips with a mold resin, a support substrate removing step of removing the support substrate from the chip holding sheet on which the semiconductor chips are attached and sealed with the mold resin, and a chip holding sheet peeling step of peeling the chip holding sheet from the front side of each semiconductor chip sealed with the mold resin.

Abstract: A method for manufacturing a chip package is provided, the method including: forming a layer arrangement over a carrier; arranging a chip including one or more contact pads over the layer arrangement wherein the chip covers at least part of the layer arrangement; and selectively removing one or more portions of the layer arrangement and using the chip as a mask such that at least part of the layer arrangement covered by the chip is not removed.

Abstract: A semiconductor device manufacturing method is provided. First and second semiconductor chips are prepared, including first and second electrodes on first and second surfaces respectively. The second semiconductor chip includes a third electrode on a third surface opposite to the second surface. The third electrode overlaps the second electrode. The second surface includes an electrode-free region that is free of any electrode. A sealing resin is applied on the first surface of the first semiconductor chip. A second surface of the first semiconductor chip is held by a bonding tool including a pressing surface and a supporting-portion projected from the pressing surface. The pressing surface is made into contact with the second electrode. The supporting-portion is arranged at a position facing the electrode-free region. The second semiconductor chip is stacked over the first semiconductor chip by the bonding tool to electrically connect the third electrode to the first electrode.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of first integrated circuits on the surface side of a first semiconductor substrate; forming a plurality of second integrated circuits in a semiconductor layer that is formed on a release layer provided on a second semiconductor substrate; bonding the two semiconductor substrates so that electrically bonding portions are bonded to each other to form a bonded structure; separating the second semiconductor substrate from the bonded structure at the release layer to transfer, to the first semiconductor substrate, the semiconductor layer in which the plurality of second integrated circuits are formed; and dicing the first semiconductor substrate to obtain stacked chips each including the first integrated circuit and the second integrated circuit.

Abstract: A communication system front-end architecture and a method of fabricating same are disclosed in which a diverse set of semiconductor technologies and device types (including CMOS, SiGe CMOS, InP HBTs (heterojunction bipolar transistors), InP HEMTs (high electron mobility transistors), GaN HEMTs, SiC devices, any number from a diverse set of MEMS sensors and actuators, and potentially photonics) is merged onto a single silicon, or other material substrate to thereby enable the development of smaller, lighter, and higher performance systems.

Abstract: An electric device and a method of making an electric device are disclosed. In one embodiment the electric device comprises a component comprising a component contact area and a carrier comprising a carrier contact area. The electric device further comprises a first conductive connection layer connecting the component contact area with the carrier contact area, wherein the first conductive connection layer overlies a first region of the component contact area and a second connection layer connecting the component contact area with the carrier contact area, wherein the second connection layer overlies a second region of the component contact area, and wherein the second connection layer comprises a polymer layer.

Abstract: A wiring method for a semiconductor integrated circuit has the steps of, separately from a first layer on which a first signal wiring pattern is mainly formed, laying out a first power-supply wiring pattern on a second layer so that a plurality of rows of the first power-supply wiring pattern are regularly arranged with vacant areas each interposed between the rows and making narrower a width of each vacant area than a narrowest width of a row among the rows of the first power-supply wiring pattern, and laying out a second signal wiring pattern electrically conductive to the first layer in two or more rows of the vacant areas on the second layer so that the second signal wiring pattern is not in contact with adjacent rows of the first power-supply wiring pattern on both sides.

Abstract: Provided is a component bonding method of bonding a semiconductor component having a thermosetting adhesive layer formed on a lower surface thereof to a circuit board having a resin layer formed on a surface thereof. In the method, wettability is improved by surface modification that performs a plasma treatment on a resin surface of the circuit board, the semiconductor component is held by a component holding nozzle having a heater, the adhesive layer is contacted to the surface-modified resin layer, and the adhesive layer is heated and thermally cured by the heater. Thereby, adhesion between the adhesive layer and the resin surface is improved, and thus the component holding nozzle can be separated from the semiconductor component without wait for completely hardening the adhesive layer. Accordingly, it is possible to improve productivity in the heat pressing process by reducing the time required for the component bonding.

Abstract: A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member.