Including Adhesive Bonding Step Patents (Class 438/118)
  • Publication number: 20130196472
    Abstract: A method for preparing a semiconductor with preapplied underfill comprises (a) providing a thinned silicon semiconductor wafer having a plurality of metallic bumps on its active face and, optionally, through-silica-vias vertically through the silicon semiconductor wafer; (b) providing an underfill material on a dicing support tape, in which the underfill material is precut to the shape of the semiconductor wafer; (c) aligning the underfill material on the dicing support tape with the semiconductor wafer and laminating the underfill material to the semiconductor wafer.
    Type: Application
    Filed: March 13, 2013
    Publication date: August 1, 2013
    Applicant: HENKEL CORPORATION
    Inventor: HENKEL CORPORATION
  • Publication number: 20130196471
    Abstract: A method includes providing a pad chip having contact pads, providing a spring chip having micro-springs, applying a chemical activator to one of either the pad chip or the spring chip, applying an adhesive responsive to the chemical activator on the other of the pad chip or the spring chip, aligning the pad chip to the spring chip such that the micro-springs will contact the contact pads, and pressing the pad chip and the spring chip together such that the chemical activator at least partially cures the adhesive.
    Type: Application
    Filed: March 13, 2013
    Publication date: August 1, 2013
    Applicant: Palo Alto Research Center Incorporated
    Inventor: Palo Alto Research Center Incorporated
  • Publication number: 20130193530
    Abstract: A semiconductor component includes a substrate, a molded package, and a semiconductor chip. The semiconductor chip is suspended on the molding compound above the substrate in the molded package in such a way that a cavity mechanically decouples the semiconductor chip from the substrate. The cavity extends along an underside facing the substrate.
    Type: Application
    Filed: December 20, 2010
    Publication date: August 1, 2013
    Applicant: ROBERT BOSCH GMBH
    Inventor: Ricardo Ehrenpfordt
  • Publication number: 20130193566
    Abstract: An integrated circuit shielding film and a manufacturing method thereof. The manufacturing method provides a plate. A stripping glue is coated on the plate. An integrated circuit is disposed on the stripping glue and the stripping glue is deposited on the surface of the integrated circuit. A shielding film is then formed on the integrated circuit by coating operations.
    Type: Application
    Filed: September 12, 2012
    Publication date: August 1, 2013
    Applicant: CHENMING MOLD IND. CORP.
    Inventors: Chuan-Li Cheng, Hsueh-Tsu Chang
  • Patent number: 8497163
    Abstract: A semiconductor substrate and a copper sheet stacked with an insulating resin layer are bonded together at a temperature of 130° C. or below (first temperature) so that an element electrode provided on the semiconductor substrate connects to the copper sheet before a thinning process. Then the semiconductor substrate and the copper sheet, on which the insulating resin layer has been stacked, are press-bonded at a high temperature of 170° C. or above (second temperature) with the copper sheet thinned to thickness of a wiring layer. Then the wiring layer (rewiring) is formed by patterning the thinned copper sheet.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: July 30, 2013
    Inventors: Koichi Saito, Yoshio Okayama, Yasuyuki Yanase
  • Patent number: 8497162
    Abstract: Various methods of attaching a lid to an integrated circuit substrate are provided. In one aspect, a method of attaching a lid to a substrate that has an integrated circuit positioned thereon is provided. An adhesive is applied to the substrate and an indium film is applied to the integrated circuit. The lid is positioned on the adhesive. The adhesive is partially hardened and the indium film is reflowed. The adhesive is cured.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: July 30, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seah Sun Too, Maxat Touzelbaev, Janet Kirkland
  • Patent number: 8492203
    Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: July 23, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Yu Gu, Wei Meng, Chee Siang Ong
  • Patent number: 8492784
    Abstract: A semiconductor device includes: a semiconductor chip including a nitride semiconductor layered structure including a carrier transit layer and a carrier supply layer; a first resin layer on the semiconductor chip, the first resin layer including a coupling agent; a second resin layer on the first resin layer, the second resin layer including a surfactant; and a sealing resin layer to seal the semiconductor chip with the first resin layer and the second resin layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 23, 2013
    Assignee: Fujitsu Limited
    Inventors: Keishiro Okamoto, Tadahiro Imada, Nobuhiro Imaizumi, Keiji Watanabe
  • Patent number: 8492199
    Abstract: The present invention provides chip containing electronic devices such as Multichip Ceramic Modules (MCM's) containing a plurality of chips on a substrate which chips are underfilled with a reworkable composition which allows one or more chips to be removed from the device and replaced. The reworkable compositions contain a base resin which is not cross-linkable and which forms a matrix with a linear curable component or preferably a combination of linear curable components which curable components are cross-linkable and when cured form a cross-linked domain in the base resin matrix. A suitable cross-linking catalyst such as Pt is used and optionally a filler preferably silane surface treated silica. The preferred base resin is linear polydimethylsiloxane and the preferred curable components are vinyl terminated linear poly dimethyl siloxane and hydrogen terminated linear poly dimethyl siloxane.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey T. Coffin, Steven P. Ostrander, Frank L. Pompeo, Jiali Wu
  • Patent number: 8492907
    Abstract: The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film having a light transmittance at a wavelength of 532 nm or 1064 nm of 20% or less, and having a contrast between a marking part and a part other than the marking part after laser marking of 20% or more.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: July 23, 2013
    Assignee: Nitto Denko Corporation
    Inventors: Naohide Takamoto, Goji Shiga, Fumiteru Asai
  • Patent number: 8492181
    Abstract: A method of forming an embedded wafer level optical package includes attaching a sensor die, PCB bars and an LED on adhesive tape laminated on a carrier, attaching a dam between two light sensitive sensors of the sensor die, encapsulating the sensor die, the PCB bars, the LED, and the dam in an encapsulation layer, debonding the carrier, grinding a top surface of the encapsulation layer, forming vias through the encapsulation layer to the sensor die and the LED, filling the vias with conductive material, metalizing the top surface of the encapsulation layer, dielectric coating of the top surface of the encapsulation layer, dielectric coating of a bottom surface of the encapsulation layer, patterning the dielectric coating of the bottom surface of the encapsulation layer, and plating the patterned dielectric coating of the bottom surface of the encapsulation layer.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: July 23, 2013
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Anandan Ramasamy, KahWee Gan, Hk Looi, David Gani
  • Publication number: 20130183800
    Abstract: A circuit board structure and a fabrication method thereof are disclosed. The circuit board structure includes a carrying board having a first and an opposite second surface and having at least one through cavity formed therein; a semiconductor chip disposed in the through cavity of the carrying board; an adhesive material filling the gap between the through cavity of the carrying board and the semiconductor chip to fix the semiconductor chip in the through cavity; and a reinforcing layer disposed on the second surface of the carrying board and the inactive surface of the semiconductor chip, thereby increasing the strength of the carrying board as well as the reliability of the circuit board.
    Type: Application
    Filed: February 11, 2013
    Publication date: July 18, 2013
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventor: UNIMICRON TECHNOLOGY CORP.
  • Publication number: 20130183799
    Abstract: Provided is a method for manufacturing a semiconductor device, which includes: preparing a semiconductor wafer; and peeling off an adhesive layer from the semiconductor wafer. The prepared semiconductor wafer includes at least one semiconductor chip having a bump electrode group formed by arraying bump electrodes in a matrix, and the adhesive layer formed on one surface having the bump electrodes. The bump electrode group is formed by arraying the bump electrodes so that the number of bump electrodes in a second direction can be smaller than that in a first direction. To peel off the adhesive layer from the semiconductor wafer, the adhesive layer is peeled off from the semiconductor wafer along the first direction from one end side of the semiconductor wafer.
    Type: Application
    Filed: May 9, 2012
    Publication date: July 18, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Jun SASAKI, Tadashi KOYANAGI
  • Patent number: 8486744
    Abstract: The present disclosure provides a method for fabricating a MEMS device including multiple bonding of substrates. In an embodiment, a method includes providing a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, providing a semiconductor substrate including a second bonding layer, and providing a cap including a third bonding layer. The method further includes bonding the MEMS substrate to the semiconductor substrate at the first and second bonding layers, and bonding the cap to the semiconductor substrate at the second and third bonding layers to hermetically seal the MEMS substrate between the cap and the semiconductor substrate. A MEMS device fabricated by the above method is also provided.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: July 16, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsien Lin, Chia-Hua Chu, Li-Cheng Chu, Yuan-Chih Hsieh, Chun-Wen Cheng
  • Patent number: 8486212
    Abstract: An electronic component mounting apparatus is capable of significantly reducing a warpage amount of an electronic component warped in a case of thermocompression bonding using a conductive adhesive agent having conductive particles and a low minimum melt viscosity where a thin electronic component having a thickness smaller than or equal to 200 ?m is mounted on a wiring board. In the mounting apparatus, an anisotropic conductive adhesive film having the minimum melt viscosity lower than or equal to 1.0×103 Pa·s is placed on a wiring board placed on a base, and an IC chip having a thickness smaller than or equal to 200 ?m is placed on the anisotropic conductive adhesive film. In the mounting apparatus, the IC chip is pressurized by a thermocompression bonding head having a compression bonding portion made of elastomer having a rubber hardness lower than or equal to 60, so that the IC chip is bonded onto the wiring board by thermocompression.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: July 16, 2013
    Assignee: Dexerials Corporation
    Inventor: Kazunori Hamazaki
  • Patent number: 8487424
    Abstract: An integrated circuit assembly is fabricated on a metal substrate strip in an array format that has raised circuitry pattern formed by photolithographic and metal etching processes. The circuitry pattern is formed on one side of the metal substrate only. The raised circuitry's etch depth extends partially through the metal substrate. Die attachment can be performed using a non-conductive material applied directly onto and around the raised circuitry features directly under the die. After wirebond and molding processes, the molded metal substrate strip assembly is processed through a metal etching process to remove the metal substrate portion that is exposed beyond the mold cap. A solder mask coating can be applied to protect the metal circuitry and to define the package pad opening to form Land-Grid-Array (LGA) packages. Solder balls can also be attached to form Ball-Grid-Array (BGA) packages.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: July 16, 2013
    Assignee: ATMEL Corporation
    Inventor: Ken Lam
  • Patent number: 8487434
    Abstract: A method for manufacturing an integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and the base interconnect; and forming a re-routing film over the encapsulant, the base device, and the base interconnect for connectivity without a substrate.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: July 16, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Heap Hoe Kuan, Seng Guan Chow, Rui Huang
  • Patent number: 8481342
    Abstract: A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: July 9, 2013
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Tomohiko Sagimori, Takahito Suzuki, Masataka Muto
  • Patent number: 8481369
    Abstract: A no-lead type semiconductor package is formed by attaching a die to a top surface of a flag of a lead frame and then taping a bottom surface of the flag and leads of the lead frame. Die bonding pads are connected to the leads with wires and then the assembly is put in a mold chase and encapsulated with a plastic material. The mold chase has protrusions between the flag and the leads of a lead frame, and between the leads themselves, which causes indentations to be formed between the leads and between the flag and the leads. The method is particularly useful for making quad flat no lead (QFN) devices and power-QFN type devices.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: July 9, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Junhua Luo, Xingshou Pang, Jinzhong Yao
  • Patent number: 8481861
    Abstract: A die having a base formed of a first material is connected to a board having a base formed of a second material. An interposer having a coefficient of thermal expansion intermediate coefficients of thermal expansion of the first and second materials is positioned between the die and the board.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: July 9, 2013
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Robert C. Cooney, Joseph M. Wilkinson
  • Patent number: 8481370
    Abstract: The present invention provides a semiconductor device having a structure that can be mounted on a wiring substrate, as for the semiconductor device formed over a thin film-thickness substrate, a film-shaped substrate, or a sheet-like substrate. In addition, the present invention provides a method for manufacturing a semiconductor device that is capable of raising a reliability of mounting on a wiring substrate. One feature of the present invention is to bond a semiconductor element formed on a substrate having isolation to a member that a conductive film is formed via a medium having an anisotropic conductivity.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: July 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuo Nishi, Hiroki Adachi, Naoto Kusumoto, Yuusuke Sugawara, Hidekazu Takahashi, Daiki Yamada, Yoshikazu Hiura
  • Publication number: 20130168850
    Abstract: Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.
    Type: Application
    Filed: January 3, 2012
    Publication date: July 4, 2013
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Arkadii V. Samoilov, Tyler Parent, Larry Y. Wang
  • Publication number: 20130168852
    Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.
    Type: Application
    Filed: August 9, 2012
    Publication date: July 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Chih Liang, Chia-Hua Chu, Te-Hao Lee, Jiou-Kang Lee, Chung-Hsien Lin
  • Patent number: 8476740
    Abstract: To provide a semiconductor wafer surface protection sheet having good adhesion to irregularities on a patterned surface of a semiconductor wafer and having good peelability after wafer grinding. Specifically, a semiconductor wafer surface protection sheet is provided that includes a base layer having a tensile elasticity at 25° C., E(25), of 1 GPa or more; a resin layer A that satisfies the condition EA(60)/EA(25)<0.1, where EA(25) is a tensile elasticity at 25° C. and EA(60) is a tensile elasticity at 60° C., the EA(60) ranging from 0.005 MPa to 1 MPa; and a resin layer B having a tensile elasticity at 60° C., EB(60), of 1 MPa or more and having a thickness of 0.1 ?m to less than 100 ?m, the EB(60) being larger than the EA(60) of the resin layer A.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: July 2, 2013
    Assignee: Mitsui Chemicals Tohcello, Inc.
    Inventors: Eiji Hayashishita, Yoshihisa Saimoto, Makoto Kataoka, Katsutoshi Ozaki, Mitsuru Sakai
  • Patent number: 8476751
    Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: July 2, 2013
    Assignee: SK Hynix Inc.
    Inventors: Kyu Won Lee, Cheol Ho Joh, Eun-Hye Do, Ji Eun Kim, Hee Min Shin
  • Patent number: 8476115
    Abstract: A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: July 2, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: DaeSik Choi, Sang Mi Park, KyungHoon Lee
  • Patent number: 8476720
    Abstract: A sensing unit package with reduced size and improved thermal sensing capabilities. An exemplary package includes a printed circuit board with a plurality of electrical traces, an application-specific integrated circuit (Analog ASIC) chip, and a micromachined sensor formed on a microelectromechanical system (MEMS) die. The Analog ASIC chip is electrically and mechanically attached to the printed circuit board. The MEMS die is in direct electrical communication with only a portion of the electrical traces of the printed circuit board and is mechanically and thermally attached directly to the Analog ASIC chip. A thermally conducting compound is located between the MEMS die and the Analog ASIC chip. One or more solder balls electrically attach the Analog ASIC chip to the printed circuit board and one or more solder traces electrically attach the MEMS die to the printed circuit board.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: July 2, 2013
    Assignee: Honeywell International Inc.
    Inventor: Chia-Ming Liu
  • Publication number: 20130161837
    Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.
    Type: Application
    Filed: June 7, 2012
    Publication date: June 27, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Yin Chen, Yu-Ching Liu, Yueh-Chiung Chang, Yu-Po Wang
  • Publication number: 20130154090
    Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.
    Type: Application
    Filed: February 15, 2013
    Publication date: June 20, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventor: STATS ChipPAC, Ltd.
  • Publication number: 20130157416
    Abstract: A method and structure for a semiconductor device, the device including a handle wafer, a diamond layer formed directly on a front side of the handle wafer, and a thick oxide layer formed directly on a back side of the handle wafer, the oxide of a thickness to counteract tensile stresses of the diamond layer. Nitride layers are formed on the outer surfaces of the diamond layer and thick oxide layer and a polysilicon is formed on outer surfaces of the nitride layers. A device wafer is bonded to the handle wafer to form the semiconductor device.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 20, 2013
    Applicant: INTERSIL AMERICAS INC.
    Inventor: INTERSIL AMERICAS INC.
  • Publication number: 20130154091
    Abstract: A semiconductor device package having an embedded three-dimensional interconnect structure and a process for making such a package is provided. One or more ball conductors are attached to a major surface of a substrate that provides at least an electrical conduit from the ball conductor to an opposite major surface of the substrate. The substrate can also provide an interconnect between solder balls. The combination of solder balls and substrate is encapsulated in the semiconductor device package. The ends of the signal conduits are exposed on one major surface of the device package, while a portion of the ball conductors is exposed on the opposite major surface of the device package. The ball conductors and signal conduits provide signal-bearing pathways between the major surfaces of the package. Contacts created by the back grinded ball conductors are used to form a package-on-package structure by coupling with contacts from another package.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Inventors: Jason R. Wright, Zhiwei Gong, Scott M. Hayes, Douglas G. Mitchell
  • Patent number: 8466539
    Abstract: A method of assembling a magnetoresistive random access memory (MRAM) device includes providing a substrate having an opening. A tape is applied to a surface of the substrate and a first magnetic shield is placed onto the tape and within the substrate opening. An adhesive is applied between the first magnetic shield and the substrate to attach the first magnetic shield to the substrate. An MRAM die is attached to the first magnetic shield and bond pads of the MRAM die are connected to pads on the substrate with wires. A second magnetic shield is attached to a top surface of the MRAM die. An encapsulating material is dispensed onto the substrate, the MRAM die, the second magnetic shield and part of the first magnetic shield, cured, and then the tape is removed. Solder balls then may be attached to the substrate.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 18, 2013
    Assignee: Freescale Semiconductor Inc.
    Inventors: Jun Li, Jianhong Wang, Xuesong Xu, Jinzhong Yao, Wanming Yu
  • Publication number: 20130149817
    Abstract: A fabricating method of a semiconductor device may include forming a semiconductor die on a supporting wafer, and picking up the die from the wafer by attaching to the die a transfer unit, the transfer unit including a head unit configured to enable twisting movement, and performing the twisting movement. A fabricating method of a semiconductor device may include forming a first semiconductor device on a supporting wafer; and picking up the first semiconductor device from the wafer, moving the first semiconductor device onto a second semiconductor device, and bonding the first semiconductor device to the second semiconductor device while maintaining the first semiconductor device oriented so that a surface faces upwardly. A fabricating method of a semiconductor device may include forming a first semiconductor device on a supporting wafer, attaching to the first semiconductor device a transfer unit configured to enable twisting movement, and performing the twisting movement.
    Type: Application
    Filed: July 26, 2012
    Publication date: June 13, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Seong JEON, Sang-Sick PARK, Sang-Wook PARK, Teak-Hoon LEE, Kwang-Chul CHOI
  • Publication number: 20130147024
    Abstract: An integrated circuit package structure includes a bottom portion having a cavity, an integrated circuit attached to a top surface of the stepped cavity, a leadframe attached to the bottom portion, wire bonding for electrically coupling the integrated circuit to the leadframe, and a top portion conformally covering the integrated circuit and the bottom portion.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: STMicroelectronics PTE Ltd.
    Inventors: Kim-Yong GOH, Xueren Zhang, Wingshenq Wong
  • Patent number: 8461688
    Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: June 11, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
  • Publication number: 20130143362
    Abstract: A technique comprising: mounting a device substrate on a processing support, forming one or more electronic elements on the device substrate with the device substrate thus mounted on the processing support; wherein the device substrate comprises an organic support structure, and provides primary protection for the overlying electronic elements against the ingress of a degrading species from a side of the device substrate opposite to the one or more electronic elements.
    Type: Application
    Filed: June 3, 2011
    Publication date: June 6, 2013
    Applicant: PLASTIC LOGIC LIMITED
    Inventors: Kieran Reynolds, Jerome Joimel
  • Publication number: 20130140693
    Abstract: A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 ?m, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.
    Type: Application
    Filed: November 28, 2012
    Publication date: June 6, 2013
    Applicant: STMicroelectronics S.A.
    Inventor: STMicroelectronics S.A.
  • Publication number: 20130143363
    Abstract: An adhesive film for a semiconductor may include about 60 wt % to about 80 wt % of a thermoplastic resin based on a total solid content of the adhesive film, a phenolic curing agent, and an amine curing agent, and the adhesive film may have a storage modulus of about 2 MPa or more and a reaction curing rate of about 50% or more when cured at 150° C. for 20 minutes.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 6, 2013
    Inventors: Sang Jin KIM, Kyoung Tae WI, Jae Won CHOI, Sang Kyun KIM, Cheol Su KIM
  • Publication number: 20130140713
    Abstract: The present disclosure relates to a method for fast and precise alignment and mounting of a top die onto an interposer wafer. The method is performed by applying a hydrophobic self assembled monolayer to a carrier wafer in a pattern defining a top die placement region correlating to an arrangement of a top die on an interposer wafer. A liquid is provided into the top die placement region and a top die is placed into contact with the liquid. The surface tension of the liquid automatically aligns the top die by generating a force causing the top die to overlap with the top die placement region. The liquid is then eliminated and the top die is affixed to the carrier wafer. The carrier wafer is bonded to the interposer wafer, bringing the top die into contact with an interposer.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: Taiwan Semiconductro Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chien-Chia Chiu, Cheng-Chieh Hsieh
  • Patent number: 8455990
    Abstract: A barrier layer can be attached in a semiconductor package to one or more sensitive devices. The barrier layer can be used to obstruct tampering by a malicious agent attempting to access sensitive information on the sensitive device. The barrier layer can cause the sensitive device to become inoperable if physically tampered. Additional other aspects of the protective packaging provide protection against x-ray and thermal probing as well as chemical and electrical tampering attempts.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: June 4, 2013
    Assignee: Conexant Systems, Inc.
    Inventors: Robert W Warren, Hyun Jung Lee, Nic Rossi
  • Patent number: 8456307
    Abstract: A method of producing a sheet 1 with IC tags comprises the steps of: preparing and feeding a sheet 21a with electrical conductors formed thereon; providing an adhesive 18 on the sheet 21a with electrical conductors; preparing multiple IC chips 20 and successively feeding the IC chips 20; successively arranging each IC chip 20 on the electrical conductors 22 of the sheet 21a; and fixing each IC chip 20 onto the electrical conductors 22 through the adhesive 18. The sheet 21a with electrical conductors formed thereon includes a non-conductive sheet 21 and a pair of electrical conductors 22. The pair of electrical conductors 22 of the sheet 21a with the electrical conductors are provided on the non-conductive sheet 21, extend in the feed direction, and are spaced apart from each other.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: June 4, 2013
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Hiroshi Suguro, Hideto Sakata, Terunao Tsuchiya, Takaichi Shimomura
  • Patent number: 8456008
    Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: June 4, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Cheng Kuo, Kai-Ming Ching, Chen Chen-Shien
  • Patent number: 8455991
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: June 4, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Yung Kuan Hsiao, Xusheng Bao, Kang Chen, Hin Hwa Goh, Rui Huang
  • Publication number: 20130134602
    Abstract: A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: Invensas Corporation
    Inventors: Kazuo Sakuma, Ilyas Mohammed, Philip Damberg
  • Patent number: 8450137
    Abstract: The present invention discloses a method for reducing the tilt of a transparent window during manufacturing of an image sensor. The method includes the following steps: providing a semimanufacture of the image sensor; carrying out a preheating process; carrying out an adhesive spreading process; carrying out a transparent window closing process; and carrying out a packaging process. By carrying out the preheating process, the environmental conditions can be stabilized during the adhesive spreading process and the transparent window closing process such that the transparent window can be kept highly flat after combining. By the implementation of the present invention, the chance of tilt and crack of the transparent window during manufacturing of the image sensor can be reduced, thereby achieving the goal for a better yield rate.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: May 28, 2013
    Assignee: Kingpak Technology Inc.
    Inventors: Chun-Hua Chuang, Yao-Nien Chuang, Tiao-Mu Hsu, Chien-Wei Chang, Chien-Hen Lin, Chen-Pin Peng, Chung-Hsien Hsin
  • Patent number: 8445328
    Abstract: The invention relates to a method for producing chip elements provided with a groove, comprising the following steps: on an interconnect substrate, providing a conductive track arranged to connect a contact area of an active surface of a chip to an area corresponding to a first wall of the groove; growing a contact bump by electrodeposition on the conductive track at the level of the area corresponding to the first wall of the groove; assembling the chip on the substrate via its active surface so that a side wall of the chip forms the bottom of the groove; machining the chip via its rear surface in parallel to the substrate while measuring the distance between the rear surface of the chip and the contact bump; stopping machining when the measured distance reaches a required value; and assembling by bonding a plate to the rear surface of the chip so as to form a second wall of the groove.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: May 21, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Jean Brun, Régis Taillefer
  • Patent number: 8445322
    Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 21, 2013
    Assignee: SK Hynix Inc.
    Inventors: Woong Sun Lee, Qwan Ho Chung
  • Patent number: 8445899
    Abstract: Provided is an organic electronic panel wherein warping (deformation) of a metal member is suppressed when the metal member is used as a packaging board, an electrical short-circuit due to the warping is eliminated, and generation of light emission failure and deterioration of power generating performance are eliminated. In the organic electronic panel, the packaging board is composed of a metal foil, and a polymer film is laminated on the metal foil surface on the reverse side of the side having the adhesive layer. The thickness of the polymer film is not more than that of the metal foil, and heat is applied at the time of bonding/laminating the packaging board or at the time of hardening the adhesive layer.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: May 21, 2013
    Assignee: Konica Minolta Holdings, Inc.
    Inventors: Masaaki Murayama, Kazuo Genda, Takahiko Nojima
  • Patent number: 8445327
    Abstract: A wafer-level packaging process of a light-emitting diode is provided. First, a semiconductor stacked layer is formed on a growth substrate. A plurality of barrier patterns and a plurality of reflective layers are then formed on the semiconductor stacked layer, wherein each reflective layer is surrounded by one of the barrier patterns. A first bonding layer is then formed on the semiconductor stacked layer to cover the barrier patterns and the reflective layers. Thereafter, a carrying substrate having a plurality of second bonding layers and a plurality of conductive plugs electrically insulated from each other is provided, and the first bonding layer is bonded with the second bonding layer. The semiconductor stacked layer is then separated from the growth substrate. Next, the semiconductor stacked layer is patterned to form a plurality of semiconductor stacked patterns. Next, each semiconductor stacked pattern is electrically connected to the conductive plug.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: May 21, 2013
    Assignee: Lextar Electronics Corp.
    Inventors: Chia-En Lee, Cheng-Ta Kuo, Der-Ling Hsia
  • Patent number: 8445990
    Abstract: A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: May 21, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang