Abstract: A fabrication method of a chip scale package includes: disposing a chip on a carrier board and embedding the chip into a composite board having a hard layer and a soft layer; and removing the carrier board so as to perform a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, chip deviation and contamination, etc., all of which may result in poor electrical connection between the wiring layer and the chip electrode pads in the subsequent RDL process and even waste products as a result.

Abstract: A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices, the second lead forming the second external electrode; and cutting the sealing member between the plurality of semiconductor devices to separate

Abstract: Technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of the material constituting a wiring substrate is provided. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Abstract: A device includes a die having: at least one of an electronic device and a microelectromechanical system, a package substrate, an electrically nonconductive interposer disposed between the die and the package substrate, at least a first adhesive layer disposed between the package substrate and the electrically nonconductive interposer, and at least a second adhesive layer disposed between the die and the electrically nonconductive interposer.

Abstract: A method of making a semiconductor chip assembly includes providing a post, a base, an ESD protection layer and a metal layer, wherein the post extends above the base and the ESD protection layer is sandwiched between the base and the metal layer, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the post with an aperture in the conductive layer, then flowing the adhesive upward between the post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, providing a heat spreader that includes the post, the base, the ESD protection layer and an underlayer that includes at least a portion of the metal layer, then mounting a semiconductor device on the post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: One embodiment of a semiconductor package described herein includes a substrate having a first through-hole extending therethrough; a conductive pattern overlying the substrate and extending over the first through-hole; a first semiconductor chip facing the conductive pattern such that at least a portion of the first semiconductor chip is disposed within the first through-hole; and a first external contact terminal within the first through-hole and electrically connecting the conductive pattern to the first semiconductor chip.

Abstract: According to an embodiment, an integrated circuit package comprises a chip, a thermal component, and a molding compound. The chip comprises an active surface and a backside surface opposite the active surface. The thermal component is physically coupled to the backside surface of the chip. The molding compound encapsulates the chip, and an exposed surface of the thermal component is exposed through the molding compound. Another embodiment is a method to form an integrated circuit package.

Abstract: To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device. A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.

Abstract: Disclosed is a method for bonding semiconductor substrates, wherein an eutectic alloy does run off the bonding surfaces during the eutectic bonding. Also disclosed is an MEMS device which is obtained by bonding semiconductor substrates by this method. Specifically, a substrate (11) and a substrate (21) are eutectically bonded with each other by pressing and heating the substrate (11) and the substrate (21), while interposing an aluminum-containing layer (31) and a germanium layer (32) between a bonding part (30a) of the substrate (11) and a bonding part (30b) of the substrate (21) in such a manner that the aluminum-containing layer (31) and the germanium layer (32) overlap each other, with an outer edge (32a) of the germanium layer (32) being inwardly set back from the an outer edge (31a) of the aluminum-containing layer (31).

Abstract: Encapsulated radio frequency identification (RFID) articles having enhanced break strength and/or temperature resistance and methods of making these articles. The RFID articles include an RFID tag embedded within a thermoplastic substrate to form the RFID article. In one embodiment, the RFID article includes an over-molded barrier material that enables the RFID article to have enhanced temperature resistance such that the articles are able to sustain repeated exposure to high temperatures and/or sterilization procedures, thereby enabling the RFID articles to be utilized in applications heretofore unavailable. In other embodiments, the RFID articles are made using an injection molding process that provides very thin encapsulated RFID tags that also exhibit an increased level of temperature resistance.

Abstract: An assembly includes a support element and a chip having contact elements. The chip is mounted onto the support element with the contact elements facing the support element. A shield layer is on the support element for electrically or magnetically shielding a circuit element of the chip.

Abstract: Disclosed herein is a method of transferring elements, including the steps of: holding a plurality of elements made at a first pitch on an element formation substrate on a temporary holding substrate in a state; forming a plurality of element mounting bases and obtaining an element disposition substrate; disposing an uncured adhesive agent layer on each of the bearing surfaces of the element mounting bases; making the temporary holding substrate and the element disposition substrate close to each other and causing some of the plurality of elements to come in contact with the uncured adhesive agent layer; curing the uncured adhesive agent layer, fixing the elements contacting the adhesive agent layer to the element mounting bases; and separating the temporary holding substrate and the element disposition substrate from each other with the elements contacting the adhesive agent layer being left on the respective element mounting bases.

Abstract: A manufacturing method for a mounting structure of a semiconductor package component, including: applying a first adhesive with viscosity ?1 and a thixotropy index T1 at a position on the substrate, which is on an outer side of the mounted semiconductor package component; applying, on the first adhesive, a second adhesive with viscosity ?2 and a thixotropy index T2 so that the second adhesive gets in contact with an outer periphery part of the semiconductor package component; and forming, through a subsequent reflow process, a first adhesive part of the hardened first adhesive and a second adhesive part of the hardened second adhesive, wherein the first and second adhesives satisfy 30??2??1?300 (Pa·s) and 3?T2?T1?7, and sectional area S1 of the first adhesive part and sectional area S2 of the second adhesive part with respect to a direction perpendicular to a mounting surface of the substrate satisfy a relation S1?S2.

Abstract: An embodiment is directed to an IC mounting assembly that comprises an IC device having a first planar surface, wherein multiple electrically conductive first terminals are located at the first surface. The assembly further comprises an IC device mounting platform having a second planar surface in closely spaced relationship with the first surface, wherein multiple electrically conductive second terminals are located at the second surface, each second terminal corresponding to one of the first terminals. A solder element extends between each first terminal and its corresponding second terminal, and a constraining element is fixably joined to the second surface, wherein the constraining element has a CTE which is selectively less than the CTE of the mounting platform at the second surface. The constraining element is provided with a number of holes or apertures, and each hole is traversed by a solder element that extends between a first terminal and its corresponding second terminal.

Abstract: A chip is bonded onto a flat face of a first support through a first bonding layer with a terminal surface of the chip turned toward the flat face of the first support. A second support is bonded onto the chip through a second bonding layer. The first support is peeled from the chip to expose the terminal surface of the chip. An insulating layer from which the terminal surface of the chip is exposed is formed on the second support.

Abstract: In a method is for producing through contacts in thin chips, whose functionality is implemented in a layer structure starting from the surface layer of a semiconductor substrate, to separate these chips, the surface layer is structured using the layer structure and at least one cavity is produced below the surface layer, so that the individual chips are defined by trenches opening into the cavity and the individual chips are connected via support elements in the area of the cavity to the substrate below the cavity. The chips are provided with through contacts, in that firstly a contact hole, which extends through the entire layer structure of the chip and opens into a support element, is produced for each through contact. At least one dielectric layer is applied to the thus structured layer structure and in particular to the wall of the contact holes and structured in accordance with the electrical connections to be created between areas of the chip surface and at least one through contact.

Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

Abstract: A manufacturing method of a package structure is provided. A seed layer is formed on a upper surface of a metal substrate. A patterned dry film layer is formed on a lower surface of the metal substrate and the seed layer. A portion of the seed layer is exposed by the patterned dry film layer. The patterned dry film layer is used as an electroplating mask to electroplate a circuit layer on the portion of the seed layer exposed by the patterned dry film layer. A chip is bonded to and electrically connected to the circuit layer. A molding compound is formed on the metal substrate. The molding compound encapsulates the chip, the circuit layer and the portion of the seed layer. A portion of the metal substrate and a portion of the seed layer are removed so as to expose a portion of the molding compound.

Abstract: Exemplary embodiments are directed to a power electronic device with an electronic device including a substrate, a metal layer formed on the substrate and a field grading means located along an edge of the metal layer. The field grading means has a non-linear electrical resistivity.

Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

Abstract: A substrate structure for an image sensor package includes a bottom base and a frame layer. The bottom base has an upper surface formed with a plurality of first electrodes, and a lower surface formed with a plurality of second electrodes. An insulation layer is coated between the first electrodes and in direct surface contact with the upper surface of the bottom base. A frame layer is arranged on and in direct surface contact with the first electrodes and the insulation layer to form a cavity together with the bottom base. The insulation layer is interposed between the bottom base and the frame layer.

Abstract: An integrated circuit package includes a package module formed from successive build-up layers which define circuit interconnections, a cavity formed on a top-side of the package module, a chip having a front side with forward contacts and having a back-side, the chip disposed such that in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and a top layer coupled to the back-side of the chip covering at least a part of the chip and the top-side of the package module.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Abstract: Disclosed herein is a power semiconductor module. The module includes metal plates each having a first through hole, with an anodic oxidation layer formed on a surface of metal plates and an interior of the first through hole. A cooling member has a second through hole at a position corresponding to the first through hole, and the metal plates are attached to both sides of the cooling member. A circuit layer is formed on the anodic oxidation layer and performs an interlayer connection through a via formed in the first and second through holes. A power device is connected to the circuit layer. A resin encapsulant encloses the circuit layer and the power device. A housing is installed to each of the metal plates to form a sealing space for the resin encapsulant.

Abstract: A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions.

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post, a base, an ESD protection layer and an underlayer. The conductive trace includes a pad and a terminal. The semiconductor device is electrically connected to the conductive trace, electrically isolated from the underlayer and thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive, the base extends laterally from the post and the ESD protection layer is sandwiched between the base and the underlayer. The conductive trace provides signal routing between the pad and the terminal.

Abstract: A multifunction tape for a semiconductor package and configured to bond to a device-formed side of a semiconductor substrate having a plurality of devices thereon while performing a process of grinding a side of the semiconductor substrate opposite to the device-formed side and a process of dicing the semiconductor substrate into individual chips with a dicing tape having a UV-curable adhesive layer bonded to the ground side of the semiconductor substrate, the multifunction tape being bonded to the individual chips while the individual chips, separated from each other by the dicing process, are picked up and die-attached and a method of manufacturing a semiconductor device using the same, the multifunction tape including a base film; a UV-curable adhesive layer on one side of the base film; and first and second bonding layers on the adhesive layer.

Abstract: A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover.

Abstract: An epoxy resin composition having excellent connection reliability and transparency, a method for manufacturing a composite unit using the epoxy resin composition, and the composite unit, are disclosed. The manufacturing method includes an attaching step of attaching an epoxy resin composition (2) containing a novolak phenolic curing agent, an acrylic elastomer composed of a copolymer containing dimethylacrylamide and hydroxylethyl methacrylate, an epoxy resin and not less than 5 parts by weight to not more than 20 parts by weight of an inorganic filler to 100 parts by weight of the epoxy resin, to a printed circuit board (1) in the form of a sheet.

Abstract: An embedded electronic component semiconductor package structure and a packaging process thereof are provided. By providing two or more preformed building blocks, the electronic component can be assembled to the joined building blocks to obtain the embedded component semiconductor package structure.

Abstract: Multiple semiconductor device components and passive device components fixed to a substrate are embedded within an electroconductive-film/insulating-resin-film structure, and are thermally bonded to an insulating resin film.

Abstract: According to an embodiment, a semiconductor device includes: a conductive base plate; a semiconductor chip bonded on the conductive base plate, a first adhesive agent disposed on a central part of a bonded surface between the semiconductor chip and the conductive base plate; and a second adhesive agent disposed on a peripheral part of the central part of the bonded surface between the semiconductor chip and the conductive base plate. A coefficient of thermal conductivity of the first adhesive agent is relatively higher than that of the second adhesive agent, and a bonding strength of the second adhesive agent is relatively higher than that of the first adhesive agent.

Abstract: A chip on film (COF) type semiconductor package is provided. The chip on film (COF) type semiconductor package includes a film, a plurality of leads formed on a surface of the film, a chip adhered to ends of the leads, an underfill layer filled within a space between the chip and the leads, and a heat dissipation layer adhered to an other surface of the film, the heat dissipation layer including a graphite material layer, a protection layer formed on a surface of the graphite material layer to cover the graphite material layer, and an adhesion layer formed on an other surface of the graphite material layer to adhere the heat dissipation layer to the other surface of the film.

Abstract: A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having a minimum thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements.

Abstract: A semiconductor device assembly includes a substrate and a semiconductor die adjacent to a first surface of the substrate. The substrate also includes a second surface opposite from the first surface, an opening extending from the first surface and the second surface, contact pads on the second surface, and substrate pads on the second surface, adjacent to the opening. Bond pads of the semiconductor die are aligned with the opening through the substrate. Intermediate conductive elements, such as bond wires, extend from bond pads of the semiconductor die, through the opening, to substrate pads on the opposite, second surface of the substrate. An encapsulant, which fills the opening and covers the intermediate conductive elements, protrudes beyond a plane in which the second surface of the substrate is located.

Abstract: A method for manufacturing a substrate for a semiconductor package includes the steps of attaching first and second insulation layers which have first surfaces and second surfaces and are formed with conductive layers on the first surfaces, by the medium of a release film which has adhesives attached to both surfaces thereof, such that the second surfaces of the first and second insulation layers face each other; forming first conductive patterns on the first surfaces of the first and second insulation layers by patterning the conductive layers; forming solder masks on the first surfaces of the first and second insulation layers including the first conductive patterns to open portions of the first conductive patterns; and separating the first and second insulation layers from each other by removing the release film.

Abstract: A die stack package is provided and includes a substrate, a stack of computing components, at least one thermal plate, which is thermally communicative with the stack and a lid supported on the substrate to surround the stack and the at least one thermal plate to thereby define a first heat transfer path extending from one of the computing components to the lid via the at least one thermal plate and a fin coupled to a surface of the lid and the at least one thermal plate, and a second heat transfer path extending from the one of the computing components to the lid surface without passing through the at least one thermal plate.

Abstract: An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.

Abstract: The invention includes: applying an anisotropic conductive resin including conductive particles only to a plurality of bumps of an electronic component; placing the electronic component above a main surface of a flexible wiring board via the anisotropic conductive resin; and pressurizing the electronic component to the wiring board and curing the anisotropic conductive resin applied to the plurality of bumps to join the plurality of bumps to the electrodes of the wiring board. This can prevent a defective mounting of the electronic component.

Abstract: A method of manufacturing an electronic system. One embodiment provides a semiconductor chip having a first main face and a second main face opposite to the first main face. A mask is applied to the first main face of the semiconductor chip. A compound is applied to the first main face of the semiconductor chip. The compound includes electronically conductive particles. The semiconductor chip is coupled to a carrier with the compound facing the carrier.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. Firstly, a semiconductor substrate having an active surface and a back surface is provided. The active surface is opposite to the back surface, and the semiconductor substrate includes at least one grounding pad disposed on the active surface. Secondly, at least one through silicon via is formed through the semiconductor substrate from the back surface to the active surface thus exposing the grounding pad. Then, a conductive layer is formed on the back surface of the semiconductor substrate and filled into the through silicon via to electrically connect to the grounding pad and the semiconductor substrate.

Abstract: A solid-state imaging device includes a semiconductor substrate, one or more wiring interlayer films disposed on or above the semiconductor substrate, and one or more metal wires embedded in the wiring interlayer films. The one or more wiring interlayer films are composed of a diffusion preventing material that prevents the diffusion of the metal wire.

Abstract: Methods for making a substrate for semiconductor packaging with improved warpage and an apparatus. A method includes providing on a die side of a substrate at least one flip chip mounted integrated circuit die. The substrate may include through substrate vias (TSVs). An underfill is dispensed between the integrated circuit die and the substrate. Initially the underfill is left uncured. A thermal interface material is provided on the upper surface of the at least one integrated circuit die. A heat sink is mounted over the integrated circuit die and in thermal contact with the thermal interface material. A thermal cure is performed to simultaneously cure the underfill material and the thermal interface material. In another embodiment, the thermal cure may simultaneously cure an adhesive mounting the heat sink to the substrate. Solder balls are disposed on a board surface of the substrate to form a ball grid array package.

Abstract: A method for making a stack of at least two stages of circuits, each stage including a substrate and at least one component and metallic connections formed in or on this substrate, the assembly of a stage to be transferred onto a previous stage including: a) ionic implantation in the substrate of the stage to be transferred through at least part of the components, so as to form a weakened zone, b) formation of metallic connections of the components, c) transfer and assembly of some of this substrate onto the previous stage, and d) a step to thin the transferred part of the substrate by fracture along the weakened zone.

Abstract: Disclosed is an adhesive composition used for adhesion of a semiconductor chip which contains a radiation polymerizable compound, a photoinitiator, and a thermosetting resin. When the adhesive composition forming an adhesive layer is brought to a B-stage by irradiation with light, the surface of the adhesive layer has a tack force of 200 gf/cm2 or less at 30° C. and 200 gf/cm2 or more at 120° C.

Abstract: A galvanic-isolated coupling of circuit portions is accomplished on the basis of a stacked chip configuration. The semiconductor chips thus can be fabricated on the basis of any appropriate process technology, thereby incorporating one or more coupling elements, such as primary or secondary coils of a micro transformer, wherein the final characteristics of the micro transformer are adjusted during the wafer bond process.

Abstract: A multi-surface compliant heat removal process that includes identifying components to share a heat rejecting device; applying non-adhesive film to the components; identifying a primary component of the components; and applying phase change material on each of the components, other than the primary component. The phase change material is placed on top of the non-adhesive film. The process also includes placing the heat rejecting device on the corresponding components and removing the heat rejecting device from the corresponding components. The phase change material and the non-adhesive film remain with the heat rejecting device. The process also includes reflowing the phase change material on the heat rejecting device; removing the non-adhesive film from the heat rejecting device; placing a heatsink-attach thermal interface material on the components; and placing the heat rejecting device on the corresponding components.

Abstract: The method for manufacturing a film-like adhesive according to the present invention includes: applying an adhesive composition comprising (A) a radiation-polymerizable compound, (B) a photoinitiator and (C) a thermosetting resin, and having a solvent content of 5% by mass or lower and being liquid at 25° C., on a base material to thereby form an adhesive composition layer; and irradiating the adhesive composition layer with light to thereby form the film-like adhesive.

Abstract: According to one embodiment, a semiconductor device includes a control element provided above a main surface of a substrate through a first adhesion layer, a second adhesion layer provided to cover the control element a first semiconductor chip provided on the second adhesion layer, a bottom surface area of the first semiconductor chip being larger than a top surface area of the control element, and at least one side of an outer edge of the control element projecting to an outside of an outer edge of the first semiconductor chip.

Abstract: The present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend interposing an adhesive sheet therebetween, a wire-bonding step of bonding wires to the semiconductor element, and a step of sealing the semiconductor element with a sealing resin, and in which the loss elastic modulus of the adhesive sheet at 175° C. is 2000 Pa or more.