Abstract: In a method of making a dual work function gate electrode of a CMOS semiconductor structure, the improvement comprising formation of the dual work function gate electrode so that there is no boron penetration in the channel region and no boron depletion near the gate oxide, comprising: a) forming a gate oxide layer over a channel of a nMOS site and over a channel of a pMOS site; b) forming an undoped polysilicon layer over the gate oxide layer; c) masking the pMOS site, forming an a-Si layer over the nMOS site using a first heavy ion implantation, and implanting arsenic solely into the a-Si layer; d) masking the nMOS site formed by step c), forming an a-Si layer over the pMOS site using a second heavy ion implantation, and implanting boron solely into the a-Si regions; e) laser annealing the nMOS and pMOS sites for a short time and at an energy level sufficient to melt at least a portion of the a-Si but insufficient to melt the polysilicon; and f) affecting cooling after laser annealing to convert a-Si into p

Abstract: A contact connection between a semiconductor chip and a substrate has a conductive adhesive extending between each contact of the chip and the substrate. The conductive adhesive includes a matrix component, a filler component, a hardener component and at least one decomposable component so that after curing at a curing temperature T1, the adhesive can be decomposed either by applying thermal energy at a temperature T2>T1 or by radiation so that the two contact surfaces can be separated smoothly. After separation the purposes of replacing a defective semiconductor chip, a second chip can be mechanically connected by applying the adhesive and curing it.

Abstract: A plurality of lead frames is supplied in lead frame by lead frame sequence. A curable adhesive, preferably a 505 Epoxy, is applied to one surface of each lead frame as it indexes through an application device. An attaching device attaches a device to each lead frame with the adhesive by holding the device in place to cure for a preselected period of time of about one second. Later, the lead frames have their edges trimmed and then are separated into separate lead frames.

Abstract: A method of manufacture of a semiconductor device comprises a step of providing an adhesive (30) between a semiconductor chip (20) and a substrate (10), a step of positioning electrodes (22) and leads (12) to oppose each other, and a step of applying pressure in the direction of making the gap between the semiconductor chip (20) and substrate (10) narrower, and on the substrate (10), in a region opposing the surface of the semiconductor chip (20) and avoiding the leads (12), a film (14) is formed with lower adhesion with the adhesive (30) than the substrate (10).

Abstract: Methods of forming solder ball contacts having dimensions of approximately 2.5 microns in diameter for use in C4-type connections. The methods form solder ball contacts using selective deposition of solder on metal contact pads of a device. The metal contact pads have exposed portions at the bottom of through holes. The through holes define the dimensions of the exposed portions of the metal contact pads, and serve to limit the dimensions of the resulting solder contact by limiting the area upon which deposition preferentially occurs. Subsequent reflow of the deposited solder forms a solder ball contact. Various devices, modules, systems and other apparatus utilizing such methods of forming solder ball contacts.

Abstract: A method of fabricating a chip scale package includes: preparing a wafer including a plurality of chips; forming an insulating layer on the upper surface of the wafer except in areas of two upper terminals of each chip; forming an upper conductive layer on the insulating layer so as to be connected to the upper terminals of the chips; forming a lower conductive layer on the lower surface of the wafer so as to be connected to a lower terminals of each chip; first dicing the wafer so that one side of the chip scale package is formed; forming electrode surfaces on side surfaces of the upper and the lower conductive layers which are defined by the side of the chip scale package formed in the first dicing step; dividing the upper conductive layer of each chip into two areas each connected to one of the two upper terminals; and second dicing the wafer into package units.

Abstract: A method and apparatus for manufacturing a coupon of material having aligned carbon nanotubes. The coupon having aligned carbon nanotubes may be used as a thermal interface device in a packaged integrated circuit device.

Abstract: A method for manufacturing a semiconductor device by bonding a first metal bump formed on a first semiconductor substrate and a second metal bump formed on a second semiconductor substrate together.

Abstract: This invention provides a mounting method for reliably connecting mounting components electrically. Specifically, an anisotropically conductive adhesive can be composed of crushable microcapsules and a second liquid in which the microcapsules are dispersed. Each microcapsule encloses a first liquid and a conductive particle. The first liquid can react with the second liquid at normal temperatures to cure the second liquid. This anisotropically conductive adhesive can be applied on a flexible printed circuit (FPC). Then, a drive IC is mounted and pressed on the FPC to crush the microcapsules between electrode pads provided on the drive IC and electrode pads provided on the FPC, thereby bonding the electrode pads. Subsequently, the anisotropically conductive adhesive is heated to plasticize a capsule wall of each microcapsule, thereby bonding the drive IC and the FPC.

Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.

Abstract: A mounting structure is formed by flip-chip mounting a semiconductor device onto a substrate. An electrical connecting portion of the semiconductor device is connected to an electrical connecting portion of the substrate by means of an electrically conductive adhesive. A region of the semiconductor device which is not involved in electrical connection is bonded to a region of the substrate which is not involved in electrical connection by means of an adhesive. A test of electrical properties is performed on the semiconductor device and the substrate which are connected to each other. If it is determined that the electrical properties are poor in the test, the semiconductor device is separated from the substrate after heating a bonding place of the adhesive up to a temperature higher than a glass transition point or a melting point of the adhesive. If it is determined that the electrical properties are good in the test, the semiconductor device and the substrate are sealed by means of a sealing resin.

Abstract: A semiconductor device in chip format having a chip which has at least one first insulating layer and electrical connection pads free of the insulating layer is described. On the first insulating layer, interconnects run from the electrical connection pads to base regions of external connection elements. A further applied insulating layer is provided with openings leading from the outside to the base regions of the external connection elements. In the openings there is a conductive adhesive, onto which small balls which are metallic at least on the outside are placed. The semiconductor element can also contain a solder paste instead of a conductive adhesive in the openings, and metallized small plastic balls are placed onto the solder paste. The invention furthermore relates to methods for producing the semiconductor device described.

Abstract: Double-sided etching techniques are disclosed for providing a semiconductor structure with one or more through-holes. The through-holes may be sealed hermetically such as by a feed-through metallization process. The feed-through metallization process may include using an electroplating technique and may provide electrical contact to an opto-electronic or integrated circuit encapsulated in a package with the semiconductor structure used as a lid.

Abstract: To provide a method of manufacturing an electronic part capable of reusing the remaining conductive particles and electrically connecting the electronic part to the counterpart substrate, a method of manufacturing an electronic part includes: forming a mask on an active surface of the wafer on which electrode pads of the electronic part are formed, the mask of a predetermined height having openings provided above the electrode pads, forming bumps inside of the openings of the mask provided above the electrode pads, the bumps having a height lower than that of the mask, scattering conductive particles above the active surface of the wafer, removing the conductive particles remaining on the surface of the mask, fixing the conductive particles on the surfaces of the bumps, removing the mask, and separating the electronic part from the wafer.

Abstract: Provided is an anisotropic conductive paste in which an aqueous solution obtained by admixing the anisotropic conductive paste with purified water has an ionic conductivity of 1 mS/m or less; the B stage-reduced composition has a viscosity of 50 to 10000 Pa.s at 80 to 100° C.; and the cured matter of the anisotropic conductive paste has a linear expansion coefficient of 10×10−5 mm/mm/° C. or less at 0 to 100° C., a heat deformation temperature Tg of 100° C. or higher, a water absorption coefficient of 2 mass % or less and a specific resistance of 1×109&OHgr;.cm or more.

Abstract: The semiconductor device comprises an insulation layer formed on surfaces of semiconductor chips where the electrodes are formed, and a wiring layer formed on the insulation layer. The wiring layer formed on the insulation layer and the electrodes of the semiconductor chips are electrically connected to each other via connection members, such as wire bumps, etc. formed on the electrodes of the semiconductor chip.

Abstract: A method of electrically interconnecting microelectronic elements comprises providing a first microelectronic element having contacts with protrusions and dipping the protrusions into a layer of bonding material. At least some of the bonding material is transferred onto the contacts. The contacts are bonded to conductive features of a second microelectronic element.

Abstract: In accordance with the present invention, there are provided adhesive compositions and methods for use thereof, comprising at least one maleimide-containing monomer, at least one cure initiator, and a plurality of spacer elements constructed from one or more organic polymers. Invention adhesive compositions are useful for controlling bond line thickness and planarity between a device and a substrate. Bond line thickness and planarity is largely determined by the size of the spacer elements in the adhesive composition.

Abstract: A bonded anisotropic conductive film fabricated using a plastic material and a plurality of conductive particles inside the plastic material. The plastic material is a thermal set material hardening after being raised to a first temperature. Each conductive particle inside the plastic material includes a conductive bead, a bonding layer and a flux layer. The bonding layer is formed over the conductive bead enclosing the conductive bead entirely. The flux layer is formed over the bonding layer. The bonding layer has a melting point at a second temperature where the second temperature is higher than the first temperature.

Abstract: A first substrate, a second substrate, an intermediate and a plurality of particles form a laminated structure. The first substrate has a first conjunction portion and a second conjunction portion, and the second substrate has a third conjunction portion and a fourth conjunction portion which are characterized by a first hardness. The intermediate is disposed between the first substrate and the second substrate. The particles provided with a second hardness greater than the first hardness are coated on the third conjunction portion to contact the first conjunction portion and coated on the fourth conjunction portion to contact the second conjunction portion. A height difference with reference to the base surface of the second substrate exists between the end surface of the third conjunction portion and the end surface of the fourth conjunction portion.

Abstract: A layer of an anisotropic material has a pair of substantially flat oppositely-directed major faces, a vertical direction extending between the faces and horizontal directions transverse to the vertical direction, the layer including a dielectric material and a plurality of conductive particles in the dielectric material. The particles are distributed non-uniformly in the horizontal directions so as to provide areas of high particle concentration interspersed with areas of low particle concentration.

Abstract: An integrated circuit, in particular from a chip, a wafer or a hybrid, to a substrate. A package is provided for the integrated circuit, which has a connection side, on which there are provided a plurality of connection regions for connection to the substrate. A corresponding plurality of connection regions are provided on the substrate, and elevated contact regions are provided on the connection regions of the package and/or the connection regions of the substrate. The elevated contact regions include a first group of contact regions and a second group of contact regions. A connection of the package to the substrate is created via the elevated contact regions. The elevated contact regions configured such that the first group of contact regions form a rigid connection and the second group of contact regions form an elastic connection between the package and the substrate. The invention likewise provides a corresponding circuit arrangement.

Abstract: A method of manufacturing an electronic component unit comprises the steps of forming a conductive pattern on a surface of a substrate, roughening a surface of a connecting area of said conductive pattern, printing an adhesive on the connecting area, connecting an electrode of an electronic component to the electroconductive adhesive on the connecting area, and drawing the adhesive at a temperature of 50-120° C.

Abstract: A method of making a microelectronic assembly includes providing a first microelectronic element having one or more conductive bumps, the conductive bumps including a first fusible material that transforms from a solid to a liquid at a first melting temperature, and providing a second microelectronic element having one or more conductive elements. The conductive bumps of the first microelectronic element are electrically interconnected with the conductive elements of the second microelectronic element using a second fusible material, the second fusible material having a second melting temperature that is lower than the first melting temperature of the first fusible material. During the electrically interconnecting step, the second fusible material is maintained at a temperature that is greater than or equal to the second melting temperature and less than the first melting temperature of the first fusible material.

Abstract: A light-emitting semiconductor component having: a semiconductor element containing an active layer, electrical contacts for impressing a current into the active layer (heat being generated at the active layer and at the electrical contacts during operation), and a carrier with a large thermal capacity for absorbing the heat generated during operation. The rear side of the semiconductor element is electrically and thermally connected to the carrier by a conductive adhesive. Recesses, which accommodate a part of the conductive adhesive when the semiconductor element is connected to the carrier, are provided in the rear side of the semiconductor element.

Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.

Abstract: A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The surface portion of the top protective layer includes electrical contact pads that are electrically connected with electrical contact pad extensions and with the integrated circuit. The second surface of the semiconductor substrate includes a multiplicity of backside electrical connectors that are in overlapping electrical contact with corresponding electrical contact pad extensions forming lap joint electrical connections between the backside electrical connectors and the corresponding electrical contact pad extensions. Methods for constructing such devices and connections are also disclosed.

Abstract: A method for packaging a multi-chip module includes the steps of: connecting connection terminals of a tape of an anisotropic conductive adhesive film, on which a circuit is patterned to bond pads of the chip by applying an adhesive on the tape, applying an adhesive on an upper surface of the chip, folding the tape and attaching the folded tape to the upper surface of the chip and forming a plurality of ball terminals on a lower surface of the tape, the ball terminals being electrically connected to the connection terminals of the tape. An individual chip scale package may be manufactured by repeating the above steps.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device supported by a substrate. The package also includes a heat spreader having a surface divided into a central area and a channel. The channel is recessed relative to said die area. The package also includes a thermal interface material layer disposed between the semiconductor device and the surface of the heat spreader to provide thermal conductivity between the semiconductor device and the heat spreader.

Abstract: A method of mounting a component in which a component is thermally press-bonded onto a substrate with a conductive adhesive. The method includes a substrate heating step in which the substrate is heated to a temperature which is 20° C.˜40° C. below the glass transition point of a bonding resin contained in the conductive adhesive, and a thermal press-bonding step in which the component is thermally press-bonded onto the substrate heated to the aforementioned temperature with the conductive adhesive.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: An electronic device includes an electronic part including at least one first electrode, a substrate including at least one second electrode, and at least one bump formed on the at least one first electrode and formed from an elastic conductive resin including a resin having rubbery elasticity, and an acicular conductive filler including a surface layer coated with one of gold, silver, nickel, and copper. The at least one first electrode and the at least one second electrode are electrically connected to each other by mechanically contacting the at least one bump with the at least one second electrode.

Abstract: A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for manipulation of the TCE of the material. These devices and composites made with these devices are in the categories of materials called “smart materials” or “responsive materials.” Another aspect of the present invention provides microdevices comprised of dual opposed bilayers of material where the two bilayers are attached to one another at the peripheral edges only, and where the bilayers themselves are at a minimum stress conditions at a reference temperature defined by the temperature at which the bilayers are formed.

Abstract: Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication there is first provided a first semiconductor substrate. There is then formed over the first semiconductor substrate at least one microelectronic device to form from the first semiconductor substrate a partially fabricated semiconductor integrated circuit microelectronic fabrication. Within the method there is also provided a second substrate. There is also formed over the second substrate, in inverted order, a dielectric isolated metallization pattern intended to mate with the partially fabricated semiconductor integrated circuit microelectronic fabrication.

Abstract: A chip scale package mainly comprises a substrate attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive film (ACF). The substrate is provided with a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads. A plurality of metal bumps provided on the contact pads of the substrate. The metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip through the ACF. The side portions of the substrate and the ACF are sealed in a package body. The present invention further provides a method of making the chip scale package at the wafer level. The method is characterized by attaching substrates onto the chips of a wafer one by one so as to greatly reduce the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield.

Abstract: A new method and assembly are provided for anchoring the heat spreader of a PBGA package to the substrate thereof. Anchor features are made part of the PBGA package. These anchor features are provided over the surface of the substrate of the PBGA package. The anchor features align with openings created in the heat spreader stand-off, thus allowing for quick and reliable positioning and anchoring of the heat spreader over the surface of the substrate of the package.

Abstract: Disclosed is an image sensor module applied to a thin image sensor device. A method of fabricating the image sensor module consists of the steps of forming a bump on a glass, attaching the glass to an image sensor at a wafer level, and firstly and secondly dicing the resulting structure. Therefore, the present invention is advantageous in that fabrication of an inferior image sensor module is reduced, thus improving a quality of the image sensor module, productivity of the image sensor module is improved because the image sensor module is fabricated at the wafer level, and a gold wiper process is omitted, thus reducing fabrication costs of the image sensor module.

Abstract: An anisotropic conductive compound is cured by exposing it to heat while in the presence of an AC magnetic field followed by a static, substantially homogeneous DC magnetic field.

Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.

Abstract: A plug-in type electronic control unit is comprised of a wiring board, a plurality of electronic parts mounted on one surface of the wiring board by utilizing a wireless bonding process, and a plug member mounted on the other surface of the wiring board by utilizing a wireless bonding process. It is possible to suppress the planar extent of the unit by such a laminated structure, and to suppress the extent of the unit in a laminating direction by the employment of the wireless bonding process. Thus, it is possible to achieve a reduction in size of the plug-in type electronic control unit.

Abstract: A three-dimensional stacked semiconductor package device includes first and second semiconductor package devices and a conductive bond. The first device includes a first insulative housing, a first semiconductor chip and a first conductive trace. The first insulative housing includes a peripheral ledge and a central portion that is recessed relative to the peripheral ledge, and the peripheral ledge and the central portion form a cavity. The first conductive trace includes a first terminal that extends through the central portion. The second device includes a second insulative housing, a second semiconductor chip and a second conductive trace. The second insulative housing includes a second bottom surface. The second conductive trace includes a second terminal that extends through the second bottom surface. The conductive bond contacts and electrically connects the terminals, and the second terminal extends into the cavity.

Abstract: A bonding method is provided in which an electronic component is connected via bumps to a substrate and the electronic component is packaged on the substrate. A surface of the substrate that packages the electronic component, a surface of the electronic component that is connected to the substrate, and a surface of the bumps undergo plasma processing. Subsequently, the bumps are heated to a temperature lower than a melting point of the bumps, and the substrate and the electronic component are compression bonded via the bumps.

Abstract: An integrated circuit package, and manufacturing method therefor, is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.

Abstract: A semiconductor chip is mounted in face-up disposition on a dielectric element, with thermally conductive but flexible elements disposed between the chip bottom surface and the top surface of the dielectric element so as to provide a compliant but thermally conductive path from the chip to a substrate which is bonded to the terminals. A spreader having coefficient of thermal expansion substantially equal to that of the chip overlies the front surface and constrains an encapsulant surrounding the leads so as to minimize shear deformation of the encapsulant.

Abstract: A semiconductor device comprising the bump containing magnetic body, magnetic body, the bump including non-magnetic body for at least partially covering the magnetic body, mixture of magnetic particles and non-magnetic particles and the bump including baked magnetic particles and baked non-magnetic particles.

Abstract: A method of curing adhesives of a die attach material to reduce the formation of voids at the resulting bondline, defined by the interface between the adhesive and the surface of a die being attached. The method includes applying a relatively high pressure, in addition to a relatively high temperature, to cure the adhesive material.

Abstract: A method and structure for conductively coupling a metallic stiffener to a chip carrier. A substrate has a conductive pad on its surface and an adhesive layer is formed on the substrate surface. The metallic stiffener is placed on the adhesive layer, wherein the adhesive layer mechanically couples the stiffener to the substrate surface and electrically couples the stiffener to the pad. The adhesive layer is then cured such as by pressurization at elevated temperature. Embodiments of the present invention form the adhesive layer by forming an electrically conductive contact on the pad and setting a dry adhesive on the substrate, such that the electrically conductive contact is within a hole in the dry adhesive. The electrically conductive contact electrically couples the stiffener to the pad. The curing step includes curing both the dry adhesive and the electrically conductive contact, resulting in the dry adhesive adhesively coupling the stiffener to the substrate.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: A novel method for production of and an apparatus for an encapsulated solid-state electrochemical device is disclosed. The present invention provides for electrical devices, such as, for example, thin-film batteries with sensitive chemistries that can survive environmental exposure while providing external electrical contact to the internal cell chemistry. The method of packaging of the present invention may include bonding one or more protective multi-layer laminates to the environmentally sensitive surfaces of an electronic device. The present invention may provide the advantage of avoiding entrapped air beneath the laminates.

Abstract: A SOC (Substrate-On-Chip) packaging process is disclosed. A layer of two-stage thermosetting mixture with solvent is coating on an upside of a substrate. Thereafter, the substrate is heated for removing solvent so that the two-stage thermosetting mixture becomes a B-stage dry adhesive film without solvent. Thus, the bonding pads of the chip are not covered by the dry adhesive film and a better operating flexibility is obtained in the SOC packaging process.