Abstract: The stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a second lead frame are attached to bonding-pad-disposed faces of the respective semiconductor chips. The inner lead of each lead frame is electrically connected to its corresponding bonding pad by means of metal wires. The inner lead of the first lead frame is also electrically connected to the second lead frame by utilizing a conductive adhesive material. A connecting hole is formed in the outer end of the inner lead for better electrical connection when soldered. The entire resultant structure is molded with an epoxy compound so as to expose a connecting part between the first and second lead frames and an outer lead of the second lead frame.

Abstract: In a method of producing a semiconductor laser apparatus, a conductive die-bonding paste is applied to a bonding surface in a predetermined position thereof and then preheated at a temperature equal to or higher than a temperature at which a diluent of the conductive die-bonding paste starts to transpire, but lower than a temperature at which the conductive die-bonding paste starts a thermosetting reaction. Then, with a semiconductor laser chip placed on the preheated conductive die-bonding paste, the latter is heated to be hardened. In the thus produced semiconductor laser apparatus, a highest position at which the conductive die-bonding paste adheres to end surfaces of the semiconductor laser chip is at a height of more than 0.01 mm from the bonding surface, but is below light-emitting points of the semiconductor laser chip.

Abstract: The invention relates to a method for the manufacture of a smart label web. The smart label web comprises smart labels placed one after another and/or side by side and comprising a circuitry pattern and an integrated circuit on a chip therein. In the method, an electrical contact is formed between the integrated circuit on a chip and the circuitry pattern of the smart label in the smart label web in such a way that a structural part separated from a separate carrier web and comprising an integrated circuit on a chip is attached to the smart label. The structural part contains a thermoplastic material whereby it is attached to the smart label.

Abstract: A method of mounting a component on a substrate includes applying a conductive adhesive on a contact pad joined to a substrate, aligning a component with the substrate such that at least one lead of the component is juxtaposed with the conductive adhesive, performing a partial cure of the conductive adhesive, testing performance of the component, and performing a full cure of the conductive adhesive. Another method includes the additional steps of applying a tacky film to the substrate and juxtaposing the component with the tacky film. When the testing in either embodiment shows a defective or misaligned component, the component may be replaced or repositioned by cold separation of the at least one component lead from the partially cured conductive adhesive. Optionally, additional conductive adhesive may be applied, when needed, before replacement or repositioning of a component.

Abstract: The present invention provides a method and apparatus for testing semiconductor wafers that is simple and allows testing prior to dicing so that the need to temporarily package individual dies for testing is eliminated. As a result, the number of manufacturing steps is reduced, thus increasing first pass yields. In addition, manufacturing time is decreased, thereby improving cycle times and avoiding additional costs. After testing, the wafer is diced into the individual circuits, eliminating the need for additional packaging. One form of the present invention provides an interposer substrate made of a ceramic material that has an upper and a lower surface. There are one or more first electrical contacts on the lower surface and one or more second electrical contacts on the upper surface. There are also one or more electrical pathways that connect the first and second electrical contacts.

Abstract: Wire bond packages which mount encapsulated semiconductor chips, such as plastic ball grid array (PBGA) packages providing for the mounting of so-called flip-chips. The chips are overlaid with a heat spreading thermally-conductive cap of a mesh-like material which is interstitially the filled with an adhesive to prevent delamination caused by mismatches in the coefficients of thermal expansion, which result in contractions which cause the entire package arrangement to warp, leading to delamination between an encapsulant and cap and resulting in failure of connect joints and the ball grid arrays.

Abstract: A method of manufacturing a semiconductor device (10) including a semiconductor element (1), such as a transistor, which is provided, on the rear side, with a conductive layer (3) including gold, and which is attached, on said side, to a conductive plate (2), such as a lead frame (2), by way of a silver-containing organic matrix (4) which is thermally cured. Subsequently, the element (1) is connected to the plate (2) by way of wire connectors (5) and provided with an encapsulation (6). The silver paste (4) is cured at a temperature of at least 350° C., preferably approximately 400° C. In this way, an excellent adhesion of the element (1) to the plate (2) is obtained, enabling the wired connectors (5) to be subsequently provided by way of wire bonding without elements (1) becoming detached from the plate (2). Moreover, the connection is still sufficiently flexible to deal with a difference in thermal expansion between the element (1) and the plate (2), even if the latter is made of copper.

Abstract: A wafer-level packaging process for MEMS applications, and a MEMS package produced thereby, in which a SOI wafer is bonded to a MEMS wafer and the electrical feed-throughs are made through the SOI wafer. The method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the SOI substrate is removed to expose the buried oxide portion of the SOI substrate.

Abstract: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.

Abstract: A semiconductor device is provided which includes a semiconductor chip, a base member for mounting the chip, anisotropic conductive adhesive arranged between the chip and the base member, and a package for enclosing the chip and the adhesive. The chip is secured to the base member not only by the adhesive but also by the package.

Abstract: An electronic component includes an electronic component element and a package to house the electronic component element. The package includes a concave area in which the electronic component element is housed, an area for a sealing frame which is located along the periphery of the concave area, and a sealing cover which is mounted on the area for a sealing frame so as to cover the concave area. Connecting electrodes are electrically connected to the electronic component element and a conductive pattern to be used for image recognition is provided on the upper surface of the area for a sealing frame.

Abstract: An anisotropic conductive film 2 is superimposed on a circuit face 1a of a semiconductor wafer 1, and sandwiched and depressurizably surrounded with a flexible film 3 and a rigid plate 4 (or two flexible films) in the laminating direction, followed by depressurization of the surrounded interior by pressurizing at least in the laminating direction and heating the laminate as is from the outside, thereby joining the semiconductor wafer and the anisotropic conductive film, to produce a semiconductor wafer with an anisotropic conductive film. By forming an inhibiting layer on the rear face of a semiconductor wafer, the inhibiting layer warps in the direction antagonizing an expansion-shrinkage force produced on the anisotropic conductive film, and the warping of the entirety can be inhibited.

Abstract: A semiconductor packaging technology is proposed for the fabrication of a chip-on-chip (COC) based multi-chip module (MCM) with molded underfill. The proposed semiconductor packaging technology is characterized by the provision of a side gap of an empirically-predetermined width between the overlying chips mounted through COC technology over an underlying chip to serve as an air vent during molding process. This allows the injected molding material to flow freely into the flip-chip undergaps during molding process. In actual application, the exact width of the side gap is empirically predetermined through molded-underfill simulation experiments to find the optimal value. Based on experimental data, it is found that this side gap width should be equal to or less than 0.3 mm to allow optimal underfill effect. The optimal value for this side gap width may be varied for different package specifications.

Abstract: In the present invention, provided are a semiconductor device having a semiconductor-element-mounting substrate on which a semiconductor element has been mounted via an adhesive having an exothermic-reaction curing start temperature of 130° C. or below as measured with a differential scanning calorimeter at a heating rate of 10° C./minute, and a process for its fabrication.

Abstract: A micro-electromechanical (MEM) process for fabrication of integrated multi-frequency communication passive components is fused into co-fired ceramics by way of “flip chip” for fabrication of a low-cost, high-performance, and high-reliability hybrid communication passive component applicable in the frequency range of 0.9 GHz˜100 GHz. The basic structure of the passive component is a double-layer substrate comprising a low-loss ceramic or glass bottom-layer substrate and a glass or plastic poly-molecular top-layer substrate and an optional ceramic substrate at the lowest layer. As the materials used and the processing temperature in the MEM process is compatible with the CMOS process, thus this invention is fit for serving as a post process following the CMOS process.

Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.

Abstract: In the forms of a flip-chip package in which the contact elements of the chip are ultrasonically welded to the contact elements of the substrate, either the chip or the substrate or both are provided, prior to juxtaposition, with a bonding material which can be ultrasonically activated. During the ultrasonic welding process in which the contact elements of the chip and substrate are bonded together, the bonding material provides an additional attachment between the chip and substrate and eliminates the need for underfilling.

Abstract: The present invention relates to a method for controlling the formation of the intermetallic compounds in solder joints, The types of the intermetallic compounds between the SnAgCu solders and the Ni-bearing substrate can be controlled by adjusting the copper concentration in the SnAgCu solders. If the SnAgCu solder has a copper concentration higher than or equivalent to 0.6 wt. %, the soldering intermetallic compound includes a continuous (Cu1−xNix)6Sn5 layer. If the copper concentration of the SnAgCu solders is lower than or equivalent to 0.4 wt. %, the soldering intermetallic compound includes a continuous (Ni1−yCuy)3Sn4 layer and a non-continuous (Cu1−xNix)6Sn5 layer. If the copper concentration of the SnAgCu solders is between 0.4 wt. % to 0.6 wt. %, the soldering intermetallic compound includes the continuous (Cu1−xNix)6Sn5.

Abstract: There are provided an adhesive for connecting a circuit to be interposed between substrates having circuit electrodes thereon opposed to each other and to electrically connect the circuit electrodes on the substrates opposed to each other to the pressurizing direction under pressure, wherein the adhesive contains a compound having an acid equivalent of 5 to 500 KOH mg/g, and an adhesive for connecting a circuit to be interposed between substrates having circuit electrodes opposed to each other and to electrically connect the electrodes on the substrate opposed to each other to the pressurizing direction under pressure, wherein the adhesive comprises a first adhesive layer and a second adhesive layer, and a glass transition temperature of the first adhesive layer after pressure connection is higher than the glass transition temperature of the second adhesive layer after pressure connection.

Abstract: FILE: 8289USF.RTF19A chip structure comprises a wafer, an insulation layer, some conductive paste, a plurality of ball pads, a solder mask and a plurality of solder balls. The wafer has an active surface. The insulation layer is formed over the active surface of the wafer. The insulation layer has a plurality of open windows. The conductive paste fills the open windows. The ball pads are formed over the insulation layer in electrical connection with the conductive paste. The solder mask formed over the insulation layer. The solder mask exposes the ball pads. A solder ball is mounted to each ball pad.

Abstract: A method for transferring layers containing semiconductor devices and/or circuits to substrates other than those on which these semiconductor devices and/or circuits have been originally fabricated. The method comprises fabricating the semiconductor devices and/or circuits, coating them with a protective layer of photoresist followed by coating with a layer of wax. A special perforated structure is then also wax coated and the waxed surface of the structure is brought into a contact with the waxed surface of photoresist. The original seed substrate is removed and the exposed surface is then coated with adhesive followed by dissolving wax through the openings in the perforated structure and attaching the layer with semiconductor devices and/or circuits to another permanent substrate. As an alternative, a disk-shaped water-soluble structure can be used instead of the perforated structure.

Abstract: A method of mounting a component on a substrate includes applying a conductive adhesive on a contact pad joined to a substrate, aligning a component with the substrate such that at least one lead of the component is juxtaposed with the conductive adhesive, performing a partial cure of the conductive adhesive, testing performance of the component, and performing a full cure of the conductive adhesive. Another method includes the additional steps of applying a tacky film to the substrate and juxtaposing the component with the tacky film. When the testing in either embodiment shows a defective or misaligned component, the component may be replaced or repositioned by cold separation of the at least one component lead from the partially cured conductive adhesive. Optionally, additional conductive adhesive may be applied, when needed, before replacement or repositioning of a component.

Abstract: The present invention includes electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive. In one embodiment, an electrical interconnection configured to electrically couple a first substrate and a second substrate includes: a bond pad of the first substrate having a male configuration; and a bond pad of the second substrate having a female configuration, the bond pad of the second substrate being configured to mate with the bond pad of the first substrate during electrical connection of the bond pads of the first substrate and the second substrate. A method of conducting electricity according to the present invention includes providing first and second bond pads individually defining a planar dimension; coupling the first and second bond pads at an interface having a surface area greater than the area of the planar dimension; and conducting electricity between the first and second bond pads following the coupling.

Abstract: CTE differentials between chips and organic dielectric carriers, boards or other substrates to which the chips are attached are accommodated with a layer of a thermoplastic material, preferably a thermotropic polymer whose physical properties can be altered by extrusion or other physical processes, such as liquid crystalline polyesters, that modifies the CTE of at least one component of the package and thereby reduces CTE differentials. The material may be applied to the entire surface of a chip carrier, printed circuit or other substrate, or form an interior layer of a multi-layered structure. It may also be applied to selected regions or areas on the surface of a carrier or other substrate where adjustment is required.

Abstract: A COF-use tape carrier for a semiconductor device has dummy leads not to be electrically connected to a semiconductor chip, in the proximity of an edge of an opening of a solder resist. The dummy leads are provided on an insulating tape, between adjacent two inner leads that are relatively widely spaced from each other. The dummy leads extend across the edge of the opening of the solder resist, so that one end of each dummy lead is located within the opening of the solder resist, while the other end of the dummy lead is located under the solder resist. A semiconductor chip is to be mounted on a chip-mounting region of the insulating tape.

Abstract: The present invention is related to a flip-chip-on-board (FCOB) assembly technology applicable for mounting large chips with high I/O count or small pitch, mounted on low-cost or low-grade substrates. The assembly technology uses both an isotropically conductive adhesive (ICA) and a non-conductive material (NCA) in the same assembly cycle. The thermocompression step establishes at the same time the electrical and mechanical interconnections and the curing of the adhesives.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: A first bump and a second bump are formed on the surface of a mounting board (substrate) so that the second bump is allowed to be higher than the first bump. A conductive adhesive member is transferred onto those bumps. A semiconductor substrate in which a mesa portion has been processed is mounted on the mounting board so that the first bump does not come into contact with an electrode on a top of the mesa portion directly while electrically connected to the electrode via the conductive adhesive member. In the semiconductor device in which the semiconductor substrate is mounted with an active surface processed to form the mesa portion facing the mounting board, the stresses applied to the mesa portion (a stress caused in mounting and a stress due to a heat cycle in use) are relieved, thus preventing deterioration of an element.

Abstract: A thick film circuit connection epoxy is provided for protecting connections of dissimilar metals in a thick film substrate from the effects of oxidation. In the fabrication of hybrid integrated circuits, aluminum leads on the integrated circuit die are connected to gold conductors on the thick film substrate by means of an ultrasonic weld. The present invention comprises disposing a silver-filled thermoplastic epoxy around the weld between the aluminum wire and the gold conductor. Physical and electrical integrity of the connection between the aluminum wire and the gold conductor is thus maintained, even if the weld fails due to oxidation at elevated operating temperatures.

Abstract: In a method of fabricating an integrated circuit chip, a circuit board unit is formed with a bore, a plurality of contact pads, and a plurality of positioning notches that correspond to the contact pads. A die is attached to a bottom surface of the circuit board unit, and solder pads on the die are wire-bonded to the contact pads using conductive wires that extend through the bore. Leads of a lead frame are inserted respectively into the positioning notches and are bonded to the contact pads. A plastic protective layer is then formed to encapsulate the circuit board unit and at least a portion of the lead frame.

Abstract: An apparatus and method is provided for forming a board-on-chip (BOC) package. An adhesive material including a carrier and microcapsules distributed in the carrier is used to bond a semiconductor component to a mounting surface in a BOC package. The microcapsules contain a hardener and/or a catalyst that, when combined with the carrier, initiate a bonding reaction. The contents of the microcapsules are released via application of an external influence, such as pressure or heat, when the bonding reaction is desired to begin. The use of microcapsules permits the formulation of adhesive blends with a substantially increased pot life, increased stability and reliability at high temperatures, and favorable low temperature reaction and bonding characteristics.

Abstract: A high throughput process line and method for underfilling an integrated circuit that is mounted to a substrate. The process line includes a first dispensing station that dispenses a first underfill material onto the substrate and an oven which moves the substrate while the underfill material flows between the integrated circuit and the substrate. The process line removes flow time (wicking time) as the bottleneck for achieving high throughput.

Abstract: The present invention includes circuits, methods of adhering an integrated circuit device to a substrate, and methods of forming a circuit. According to one aspect of the present invention, a method of forming a circuit includes: providing an integrated circuit device having an outer surface and a plurality of conductive bumps upon the outer surface; providing a substrate having a plurality of bond pads which correspond to respective ones of the conductive bumps; providing an electrically insulative adhesive over at least a portion of the outer surface of the integrated circuit device; and coupling the integrated circuit device and the substrate following the providing the adhesive, the coupling connecting the outer surface of the integrated circuit device with the substrate and forming a plurality of electrical interconnections comprising the conductive bumps and the bond pads.

Abstract: Disclosed herein is a semiconductor device, which comprises a semiconductor chip including, over one main surface thereof, first wirings, protective films formed so as to cover other portions excluding parts of the first wirings, flexible layers respectively formed on the protective films so as to exclude the parts of the first wirings, and second wirings having first portions respectively electrically connected to the parts of the first wirings, and second portions respectively drawn onto the flexible layers; a wiring board having third wirings over one main surface thereof; and an adhesive comprising a large number of conductive particles contained in an insulative resin, and wherein the semiconductor chip is bonded to the wiring board with the adhesive interposed therebetween in a state in which the one main surface thereof is face to face with the one main surface of the wiring board, and the second portions of the second wirings are respectively electrically connected to the third wirings with some of th

Abstract: The present invention provides a method, apparatus and system for building a wafer-interposer assembly. The method includes the steps of forming a redistribution layer (RDL) pad on a semiconductor wafer. The semiconductor wafer has a semiconductor die and the RDL pad has an electrical connection to the semiconductor die. A layer of epoxy is placed on the semiconductor wafer and on the RDL pad. The epoxy is then leveled generally parallel to the surface of the semiconductor wafer and removed from a portion of the RDL pad. An interposer pad is formed on the RDL pad where the epoxy was removed.

Abstract: Disclosed is a method for fabricating wafer-level flip chip packages using anisotropic conductive adhesive. A low-priced non-solder bump, such as a gold stud bump or an electroless nickel/gold bump, is formed on an I/O pad of each chip of a wafer obtained by semiconductor processes. An anisotropic conductive adhesive solution or film is applied onto the wafer, followed by dicing the wafer into individual chips. They are arranged on and heat-pressed against a substrate at 150° C. for 5 min with the aid of a flip chip bonder. Each of the chips is mechanically and electrically connected to the substrate via the anisotropic conductive adhesive. Thus, the method can accomplish low-priced flip chip packaging or chip size packaging simply using conventional packaging lines.

Abstract: A process for producing a semiconductor device comprises mounting of a semiconductor element on a circuit board via a thermosetting resin-based adhesive by means of a thermocompression process, wherein the thermocompression process is carried out under a first set of conditions (pressure=P1 and temperature=T1) designed to eliminate voids present in the adhesive, and subsequently under a second set of conditions (pressure=P2 and temperature=T2) designed to bring about curing of the thermosetting resin, provided that pressure P2 of the second set of conditions is set to a lower level than the pressure P1 of the first set of conditions.

Abstract: A surface mount area-array integrated circuit package is disclosed. The package consists of a package substrate having conductive vias and internal and external conductive traces, a semiconductor die electrically and mechanically connected to the top surface of package substrate, an area-array of conductive surface mount terminations electrically and mechanically connected to the bottom of the package substrate, and at least one adhesive mass. The at least one adhesive mass is located on the bottom of the package substrate and replaces the conductive terminations in the area(s) where the joint strain energy density is calculated to be the greatest. When mounted on a substrate, the at least one adhesive mass adheres the package to the substrate. Increased mechanical and electrical reliability is thus achieved.

Abstract: A semiconductor chip (105′) and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406). The semiconductor chip (105′) is formed by contacting a semiconductor wafer (105) attached to a tape (107) with an etchant while rotating the semiconductor wafer (105) within an in-plane direction at a high speed or reciprocating the wafer (105) laterally to uniformly etch the semiconductor wafer (105) thereby reducing the thickness thereof, and dicing the thus reduced wafer. The resultant thin chip (105′) is hot-pressed by means of a heating head (106) for bonding on the substrate (102). In this way, a thin semiconductor chip can be formed stably at low costs and bonded on a substrate without causing any crack of the chip, thereby obtaining a semiconductor device which is unlikely to break owing to the bending stress from outside.

Abstract: Methods of forming electrically conductive interconnections and electrically interconnected substrates are described. In one implementation, a first substrate having an outer surface is provided and a layer of material is formed thereover. Openings are formed within the layer of material and conductive masses are formed within the openings. A second substrate having conductive interconnect surfaces is provided. The conductive interconnect surfaces are then contacted with the conductive masses and deformed thereby. In one aspect, the interconnect surfaces are deformed in part by portions of the layer of material proximate the conductive masses. In another aspect, the layer of material is removed and the interconnect surfaces are deformed by the conductive masses themselves.

Abstract: A soldering method for attaching a chip and electronic devices to a chip carrier has a lengthening reflowing time when attaching the electronic devices. Because the pins of the electronic device connect to the chip carrier by solder, the solder between the electronic device and the chip carrier are oxidized, which forms a high melting point oxide layer on a surface of the solder. Therefore the solder connecting the electronic device with the chip carrier ensures that the electronic devices do not move on the chip carrier in the follow-up high temperature processes.

Abstract: A semiconductor device is proposed, in which a chip is placed in an opening penetratingly formed in a substrate in a manner as not to come into contact with the substrate, and an encapsulant formed on the substrate fills up the opening for encapsulating the chip. This arrangement of the chip accommodated in the substrate therefore reduces the overall height of the semiconductor device. Moreover, a plurality of conductive elements disposed on the substrate are also encapsulated by the encapsulant in a manner that, bottom sides of the conductive elements are exposed to outside of the encapsulant, and coplanarly positioned with a bottom side of the encapsulant. This therefore provides good planarity for a bottom side of the semiconductor device, allowing the semiconductor device to be well electrically connected to external devices. A method for fabricating the foregoing semiconductor device is also proposed.

Abstract: A method of manufacturing a semiconductor device comprises: a first step of interposing a thermosetting anisotropic conductive material 16 between a substrate 12 and a semiconductor chip 20; a second step in which pressure and heat are applied between the semiconductor chip 20 and the substrate 12, an interconnect pattern 10 and electrodes 22 are electrically connected, and the anisotropic conductive material 16 is spreading out beyond the semiconductor chip 20 and is cured in the region of contact with the semiconductor chip 20; and a third step in which the region of the anisotropic conductive material 16 other than the region of contact with the semiconductor chip 20 is heated.

Abstract: A microelectronic element is provided with small meniscus-shaped solder masses, and these masses are connected to deformable connecting elements such as flexible leads. The connections can be made under vacuum in a chamber or in a space enclosed in part by a flexible film. Atmospheric pressure on the flexible film can urge the components together during bonding. Temporary securements such as adhesive bonds between the microelectronic element and the component can hold the microelectronic element in place relative to the component while electrical connections are made by conductive bonding material such a solder.

Abstract: An electronic device comprising: a semiconductor chip having plural electrode pads on one main surface thereof; a wiring board having plural connection parts; and plural salient electrodes disposed respectively between the electrode pads of the semiconductor chip and the connection parts of the wiring board to provide electrical connections between the two, the salient electrodes being arranged in an array not providing balance of the semiconductor chip with respect to one main surface of the wiring board, the plural connection parts of the wiring board being arranged at a deeper position than one main surface of the wiring board in a depth direction from the one main surface.

Abstract: A flexible package fabrication method, which enables the IC chip packaging film and the inner lead automated bonding to be simultaneously done. The method includes the steps of preparing a base member, electroplating a circuit having inner leads, outer leads, test lines/test terminals on the base member, covering the top side of the circuit with a polyimide passivation film or layer of flexible solder protective paint, bonding the bumps of a bumped IC chip or passive element to the inner leads of the circuit by thermocompression bonding, removing the base member, and covering the bottom side of the circuit with a polyimide passivation layer or layer of flexible solder protective paint.

Abstract: The present invention, as embodied and broadly described, the present invention includes a semiconductor chip, a chip pad in a first area of the semiconductor chip, a stress-easing layer formed in a second area of the semiconductor chip, a conductive wire connecting the chip pad to the stress-easing layer. And an electrical conductor on the conductive wire over the stress-easing layer. And, the present invention includes the steps of forming a chip pad on a first area of a semiconductor chip, forming a stress-easing layer on a second area of the semiconductor chip, forming a conductive wire connecting the chip pad to the stress-easing layer, and forming a electrical conductor on the conductive wire over the stress-easing layer.

Abstract: An apparatus and method for evenly applying an atomized adhesive for bonding a die to a leadframe is disclosed. In one embodiment, the apparatus includes a hood in communication with an air supply and a vacuum plenum that encompass a semiconductor device component located in a target area during adhesive application so that the adhesive is selectively applied to specific portions of the leadframe or other semiconductor device component and adhesive is not allowed outside the system. A mask or stencil may be employed for further prevention of adhesive application to undesired areas. An air purge may be employed to direct the adhesive mist toward the component to be coated. In another embodiment, a fine adhesive spray is directed against the surface of the workpiece to be coated, selected areas being masked to prevent coating. Wafers may be coated as well as leadframes.

Abstract: According to a fabricating method of the present invention, a cap shaped cover plate having a concaved portion on the inner surface is mounted on the rear surface of a semiconductor chip. After solder bumps are formed on a connecting pad of a wiring substrate, a fluid resin layer is formed on the bump formed surface. Thereafter, the semiconductor chip with the cover plate adhered is mounted with a face down on the resin layer formed surface of the wiring substrate. The solder bumps on the chip side and the solder bumps on the substrate side are contacted. At that time, the peripheral portion of the cover plate is contacted and adhered to the wiring substrate. Thereafter, while the bumps on the chip side and the bumps on the substrate side are being heated, melted, and connected, the fluid resin layer on the wiring substrate is hardened. Thus, the space between the semiconductor chip and the wiring substrate (namely, the height of the bumps) is controlled to a predetermined value.

Abstract: A method of manufacturing a semiconductor device comprises: a first step of interposing a thermosetting anisotropic conductive material 16 between a substrate 12 and a semiconductor chip 20; a second step in which pressure and heat are applied between the semiconductor chip 20 and the substrate 12, an interconnect pattern 10 and electrodes 22 are electrically connected, and the anisotropic conductive material 16 is spreading out beyond the semiconductor chip 20 and is cured in the region of contact with the semiconductor chip 20; and a third step in which the region of the anisotropic conductive material 16 other than the region of contact with the semiconductor chip 20 is heated.