Abstract: In one embodiment, a method of forming a multi-die semiconductor device is provided. A plurality of dice is mounted on a semiconductor substrate, and neighboring ones of the dice are separated by a distance at which a first one of the neighboring dice will contact a meniscus of a flange of the neighboring die during underfill to form a capillary bridge between the neighboring dice. Solder bumps are reflowed to electrically connect contact terminals of the plurality of dice to contact terminals on a top surface of the substrate. Underfill is deposited along one or more edges of one or more of the plurality of dice. As a result of the capillary bridge formed between neighboring dice, flow of underfill is induced between the bottom surfaces of the neighboring dice and the top surface of the substrate. The dispensed underfill is cured.

Abstract: A heat dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted on a chip carrier. A heat sink is mounted on the chip, and includes an insulating core layer, a thin metallic layer formed on each of an upper surface and a lower surface of the insulating core layer and a thermal via hole formed in the insulating core layer. A molding process is performed to encapsulate the chip and the heat sink with an encapsulant to form a package unit. A singulation process is performed to peripherally cut the package unit. A part of the encapsulant above the thin metallic layer on the upper surface of the heat sink is removed, such that the thin metallic layer on the upper surface of the heat sink is exposed, and heat generated by the chip can be dissipated through the heat sink.

Abstract: A system for clamping a heat sink that prevents excessive clamping force is provided. The system may include a heat sink, a semiconductor device, a printed circuit board, and a cover. The semiconductor device may be mounted onto the circuit board and attached to the cover. The heat sink may be designed to interface with the semiconductor device to transfer heat away from the semiconductor device and dissipate the heat into the environment. Accordingly, the heat sink may be clamped into a tight mechanical connection with the semiconductor device to minimize thermal resistance between the semiconductor device and the heat sink. To prevent excessive clamping force from damaging the semiconductor device, loading columns may extend between the cover and the heat sink.

Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.

Abstract: A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.

Abstract: Embodiments discussed herein are directed to a power semiconductor packaging that removes heat from a semiconductor package through one or more cooling zones that are located in a laterally oriented position with respect to the semiconductor package. Additional embodiments are directed to circuit elements that are constructed from one or more modular power semiconductor packages.

Abstract: A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover.

Abstract: A method of manufacturing an integrated circuit package includes mounting a large panel leadframe having a substantially square shape to a ring. The large panel leadframe includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. An integrated circuit chip is attached to each of the die pads. An encapsulant material is applied over the integrated circuit chips and at least a part of the large panel leadframe. Each of the die pads and its corresponding leads are separated from the large panel leadframe to form individual integrated circuit packages. The steps of attaching the integrated circuit chips and applying the encapsulant material are performed while the large panel leadframe is mounted to a taped ring.

Abstract: A method of making a semiconductor chip assembly includes providing a bump and a ledge, mounting an adhesive on the ledge including inserting the bump into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the bump with an aperture in the conductive layer, then flowing the adhesive between the bump and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, then mounting a semiconductor device on the bump opposite a cavity in the bump, wherein a heat spreader includes the bump and a base that includes a portion of the ledge adjacent to the bump, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: An article of manufacture includes a semiconductor die (110) having an integrated circuit (105) on a first side of the die (110), a diffusion barrier (125) on a second side of the die (110) opposite the first side, a mat of carbon nanotubes (112) rooted to the diffusion barrier (125), a die attach adhesive (115) forming an integral mass with the mat (112) of the carbon nanotubes, and a die pad (120) adhering to the die attach adhesive and (115) and the mat (112) of carbon nanotubes for at least some thermal transfer between the die (110) and the die pad (120) via the carbon nanotubes (112). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.

Abstract: A memory element can include a memory layer formed between two electrodes; at least one element within the memory layer that is oxidizable in the presence of an electric field applied across the electrodes; and an inhibitor material incorporated into at least a portion of the memory layer that decreases an oxidation rate of the at least one element within the memory layer with respect to the memory layer alone. Methods of forming such a memory element are also disclosed.

Abstract: Thermally regulated semiconductor devices having reduced thermally induced defects are provided, including associated methods. Such a device can include a heat spreader having a monolayer of diamond particles within a thin metal matrix and a semiconductor material thermally coupled to the heat spreader. In one aspect, the coefficient of thermal expansion difference between the heat spreader and the semiconductor material is less than or equal to about 50%.

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace, a substrate and an adhesive. The heat spreader includes a post and a base. The conductive trace includes a pad, a terminal, a conductive pattern and first and second vias. The substrate includes the conductive pattern and a dielectric layer. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive and an aperture in the substrate, and the base extends laterally from the post. The conductive trace provides signal routing between the pad and the terminal using the conductive pattern and the vias.

Abstract: A method of producing a semiconductor module which includes a resin molded package and a coolant passage is provided. The resin molded package is made up of a thermosetting resin-made mold and a thermoplastic resin-made mold. The resin molded package is formed by making the thermoplastic resin-made mold, placing the thermoplastic resin-made mold and a semiconductor sub-assembly made up of a power semiconductor chip, heat spreaders, terminals, etc., and then forming the thermosetting resin-made mold. Specifically, the thermosetting resin-made mold is made after the thermoplastic resin-made mold, thereby creating a high degree of adhesion of the thermosetting resin-made mold to the thermoplastic resin-made mold before the thermosetting resin-made mold is hardened completely, thereby forming firmly an adhered interface between the thermosetting resin-made mold and the thermoplastic resin-made mold.

Abstract: A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.

Abstract: Provided are a semiconductor package of a semiconductor chip, a semiconductor module, an electronic system, and methods of manufacturing the same. The method includes mounting a semiconductor chip on a package substrate, forming a molding member on the semiconductor chip, forming via holes penetrating the molding member to expose a portion of a top surface of the semiconductor chip, the via holes being arranged in a lattice shape in a plan view, and forming thermally conductive via plugs in the via holes.

Abstract: An electronic assembly includes a workpiece, a through substrate via (TSV) die including a substrate and a plurality of TSVs, a topside and a bottomside having TSV connectors thereon. The TSV die is attached to the workpiece with its topside on the workpiece. A heat spreader having an inner open window is on the bottomside of the TSV die. Bonding features are coupled to the TSV connectors or include the TSV connectors themselves. The bonding features protrude from the inner open window to a height above a height of the top of the heat spreader that allows a top die to be bonded thereto.

Abstract: A microelectronic unit can include a lead frame and a device chip. The lead frame can have a plurality of monolithic lead fingers extending in a plane of the lead frame. Each lead finger can have a fan-out portion and a chip connection portion extending in the lead frame plane. The fan-out portions can have first and second opposed surfaces and a first thickness in a first direction between the opposed surfaces. The chip connection portions can have a second thickness smaller than the first thickness. The chip connection portions can define a recess below the first surface. The device chip can have a plurality of at least one of passive devices or active devices. The device chip can have contacts thereon facing the chip connection portions and electrically coupled thereto. At least a portion of a thickness of the device chip can extend within the recess.

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace, an adhesive and a support layer. The heat spreader includes a post, a base, an underlayer and a thermal via. The conductive trace includes a pad and a terminal. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive, the base extends laterally from the post, the support layer is sandwiched between the base and the underlayer and the thermal via extends from the base through the support layer to the underlayer. The conductive trace provides signal routing between the pad and the terminal.

Abstract: Provided is a double-sided cooling structure for a semiconductor device using a low processing temperature and reduced processing time utilizing solid phase diffusion bonding. The fabrication method for this system is provided. The semiconductor device 1 comprising: a mounting substrate 70; a semiconductor chip 10 disposed on the mounting substrate 70 and a semiconductor substrate 26, a source pad electrode SP and a gate pad electrode GP disposed on a surface of the semiconductor substrate 26, and a drain pad electrode 36 disposed on a back side surface of the semiconductor substrate 26 to be contacted with the mounting substrate 70; and a source connector SC disposed on the source pad electrode SP. The mounting substrate 70 and the drain pad electrode 36 are bonded by using solid phase diffusion bonding.

Abstract: A semiconductor package includes a substrate with a first surface on which a semiconductor device is mounted and a second surface opposite to the first surface, and a loop heat pipe including an evaporator and attached to the second surface of the substrate, wherein the substrate has a groove structure in the second surface, the groove structure being in contact with a porous wick provided in the evaporator.

Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.

Abstract: A method for forming a molded die assembly includes attaching a first major surface of a semiconductor die onto a package substrate; attaching a heat spreader to a second major surface of the semiconductor die, wherein the second major surface is opposite the first major surface, and wherein the semiconductor die, package substrate, and heat spreader form a die assembly; conforming a die release film to a transfer mold; closing the transfer mold around the die assembly such that the die release film is compressed against the heat spreader and a cavity is formed around the die assembly; transferring a thermoset material into the cavity; and releasing the die assembly from the die release film and the transfer mold.

Abstract: An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.

Abstract: A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.

Abstract: A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.

Abstract: A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Abstract: A package comprises a die stack having at least two stacked dies coupled for contactless communications with each other. At least one of the stacked dies has a substrate joined to its major face. The substrate has a plurality of conductive traces in or on the substrate for conducting power to the dies and for conducting heat from the dies. At least one conductive pillar is joined to at least one of the conductive traces on at least a first edge of the substrate, for conducting power to the at least one die and for conducting heat from the at least one die.

Abstract: At least a part of a heat radiation member (9) connected to a DRAM (11) for radiating heat of the DRAM (11) is exposed from a protection member (4) arranged to surround the DRAM and the heat radiation member (9) so as to protect the DRAM (11). Thus, it is possible to provide a semiconductor device having a preferable heat radiation performance.

Abstract: A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive.

Abstract: A semiconductor device has a substrate having a front surface, and a rear surface including a fin forming region and a peripheral region surrounding the fin forming region. An insulating substrate is disposed on the front surface of the substrate. A semiconductor chip is disposed on the insulating substrate. A plurality of fins is formed in the fin forming region, and a reinforcing member is formed on the substrate through a bonding member, so as to overlap the peripheral region.

Abstract: An optoelectronic component (1) is provided, having at least two connecters (2) for electrical contacting of the component (1), a housing body (3), in which the connecters (2) are embedded in places, a heat sink (4), which is connected to at least one connecter (2), wherein the housing body (3) is formed of a plastics material, the housing body (3) comprises an opening (30), in which the heat sink (4) is freely accessible in places, at least one optoelectronic semiconductor chip (5) is arranged in the opening (30) on the heat sink (4), and at least two of the connecters (2) each comprise a chip-end portion (2c), which faces the at least one optoelectronic semiconductor chip (5), wherein the chip-end portions (2c) of the at least two connecters (2) are arranged in a common plane.

Abstract: By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal material can be electrically insulating. Through silicon-vias (TSVs) can be constructed at certain locations to assist in heat dissipation away from thermally troubled locations.

Abstract: A power semiconductor module includes a baseplate having a top side, an underside, and a depression formed in the baseplate. The depression extends into the baseplate proceeding from the top side. A thickness of the baseplate is locally reduced in a region of the depression. The power semiconductor module further includes a circuit carrier arranged above the depression on the top side of the baseplate such that the depression is interposed between the circuit carrier and the underside of the baseplate.

Abstract: A thermally enhanced expanded wafer level ball grid array package. The expanded wafer level ball grid array package includes an integrated thermally conductive heat dissipater. In one embodiment the heat dissipater is positioned in close proximity to a non-active face of a die and is separated from the non-active face by a thermal interface material. In another embodiment the heat dissipater includes legs that displace the heat dissipater a short distance from the non-active die face, with the intervening space occupied by encapsulation material. In yet another embodiment, the thermal interface material exists between the non-active die face and the heat dissipater, but extends beyond the edge of the semiconductor die to also cover a portion of the encapsulation material. Methods for making the various embodiments of the expanded wafer level ball grid array package are also shown.

Abstract: A method of mounting a light emitting diode (LED) module (100) to a heat sink (102), the method comprising the steps of placing the LED module (100) in a hole (120) in the heat sink (102); and expanding a portion of the LED module (100) such that the LED module (100) is secured to the heat sink (102). The method provides a cost efficient way of securing an LED module to a heat sink where the mount has a high reliability over time.

Abstract: A method for manufacturing a multiple encapsulation integrated circuit package-in-package system includes: dicing a top integrated circuit wafer having a bottom encapsulant thereon to form a top integrated circuit die with the bottom encapsulant; positioning internal leadfingers adjacent and connected to a bottom integrated circuit die; pressing the bottom encapsulant on to the bottom integrated circuit die; connecting the top integrated circuit die to external leadfingers adjacent the internal leadfingers; and forming a top encapsulant over the top integrated circuit die.

Abstract: A semiconductor package, comprises an encapsulant which contains a semiconductor substrate, the package lower side being mountable on a surface. The semiconductor substrate backside is in close proximity of the semiconductor package lower side for improved thermal conductivity to the surface. The active side of the semiconductor substrate, facing the upper side of the semiconductor package, has a plurality of die contacts. A plurality of electrically conductive interconnects are connected to the die contacts and extend to the lower side of the semiconductor package for connecting the die contacts to the surface.

Abstract: A method for making a structure for thermal management of circuit devices. The method provides a first substrate and a second substrate where at least one of the first and second substrates includes a circuit element. The method forms in at least one of the first substrate and the second substrate an entrance through-hole extending through a thickness of the first substrate or the second substrate, forms in at least one of the first substrate and the second substrate an exit through-hole extending through a thickness of the first substrate or the second substrate, forms respective bonding elements on at least one of the first and second substrates, and bonds the first and second substrates at the respective bonding elements to form a seal between the first and second substrates and to form a first coolant channel in between the first and second substrates.

Abstract: The invention relates to thermally contacting a semiconductor component arrangement, wherein at least one of two heat conducting bodies disposed on opposite sides of the semiconductor component arrangement is brought into contact with a contact surface of the semiconductor component arrangement by means of a metal layer under the application of a force, wherein the metal layer melts during solidification of a locking agent, forming an adhesive bond between the two heat transfer bodies over the entire region thereof.

Abstract: A power electronic system with a cooling device, and a method for producing the system, comprising a plurality of submodules, each submodule having a first planar insulating material body, one first conductor track cohesively connected thereto, one power switch arranged on the conductor track, at least one internal connecting device composed of an alternate layer sequence of at least one electrically conductive film and at least one electrically insulating film, wherein at least one electrically conductive layer forms at least one second conductor track, and comprising external connection elements. In this case, the submodules are arranged cohesively or in a force-locking manner and in a manner spaced apart from one another with their first main surface on the cooling device. At least one second conductor track at least partially covers first conductor tracks of two submodules, electrically connects them to one another and covers an interspace between the submodules.

Abstract: A power semiconductor module includes a power semiconductor element formed with a plurality of control electrodes on one main surface, a first conductor plate bonded by way of a first solder material to one of the main surfaces of the power semiconductor element, and a second conductor plate bonded by way of a second solder material on the other main surface of the power semiconductor element. A first protrusion section protruding from the base section of the applicable first conductor plate and including a first protrusion surface formed over the upper side, is formed over the first conductor plate. A second protrusion section including a second protrusion surface formed facing opposite one of the main surfaces of the power semiconductor element. The first solder material is interposed between the power semiconductor element and the first conductor plate while avoiding the plural control electrodes.

Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

Abstract: A microelectronic package includes a substrate, first and second microelectronic elements, and a heat spreader. The substrate has terminals thereon configured for electrical connection with a component external to the package. The first microelectronic element is adjacent the substrate and the second microelectronic element is at least partially overlying the first microelectronic element. The heat spreader is sheet-like, separates the first and second microelectronic elements, and includes an aperture. Connections extend through the aperture and electrically couple the second microelectronic element with the substrate.

Abstract: A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel, and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel. Other embodiments are also disclosed and claimed.

Abstract: A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover.

Abstract: A method of making a support structure is provided. The method includes depositing a photoresist layer on a substrate of the support structure and patterning the photoresist layer. The method further includes etching the patterned photoresist layer. Etching the patterned photoresist includes forming a first group of through silicon vias (TSVs) configured to electrically connect a first surface of the substrate to a first electrical interface adjacent an opposite second surface of the substrate. Etching the patterned photoresist further includes forming a second group of TSVs configured to conduct thermal energy from the first surface of the substrate to a thermal interface adjacent the second surface of the substrate. A difference in cross-sectional area between TSVs in the first group of TSVs and TSVs in the second group of TSVs is less than 10%, and the first electrical interface is separated from the thermal interface.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a through hole; mounting an integrated circuit in the through hole, the integrated circuit having an inactive side and a vertical side; connecting a first interconnect in direct contact with the integrated circuit and the substrate; applying a wire-in-film adhesive around and above the integrated circuit leaving a portion of the vertical side and the inactive side exposed and covering a portion of the first interconnect; and mounting a chip above the integrated circuit and in direct contact with the wire-in-film adhesive.

Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. Contact pads are formed on a surface of the semiconductor die. The semiconductor die are separated to form a peripheral region around the semiconductor die. An encapsulant or insulating material is deposited in the peripheral region around the semiconductor die. An interconnect structure is formed over the semiconductor die and insulating material. The interconnect structure has an I/O density less than an I/O density of the contact pads on the semiconductor die. A substrate has an I/O density consistent with the I/O density of the interconnect structure. The semiconductor die is mounted to the substrate with the interconnect structure electrically connecting the contact pads of the semiconductor die to the first conductive layer of the substrate. A plurality of semiconductor die each with the interconnect structure can be mounted over the substrate.

Abstract: A semiconductor device includes an insulation layer, a first semiconductor element and a second semiconductor element which are disposed within the insulation layer, a frame which has higher thermal conductivity than the insulation layer and surrounds the first semiconductor element and the second semiconductor element via the insulation layer, and a wiring layer which is disposed over the insulation layer and includes an electrode which electrically connects the first semiconductor element and the second semiconductor element.