Abstract: A semiconductor device with efficient heat dissipating structures is disclosed. The semiconductor device includes a first semiconductor chip that is flip-chip mounted on a first substrate, a heat absorption portion that is formed between the first semiconductor chip and the first substrate, an outer connection portion that connects the first semiconductor chip to an external device and a heat conduction portion formed between the heat absorption portion and the outer connection portion to dissipate heat generated by the first semiconductor chip.

Abstract: A semiconductor module is manufactured by bonding a resin case having a first opening through which surfaces of main circuit terminals and control terminals are exposed, onto a metal heat-dissipating substrate onto which is bonded, a conductive-patterned insulating substrate onto which are bonded, semiconductor chips, the main circuit terminals, and the control terminals; inserting into and attaching to a second opening formed on a side wall constituting a resin case, a resin body having a nut embedded therein to fix the main circuit terminals and the control terminals; and filling the resin case with a resin material. A side wall of the first opening is tapered toward the surface thereof; a tapered contact portion contacting the tapered side wall is disposed on the control terminal; and the resin body having the embedded nut fixes the control terminal having a one-footing structure that is an independent terminal.

Abstract: An integrated circuit package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween and a semiconductor die mounted on the first surface of the substrate. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulant encapsulates the wirebonds and the semiconductor die. A heat spreader has a cap, at least a portion of the cap extending inwardly toward and being spaced from the semiconductor die. The encapsulant fills the space between the portion of the cap and the semiconductor die. The heat spreader further has at least one sidewall extending from the cap, the at least one sidewall disposed on the substrate. A ball grid array is disposed on the second surface of the substrate, bumps of the ball grid array being in electrical connection with ones of the conductive traces.

Abstract: An integrated circuit package system that includes: providing a first package including a first package first device and a first package second device both adjacent a first package substrate; and mounting and electrically interconnecting a second package over an electrical interconnect array formed on a substrate of the first package second device.

Abstract: A power semiconductor module includes: a circuit body having a power semiconductor element and a conductor member connected to the power semiconductor element; a case in which the circuit body is housed; and a connecting member which connects the circuit body and the case. The case includes: a first heat dissipating member and a second heat dissipating member which are disposed in opposed relation to each other while interposing the circuit body in between; a side wall which joins the first heat dissipating member and the second heat dissipating member; and an intermediate member which is formed on the periphery of the first heat dissipating member and connected to the side wall, the intermediate member including a curvature that is projected toward a housing space of the case.

Abstract: In a manufacturing technique for packaged semiconductor devices, a pre-form of a packaged semiconductor device is formed by a molding process which encapsulates the semiconductor device and its associated heat transfer component in a passivating material presenting a surface. The surface is then processed to at least remove excess passivating material and expose the heat transfer component. The processing may further remove a portion of the heat transfer component. The removal process may, for example, utilize a grinding and/or polishing process. The process may be controlled so as to expose or form a heat transfer surface of desired shape and size.

Abstract: An apparatus having a three-dimensional integrated circuit structure is described herein. The apparatus include an interposer for carrying a plurality of high and low-power chips. The high-power chips are attached and connected to one side of the interposer, while the low-power chips are attached and connected to the other side of the interposer. In generally, the high-power chips produce more heat than does the low-power chip during their operations. The interposer further include through silicon vias and redistribution layers for connecting the chips on both surfaces. In addition, the interposer assembly is attached and connected to a substrate layer, which is in turn attached and connected to a printed circuit board. In order to provide improve thermal management, the interposer surface carrying the high-power chips are oriented away from the circuit board. A heat spreader is attached to the back sides of the high-power chips for dissipating the heat.

Abstract: An electronic device for power applications and configured for being mounted on a printed circuit board is disclosed. The electronic device includes a semiconductor chip integrating a power component, and a package. The package comprises an insulating body embedding the semiconductor chip, and exposed electrodes for electrically connecting conductive terminals of the semiconductor chip to external circuitry in the printed circuit board. The electronic device is further configured to be fastened to a heatsink with a back surface of the insulating body in contact with a main surface of the heatsink for removing heat produced by the electronic device during the operation thereof. The insulating body lacks of a fixing portion in which a hole for receiving an insertable fastener element for the fastening of the electronic device to the heatsink is located.

Abstract: A method of manufacturing a modular semiconductor subassembly: providing at least one semiconductor subassembly having a modular sidewall element of modular dimensions and a semiconductor substrate base element coupled to the modular sidewall element that has at least one semiconductor element with a layout sized to be accommodated by modular dimensions of the modular sidewall element. If a modular package protective cover is to be used: providing the modular package protective cover configured to accommodate the semiconductor subassembly in accordance with a modular design; securing the semiconductor subassembly in the modular package protective cover to create a modular package assembly; and mounting the modular package assembly to a core, with a base side of the semiconductor substrate base element in contact with the core; otherwise: mounting the at semiconductor subassembly to the core, with the base side of the semiconductor substrate base element in contact with the core.

Abstract: An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die.

Abstract: The LED unit 100 comprises a plurality of the LED module 1 and the heat radiation plate. Each the LED module 1 comprises the LED chip and the package for incorporating the LED chip therein; the package has the electrical insulation property. Each the package comprises the sub-mount member which is located between the LED chip and the heat radiation plate and which has heat conductivity; these are integrally formed. The LED modules are arranged on the first surface of the heat radiation plate. This configuration makes it possible for the LED unit to efficiently disperse the heat in the LED chip 10 to the heat radiation plate.

Abstract: The semiconductor package as well as a method for making it and using it is disclosed. The semiconductor package comprises a semiconductor chip having at least one heat-generating semiconductor device and a volumetrically expandable chamber disposed to sealingly surround the semiconductor chip, the volumetrically expandable chamber filled entirely with a non-electrically conductive liquid in contact with the semiconductor device and circulated within the volumetrically expandable chamber at least in part by the generated heat of the at least one semiconductor device to cool the at least one semiconductor device.

Abstract: Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.

Abstract: A semiconductor device has a semiconductor die. An encapsulant is formed over the semiconductor die. A conductive micro via array is formed over the encapsulant outside a footprint of the semiconductor die. A first through-mold-hole having a step-through-hole structure is formed through the encapsulant to expose the conductive micro via array. In one embodiment, forming the conductive micro via array further includes forming an insulating layer over the encapsulant and the semiconductor die, forming a micro via array through the insulating layer outside the footprint of the semiconductor die, and forming a conductive layer over the insulating layer. In another embodiment, forming the conductive micro via array further includes forming a conductive ring.

Abstract: A method of converting power using a power semiconductor module includes conducting power to power semiconductor devices; converting the conducted power with the power semiconductor devices; conducting heat generated by the power conversion from the power semiconductor devices first through a conductive circuit layer, then through an insulating substrate, to a baseplate; and removing the heat from the baseplate. The conductive circuit layer and the baseplate are formed of a material with a coefficient of thermal expansion less than about 8.0×10=6/° C. and a density less than about 4 g/cm3.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a thermal spreader having graduated thermal expansion parameters. In some embodiments, the thermal spreader may have a first layer with a first coefficient of thermal expansion (CTE) and a second layer with a second CTE that is greater than the first CTE. Other embodiments may be described and/or claimed.

Abstract: The invention relates to an electronic component having a circuit integrated on a semiconductor substrate, and a heat-conducting connection of the substrate by soldering using a carrier serving as a heat sink, wherein the invention proposes depositing a first, thicker Au layer (23) in the conventional back-side metallization of the substrate, thereafter a barrier coating (24), and, as the last layer, a thinner, second Au layer (25), wherein the material of the barrier coating is selected such that the barrier coating prevents the penetration by means of a diffusion barrier of Sn or AuSn from a liquid Au—Sn phase in the region of the second Au layer into the first Au layer (23) during the soldering process. The layer sequence of the back-side metallization is also deposited in the pass-through openings of the substrate, wherein the surface of the second Au layer comprises a reduced coatablity for the solder material due to the material diffused out of the barrier coating.

Abstract: A metal plate on a multi-die LED emitter substrate or a metal plate on a metal-core printed circuit board (MCPCB) that attaches to the emitter substrate (or both plates) can be fabricated with a number of generally radial grooves, at least some of which extend to the peripheral edge of the plate. These grooves can provide channels that allow air to escape during solder-bonding processes, reducing the size and/or total area of solder voids and thereby improving thermal transfer between the emitter and the MCPCB.

Abstract: A chip package having a lead frame and a molded portion. The lead frame includes a thermal pad and at least one electrode. The molded portion partially encapsulates the at least one electrode such that it is exposed on a top surface but not on a bottom surface. A bottom surface of the thermal pad is exposed for direct securement to an external heat sink. The molded portion is disposed between the at least one electrode and the heat sink to prevent a short circuit.

Abstract: A semiconductor device includes an IGBT as a vertical semiconductor element provided between first, and second lead frames, in pairs, the first, and second lead frames being opposed to each other, first and second sintered-metal bonding layers provided on first and second bonding surfaces of the IGBT, in pairs, respectively, a through-hole opened in the second lead frame, and a heat-release member having a surface on one side thereof, bonded to a second sintered-metal bonding layer of the second bonding surface while a side (lateral face) of a surface of the heat-release member, on the other side thereof, being fitted into the through-hole. A solder layer is formed in a gap between an outer-side wall of the side of the surface of the heat-release member, on the other side thereof, and an inner-side wall of the through-hole.

Abstract: A semiconductor assembly includes a semiconductor device and a connecting structure. The semiconductor device includes an interconnect region over a semiconductor substrate and a pillar layer having a plurality of pillar contacts on the interconnect region. The pillar layer also includes a plurality of radial heat conductors that have at least a portion overlying a heat source that is within and overlies the semiconductor substrate. Each radial heat conductor extends a length radially from the heat source that is at least twice as great as the diameter of the pillars. The connecting structure includes a connecting substrate that supports a first corresponding pillar contact that is in contact with a first pillar contact of the plurality of pillar contacts. The first connecting structure further includes a heat conductor, supported by the substrate, in contact with a first radial heat conductor of the plurality of radial heat conductors.

Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.

Abstract: A method, system, and apparatus for cooling one or more devices through use of a cooling plate. An example system includes multiple heat generating devices coupled to a cooling plate, each through an individual thermal interface unit. The thermal interface unit includes a compressible solid pad with at least one surface having a plurality of projections carrying a flowable material. The thermal interface units are pressed between the heat generating devices and the cooling plate so that the flowable material is completely enclosed.

Abstract: A manufacturing method of a solid state light emitting element is provided. A plurality of protrusion structures separated to each other are formed on a first substrate. A buffer layer is formed on the protrusion structures and fills the gaps between protrusion structures. An epitaxial growth layer is formed on the buffer layer to form a first semiconductor stacking structure. The first semiconductor stacking structure is inverted to a second substrate, so that the first semiconductor epitaxial layer and the second substrate are connected to form a second semiconductor stacking structure. The buffer layer is etched by a first etchant solution to form a third semiconductor stacking structure. A second etchant solution is used to permeate through the gaps between the protrusion structures, so that the protrusion structures are etched completely. The first substrate is removed from the third semiconductor stacking structure to form a fourth semiconductor stacking structure.

Abstract: At least one feature pertains to an apparatus having passive thermal management that includes an integrated circuit die, a heat spreader thermally coupled to the integrated circuit die, a phase change material (PCM) thermally coupled to the heat spreader, and a molding compound that encases the heat spreader and the PCM. In one example, the heat spreader may include a plurality of fins, and at least a portion of the PCM is interposed between the plurality of fins. Another feature pertains to an apparatus that includes an integrated circuit die, and a molding compound having a phase change material intermixed therein. The resulting molding compound completely encases the die.

Abstract: A device comprises a semiconductor package including a first integrated circuit (IC) die including a plurality of through silicon vias (TSVs). The TSVs are formed of conductive material that extend through the first IC die from an outer surface on a first side of the die to an outer surface of a second side of the die. The package further includes first electrical connections contacting the first side of the first IC die, and second electrical connections contacting the second side of the first IC die. The first electrical connections are independent of the second electrical connections. Molding compound encapsulates the first IC die and the first and second electrical connections. The semiconductor package is mounted on a substrate so that the first and second sides of the IC die are oriented perpendicular to the substrate.

Abstract: A heat spreader that is configured to be attached to an integrated circuit substrate. The heat spreader includes a thermally conductive core and a heat spreader via that passes through the thermally conductive core. A connection point of the thermally conductive core is configured to form a solder connection to an integrated circuit substrate plug.

Abstract: A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.

Abstract: By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.

Abstract: An exemplary embodiment of the present invention provides a chip for use in fabricating a three-dimensional integrated circuit, the chip comprising a wafer, one or more metallic-filled, electrical vias, and one or more hollow, fluidic vias. The wafer can comprise a first surface and a second surface. The one or more metallic-filled, electrical vias can extend through the wafer. Each electrical via can be in electrical communication with an electrical interconnect proximate the first surface, providing electrical communication between chips in the integrated circuit. The one or more hollow, fluidic vias can extend through the wafer. Each fluidic via can be in fluid communication with a fluidic interconnect, providing fluid communication between adjacent chips in the integrated circuit. Each fluidic interconnect can comprise a first end proximate the first surface, a second end, and a cap proximate the second end, defining an air-filled space within the fluidic interconnect.

Abstract: A fabricating method of a semiconductor package structure is provided. A dielectric layer having a first surface and a second surface is provided. A patterned metal layer has been formed on the first surface of the dielectric layer. An opening going through the first and the second surfaces is formed. A carrier having a third surface and a fourth surface is formed at the second surface. A portion of the third surface is exposed by the opening of the dielectric layer. A semiconductor die having a joining surface and a side-surface is joined in the opening. At least a through hole going through the third and the fourth surfaces is formed. A metal layer having at least a heat conductive post extending from the fourth surface of the carrier to the through hole and disposed in the through hole and a containing cavity is formed on the fourth surface.

Abstract: Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.

Abstract: A semiconductor device includes a reinforcement plate having an accommodating hole and a through hole extending from a first surface to a second surface, a semiconductor chip including a chip core and a pad formed on a pad surface of the chip core, the semiconductor chip disposed in the accommodating hole with the pad surface flush with the first surface, the chip core having substantially the same thickness as the reinforcement plate and including a semiconductor substrate, a through-hole electrode disposed in the through hole, resin sealing the semiconductor chip and the reinforcement plate, a interconnection pattern disposed on the first-surface side of the reinforcement plate to connect between the through-hole electrode and the pad, and a interconnection pattern disposed on the second-surface side of the reinforcement plate to be connected to the through-hole electrode, wherein the reinforcement plate is made of the same material as the semiconductor substrate.

Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.

Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.

Abstract: According to the invention, a semiconductor device composite structure is provided which comprises an initial substrate with discreet, integrated devices and a heat removal structure. The heat removal structure comprises: a bond layer which is attached to the initial substrate or the devices, a heat removal structure which is attached on the bond layer and which consists of a material with a specific thermal conductivity which is at least double the level of the average specific heat conductivity of the initial substrate or the devices, and one or more metallic thermal bridges which thermally connect the devices with the heat removal structure via the bond layer. The thermal bridges are designed as vertical through connections (vias) through the bond and heat removal structure. The invention furthermore relates to an associated production method.

Abstract: Apparatus and methods for forming a heat spreader on a substrate to release heat for a semi-conductor package are disclosed. The apparatus comprises a substrate. A dielectric layer is formed next to the substrate and in contact with a surface of the substrate. A heat spreader is formed next to the substrate and in contact with another surface of the substrate. A passivation layer is formed next to the dielectric layer. A connection pad is placed on top of the passivation layer. The substrate may comprise additional through-silicon-vias. The contact surface between the substrate and the heat spreader may be a scraggy surface. The packaging method further proceeds to connect a chip to the connection pad by way of a connection device such as a solder ball or a bump.

Abstract: A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other; and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed.

Abstract: A package for a microelectronic die (110) includes a first substrate (120) adjacent to a first surface (112) of the die, a second substrate (130) adjacent to the first substrate, and a heat spreader (140) adjacent to a second surface (111) of the die. The heat spreader makes contact with both the first substrate and the second substrate.

Abstract: This invention discloses a mixed alloy lead frame for power semiconductor devices, which includes a plurality of heat sinks and a pin array; the heat sinks are made of the first material, with positioning holes on their upper parts and welding zones at the center of their lower parts, while the pin array is made of the second material, which is different from the first material, with a plurality of sets of terminals leading out from its upper end and lower end respectively. The heat sinks are positioned on the lead frame assembly welding plate, the pin is positioned in the area between the upper heat sinks and lower heat sinks on the lead frame assembly welding plate. The mixed alloy lead frame for power semiconductor devices in this invention improves the heat dissipation of lead frame, reduces the fabrication cost of lead frame, and enhances the flexibility of fabrication.

Abstract: A method includes forming a first oxide layer on a surface of an integrated heat spreader, and forming a second oxide layer on top surfaces of fins, wherein the fins are parts of a heat sink. The integrated heat spreader is bonded to the heat sink through the bonding of the first oxide layer to the second oxide layer.

Abstract: Semiconductor packages including a die pad, at least one connecting bar, at least one supporting portion, a plurality of leads, a semiconductor chip, a heat sink and a molding compound. The connecting bar connects the die pad and the supporting portion. The leads are electrically isolated from each other and the die pad. The semiconductor chip is disposed on the die pad and electrically connected to the leads. The heat sink is supported by the supporting portion. The molding compound encapsulates the semiconductor chip and the heat sink. Heat from the semiconductor chip is efficiently dissipated from the die pad through the connecting bar, through the supporting portion, and through the heat sink.

Abstract: An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates while including at least one electrical component (e.g., a power module) substantially therein to provide even further operational capabilities for the resulting package.

Abstract: A cold plate has a base plate connected to a cover to form an enclosure, with an inlet and outlet nozzle penetrating the enclosure for coolant flow. The base plate includes a top surface opposite a bottom surface, Where the top surface includes enhancements positioned within the enclosure under the cover. The base plate has an inlet trough and an outlet trough that serve as headers, so the inlet nozzle connects to the inlet trough, and coolant from the inlet trough can flow through the enhanced surface, collect in the outlet trough, and then exit the cold plate through the outlet nozzle. The enhanced surface includes enhancements that begin at a point in between the bottom surface and the top surface, and the enhancements extend to a point above the top surface. In another embodiment, electronic components can be soldered on a cold plate. The electronic component can be positioned in contact with the cold plate, and solid solder can be positioned at a contact point on the electronic component.

Abstract: A semiconductor assembly includes a semiconductor device and a connecting structure. The semiconductor device includes an interconnect region over a semiconductor substrate and a pillar layer having a plurality of pillar contacts on the interconnect region. The pillar layer also includes a plurality of radial heat conductors that have at least a portion overlying a heat source that is within and overlies the semiconductor substrate. Each radial heat conductor extends a length radially from the heat source that is at least twice as great as the diameter of the pillars. The connecting structure includes a connecting substrate that supports a first corresponding pillar contact that is in contact with a first pillar contact of the plurality of pillar contacts. The first connecting structure further includes a heat conductor, supported by the substrate, in contact with a first radial heat conductor of the plurality of radial heat conductors.

Abstract: Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module.

Abstract: Wafer level packaging (WLP) packages semiconductor dies onto a wafer structure. After the wafer level package is complete, individual packages are obtained by singulating the wafer level package. The resulting package has a small form factor suitable for miniaturization. Unfortunately conventional WLP have poor heat dissipation. An interposer with a thermal pad can be attached to the semiconductor die to facilitate improved heat dissipation. In one embodiment, the interposer can also provide a wafer substrate for the wafer level package. Furthermore, the interposer can be constructed using well established and inexpensive processes. The thermal pad attached to the interposer can be coupled to the ground plane of a system where heat drawn from the semiconductor die can be dissipated.

Abstract: Disclosed is a method for forming a thermal interface material for a semiconductor chip, comprising the steps of forming an initial layer on a substrate, the initial layer including carbon nanotubes and nano metal powder; arranging a semiconductor chip on the initial layer; and heat-treating the initial layer with a sintering temperature of the nano metal powder to obtain a thermal interface material of the carbon nanotubes and the nano metal powder.

Abstract: A method of forming a heat-dissipating structure for semiconductor circuits is provided. First and second semiconductor integrated circuit (IC) chips are provided, where the first and second semiconductor chips each have first and second opposing sides, wherein the first and second semiconductor IC chips are configured to be fixedly attached to a top surface of a substantially planar circuit board along their respective first sides. The respective second opposing sides of each of the first and second semiconductor IC chips are coupled to first and second respective portions of a sacrificial thermal spreader material, the sacrificial thermal spreader material comprising a material that is thermally conductive. The first and second portions of the sacrificial thermal spreader material are planarized to substantially equalize a respective first height of the first semiconductor chip and a respective second height of the second semiconductor chip.

Abstract: Package structures for integrating thermoelectric components with stacking chips are presented. The package structures include a chip with a pair of conductive through vias. Conductive elements are disposed one side of the chip contacting the pair of conductive through vias. Thermoelectric components are disposed on the other side of the chip, wherein the thermoelectric component includes a first type conductive thermoelectric element and a second type conductive thermoelectric element respectively corresponding to and electrically connecting to the pair of conductive through vias. A substrate is disposed on the thermoelectric component, wherein the thermoelectric component, the pair of conductive through vias and the conductive element form a thermoelectric current path. Therefore, heat generated from the chip is transferred outward through a thermoelectric path formed from the thermoelectric components, the conductive through vias and the conductive elements.